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A Simple Computer March, 2012

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A Simple Computer March, 2012 Cmpt 150 A Simple Computer March, 2012 A Simple Computer It’s time to assemble some pieces and create a computer. We’re not going to cover this in depth — many details will be swept under the rug — but at the end we should have a pretty good idea of how assembly language connects with the underlying hardware. Instruction Set Architecture The true specification for a CPU is the instruction set architecture (ISA). In plain language, the set of instructions that the CPU hardware is capable of recognising and executing. In the roughly 70 years since the first digital computers were constructed1 hardware and software have co-evolved to their present state. Today there are two broad classes of ISAs: e Complex Instruction Set (CISC) ISAs are the older class, evolved from the pe- riod when the guiding philosophy was a rich set of machine instructions that facilitated assembly language programming by humans and closely matched the requirements of evolving higher-level programming languages (e.g., For- tran and Cobol). The dominant CISC ISA today is the Intel x86 instruction set. e Reduced Instruction Set (RISC) ISAs are the newer class, evolving from the observation that the vast majority of assembly language today is written by compilers. RISC ISAs have a bare minimum of instructions, chosen to min- imise hardware complexity and maximise speed of execution. Multiple RISC instructions are often required to do the work of a single CISC instruction, but even so can be executed more quickly. Compilers and assemblers do the tedious work of translating programs in high-level language into machine instructions. RISC ISAs are also referred to as load/store instruction sets, because only load and store instructions can transfer data between the CPU registers and RAM memory. All other instructions operate on data in registers The dominant RISC ISAs today are the SPARC, MIPS, and PowerPC archi- tectures. 1Depending on where you want to start, the Atanasoff-Berry computer in 1937, the Harvard Mark I in 1944, or the Manchester SSEM in 1948. The SSEM was the first implementation of a computer where instructions and data were both stored in memory, the von Neumann architecture. 1 Cmpt 150 A Simple Computer March, 2012 It’s worth pointing out that Intel has put a huge amount of effort into speeding up the execution of their CISC ISA, and it can be argued that the resulting CPU hardware essentially translates the CISC instructions into RISC instructions on- the-fly for execution by the hardware. The ISA presented by Mano in Chapter 9 of the text is a RISC architecture. The ISA implemented in the HC12 is a CISC architecture. We’ll explore the differences when we’ve had a chance to look at both. A CPU implements an algorithm called the instruction execution cycle to pro- cess the instructions of a program. Here are the steps: 1. Instruction Fetch: Fetch the instruction from memory into the CPU for pro- cessing. 2. Instruction Decode: Inspect the instruction to see what operation it specifies, what operands it needs, and what it will do with the result. 3. Operand Fetch: Make the operands available to the appropriate functional unit for execution. 4. Operation Execution: Perform the operations specified by the instruction using the operands fetched in the previous step. 5. Store Result: Store the result of the operation. All instructions require fetch and decode, but some instructions do not need all of the last three steps. In that case, the hardware is instructed to perform an appropriate ‘no operation’ for that particular step. We’ll see how this is done shortly. The number of clock periods required to execute an instruction, and the length of the clock period, depend on the the details of the implementation. We will design a simple, but relatively slow, implementation. The Mano Simple Computer Instruction Set Table 1 shows the complete instruction set for the Mano Simple Computer. This is a RISC (load/store) instruction set, recognisable because only the load (LD) and store (ST) instructions can transfer data between the registers and mem- ory. All other instructions operate on data in the registers. Digital hardware understands only 1’s and 0’s, so the assembly language of Table 1 must be translated into machine language using the formats shown in Figure 1. Let’s consider a few examples: 2 Cmpt 150 A Simple Computer March, 2012 Operation Mnemonic Opcode Action Status Fmt Move A MOVA 0000000 R[DR] ¬ R[SA] N, Z R Increment INC 0000001 R[DR] ¬ R[SA] + 1 N, Z R Add ADD 0000010 R[DR] ¬ R[SA] + R[SB] N, Z R Subtract SUB 0000101 R[DR] ¬ R[SA] + R[SB] + 1 N, Z R Decrement DEC 0000110 R[DR] ¬ R[SA] − 1 N, Z R AND AND 0001000 R[DR] ¬ R[SA] ∧ R[SB] N, Z R OR OR 0001001 R[DR] ¬ R[SA] ∨ R[SB] N, Z R Exclusive-OR XOR 0001010 R[DR] ¬ R[SA] Å R[SB] N, Z R NOT NOT 0001011 R[DR] ¬ R[SA] N, Z R Move B MOVB 0001100 R[DR] ¬ R[SB]R Shift Right SHR 0001101 R[DR] ¬ sr R[SB]R Shift Left SHL 0001110 R[DR] ¬ sl R[SB]R Load Immediate LDI 1001100 R[DR] ¬ zf OP I Add Immediate ADI 1000010 R[DR] ¬ R[SA] + zf OP N, Z I Load LD 0010000 R[DR] ¬ M[R[SA]] R Store ST 0100000 M[R[SA]] ¬ R[SB]R Branch on Zero BRZ 1100000 if (R[SA] = 0) PC ¬ PC + se AD N,Z J if (R[SA] ¹ 0) PC ¬ PC + 1 Branch on Negative BRN 1100001 if (R[SA] < 0) PC ¬ PC + se AD N, Z J if (R[SA] ³ 0) PC ¬ PC + 1 Jump JMP 1110000 PC ¬ R[SA]J Where no PC assignment is specified, the instruction performs PC ¬ PC + 1. Table 1: Mano Simple Computer Instruction Set ([1, Table 9-8]) e Supppose that we want to subtract the contents of R[4] from R[5], placing the result in R[7]. In assembly language, we would write SUB R7, R5, R4 In machine language, this is an R format instruction: 15 9 8 6 5 3 2 0 0000101 111 101 100 e Supppose that we want to load R[6] with the constant 7. In assembly lan- guage, we would write LDI R6, 7 3 Cmpt 150 A Simple Computer March, 2012 15 9 8 6 5 3 2 0 Destination Source Source Opcode Register (DR) Register A (SA) Register B (SB) 15 9 8 6 5 3 2 0 Destination Source Opcode Operand (OP) Register (DR) Register A (SA) 15 9 8 6 5 3 2 0 Address (AD) Source Address (AD) Opcode Left Register A (SA) Right Figure 1: Machine Instruction Formats for the Mano Simple Computer ([1, Fig- ure 9-14]) In machine language, this is an I format instruction: 15 9 8 6 5 3 2 0 1001100 110 000 111 Note that the value of the RA field is not used; the actual value is unimpor- tant so it’s set to zero. e Supppose that we want to branch to PC − 5 if the value in R[3] is less than zero. In assembly language, we would write BRN R3, -5 In machine language, this is a J format instruction: 15 9 8 6 5 3 2 0 1100001 111 011 011 Remember that for a branch instruction, the values of the RD and RB fields are concatenated to form a six-bit two’s-complement value; in this case, −5 = 111011. To get an understanding of how all of this fits together, let’s consider the fol- lowing (Java) program fragment: int[] arrayOfInt = new int[7] ; for (int ndx = 6 ; ndx >= 0 ; ndx = ndx-1) arrayOfInt[ndx] = -ndx ; How could we implement this in the Simple Computer? There are a number of issues to consider: 4 Cmpt 150 A Simple Computer March, 2012 e Every data item requires space. We’ll have to identify some space in registers or memory to hold the values for ndx and arrayOfInt. And once we’ve decided on where to put them, we’ll have to figure out a way to create those values in our program. e Then there’s the matter of constructing the loop from the available instruc- tions. Let’s see how we might go about this. Suppose that I decide to place my array at location 42 in memory. I’ll need to set a register to the value 42 so that I can use it in a ST instruction. A quick glance at the instruction set is enough to see that the largest value I can specify as an immediate operand in an instruction is 7. How can I construct the value 42? One trick is to use shift left to multiply by 2. I can construct the value 42 as 8 ´ 5 + 2: LDI R7, 5 ; Load R7 with the seed SHL R7, R7 ; x 2 = 10 SHL R7, R7 ; x 2 = 20 SHL R7, R7 ; x 2 = 40 ADI R7, R7, 2 ; R7 now contains 42 This is more work that you might expect, and a practical instruction set will include the ability to specify immediate operands of a practical size (at least 16 bits) and the ability to shift by a variable amount. Even so, you may occasionally find yourself faced with a similar task. Another thing to take away from this example is that we need temporary reg- isters to hold intermediate values. If there are not enough registers, intermediate values must be stored in memory and recovered as needed.
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