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Mpc5xx/8Xx Debugger and Trace

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Mpc5xx/8Xx Debugger and Trace MPC5xx/8xx Debugger and Trace TRACE32 Online Help TRACE32 Directory TRACE32 Index TRACE32 Documents ...................................................................................................................... ICD In-Circuit Debugger ................................................................................................................ Processor Architecture Manuals .............................................................................................. PQ/MPC500 .............................................................................................................................. MPC5xx/8xx Debugger and Trace ....................................................................................... 1 Brief Overview of Documents for New Users ................................................................. 5 Warning .............................................................................................................................. 6 Quick Start ......................................................................................................................... 7 Target Design Requirement/Recommendations ............................................................ 9 General 9 RESET Configuration 10 BDM Termination 11 General Restrictions 12 Troubleshooting 13 SYStem.Up Errors 13 FAQ ..................................................................................................................................... 13 Configuration ..................................................................................................................... 14 Breakpoints ........................................................................................................................ 16 Software Breakpoints 16 On-chip Breakpoints 16 On-chip Breakpoints on InstructionsROM or FLASH 17 On-chip Breakpoints on Read or Write Accesses 17 Example for Breakpoints 17 Simultaneous FLASH Programming for MPC555 18 Memory Classes ................................................................................................................ 19 Memory Coherency MPC8xx 19 Trace Extension ................................................................................................................. 20 MPC555/MPC553 Pin Multiplexing 20 Troubleshooting MPC500/MPC800 RISC Trace 21 Used Options for RiscTrace 21 General SYStem Commands ............................................................................................ 22 ©1989-2020 Lauterbach GmbH MPC5xx/8xx Debugger and Trace 1 SYStem.BdmClock Define the BDM clock speed 22 SYStem.CONFIG Configure debugger according to target topology 22 SYStem.CPU Select CPU type 22 SYStem.CpuAccess Run-time memory access (intrusive) 23 SYStem.CpuBreak Master control to deny stopping the target (long stop) 23 SYStem.CpuSpot Master control to deny spotting the target (short stop) 25 SYStem.MemAccess Real-time memory access (non-intrusive) 26 SYStem.Mode Establish the communication with the CPU 27 CPU specific SYStem Commands ...................................................................................28 SYStem.LOADVOC Load vocabulary for code compression 28 SYStem.Option BRKNOMSK Allow program stop in a non-recoverable state 28 SYStem.Option CCOMP Enable code compression 29 SYStem.Option CLEARBE Clear MSR[BE] on step/go 29 SYStem.Option CSxxx CS setting for program flow trace 29 SYStem.Option DCREAD Use DCACHE for data read 30 SYStem.Option FAILSAVE Special error handling for debug port 31 SYStem.Option FreezePin Use alternative signal on the BDM connector 31 SYStem.Option IBUS Configure the show cycles for the I-BUS 32 SYStem.Option ICFLUSH Flush branch target cache before program start 32 SYStem.Option ICREAD Use ICACHE for program read 33 SYStem.Option IMASKASM Disable interrupts while single stepping 33 SYStem.Option IMASKHLL Disable interrupts while HLL single stepping 33 SYStem.Option LittleEnd Selection of little endian mode 34 SYStem.Option MMUSPACES Enable space IDs 34 SYStem.Option NODATA The external data bus is not connected to trace 35 SYStem.Option NOTRAP Use alternative instruction to enter debug mode 35 SYStem.Option OVERLAY Enable overlay support 36 SYStem.Option PPCLittleEnd Control for PPC little endian 36 SYStem.Option SCRATCH Scratch for FPU access 37 SYStem.Option SIUMCR SIUMCR setting for the trace 37 SYStem.Option SLOWLOAD Alternative data load algorithm 37 SYStem.Option SLOWRESET Activate SLOWRESET 37 SYStem.Option WATCHDOG Enable software watchdog after SYStem.Up 38 SYStem.state Display SYStem window 38 CPU specific MMU commands ......................................................................................... 39 MMU.DUMP Page wise display of MMU translation table 39 MMU.List Compact display of MMU translation table 41 MMU.SCAN Load MMU table from CPU 42 MMU.TLB Display MMU TLB entries 43 MMU.TLBSCAN Load MMU TLB entries 43 MMU.Set Set an MMU TLB entry 44 CPU specific TrOnchip Commands .................................................................................45 ©1989-2020 Lauterbach GmbH MPC5xx/8xx Debugger and Trace 2 TrOnchip.CONVert Adjust range breakpoint in on-chip resource 45 TrOnchip.DISable Disable NEXUS trace register control 45 TrOnchip.ENable Enable NEXUS trace register control 46 TrOnchip.G/H Define data selector 46 TrOnchip.IWx.Count Event counter for I-Bus watchpoint 47 TrOnchip.IWx.Ibus Instructions address for I-Bus watchpoint 48 TrOnchip.IWx.Watch Activate I-Bus watchpoint pin 48 TrOnchip.LW0.Count Event counter for L-Bus watchpoint 49 TrOnchip.LW0.CYcle Cycle type for L-Bus watchpoint 50 TrOnchip.LW0.Data Data selector for L-Bus watchpoint 50 TrOnchip.LW0.Ibus Instructions address for L-Bus watchpoint 50 TrOnchip.LW0.Lbus Data address for the L-Bus watchpoint 51 TrOnchip.LW0.Watch Activate L-Bus watchpoint pin 52 TrOnchip.RESet Reset on-chip trigger unit 52 TrOnchip.Set Stop program execution at specified exception 52 TrOnchip.TCompress Trace data compression 53 TrOnchip.TEnable Set filter for the trace 53 TrOnchip.TOFF Switch the sampling to the trace to OFF 54 TrOnchip.TON Switch the sampling to the trace to ON 54 TrOnchip.TTrigger Set a trigger for the trace 54 TrOnchip.VarCONVert Adjust HLL breakpoint in on-chip resource 54 TrOnchip.state Display on-chip trigger window 54 BenchMarkCounter ........................................................................................................... 56 BDM Connector ................................................................................................................. 57 10 pin BDM Connector MPC500/MPC800 57 Support ............................................................................................................................... 58 Available Tools 58 Compilers 59 Target Operating Systems 60 3rd-Party Tool Integrations 62 Products ............................................................................................................................. 64 Product Information 64 Order Information 64 ©1989-2020 Lauterbach GmbH MPC5xx/8xx Debugger and Trace 3 MPC5xx/8xx Debugger and Trace Version 21-Feb-2020 ©1989-2020 Lauterbach GmbH MPC5xx/8xx Debugger and Trace 4 Brief Overview of Documents for New Users Architecture-independent information: • “Debugger Basics - Training” (training_debugger.pdf): Get familiar with the basic features of a TRACE32 debugger. • “T32Start” (app_t32start.pdf): T32Start assists you in starting TRACE32 PowerView instances for different configurations of the debugger. T32Start is only available for Windows. • “General Commands” (general_ref_<x>.pdf): Alphabetic list of debug commands. Architecture-specific information: • “Processor Architecture Manuals”: These manuals describe commands that are specific for the processor architecture supported by your debug cable. To access the manual for your processor architecture, proceed as follows: - Choose Help menu > Processor Architecture Manual. • “OS Awareness Manuals” (rtos_<os>.pdf): TRACE32 PowerView can be extended for operating system-aware debugging. The appropriate OS Awareness manual informs you how to enable the OS-aware debugging. ©1989-2020 Lauterbach GmbH MPC5xx/8xx Debugger and Trace 5 Warning WARNING: To prevent debugger and target from damage it is recommended to connect or disconnect the debug cable only while the target power is OFF. Recommendation for the software start: 1. Disconnect the debug cable from the target while the target power is off. 2. Connect the host system, the TRACE32 hardware and the debug cable. 3. Power ON the TRACE32 hardware. 4. Start the TRACE32 software to load the debugger firmware. 5. Connect the debug cable to the target. 6. Switch the target power ON. 7. Configure your debugger e.g. via a start-up script. Power down: 1. Switch off the target power. 2. Disconnect the debug cable from the target. 3. Close the TRACE32 software. 4. Power OFF the TRACE32 hardware. ©1989-2020 Lauterbach GmbH MPC5xx/8xx Debugger and Trace 6 Quick Start Starting up the BDM Debugger is done by the following steps: 1. Select the device prompt B: for the TRACE32 ICD-Debugger, if the device prompt is not active after starting the TRACE32 software. B: 2. Select the CPU type to load the CPU specific settings. SYStem.CPU MPC563 The default CPU is the MPC860. 3. Inform the debugger where’s FLASH/ROM on the target, this is necessary for the use of the on- chip breakpoints. MAP.BOnchip 0x100000++0x0fffff On-chip breakpoints are now used, if a program or spot breakpoint is set within the specified address range. A list of all available on-chip
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