ARM Debugger TRACE32 Online Help TRACE32 Directory TRACE32 Index TRACE32 Documents ...................................................................................................................... ICD In-Circuit Debugger ................................................................................................................ Processor Architecture Manuals .............................................................................................. ARM/CORTEX/XSCALE ........................................................................................................... ARM Debugger ..................................................................................................................... 1 Warning .............................................................................................................................. 8 Introduction ....................................................................................................................... 9 Brief Overview of Documents for New Users 9 Demo and Start-up Scripts 10 Quick Start of the JTAG Debugger .................................................................................. 12 Troubleshooting ................................................................................................................ 14 Communication between Debugger and Processor can not be established 14 FAQ ..................................................................................................................................... 15 ARM 15 Trace Extensions ............................................................................................................... 18 Symmetric Multiprocessing ............................................................................................. 19 ARM Specific Implementations ........................................................................................ 20 Breakpoints 20 Software Breakpoints 20 On-chip Breakpoints for Instructions 20 On-chip Breakpoints for Data 20 Hardware Breakpoints (Bus Trace only) 21 Example for Standard Breakpoints 22 Complex Breakpoints 28 Direct ICE Breaker Access 28 Example for ETM Stopping Breakpoints 29 Trigger 30 Virtual Terminal 31 Semihosting 32 SVC (SWI) Emulation Mode 32 DCC Communication Mode (DCC = Debug Communication Channel) 34 Runtime Measurement 35 ©1989-2017 Lauterbach GmbH ARM Debugger 1 Coprocessors 36 Access Classes 38 TrustZone Technology 46 Debug Permission 46 Checking Debug Permission 47 Checking Secure State 47 Changing the Secure State from within TRACE32 47 Accessing Memory 47 Accessing Coprocessor CP15 Register 48 Accessing Cache and TLB Contents 48 Breakpoints and Vector Catch Register 48 Breakpoints and Secure Modes 48 Large Physical Address Extension (LPAE) 49 Consequence for Debugging 49 Virtualization Extension, Hypervisor 50 Consequence for Debugging 50 big.LITTLE 51 Debugger Setup 51 Consequence for Debugging 52 Requirements for the Target Software 52 big.LITTLE MP 52 ARM specific SYStem Commands ...................................................................................53 SYStem.CLOCK Inform debugger about core clock 53 SYStem.CONFIG.state Display target configuration 53 SYStem.CONFIG Configure debugger according to target topology 54 <parameters> describing the “DebugPort” 61 <parameters> describing the “JTAG” scan chain and signal behavior 66 <parameters> describing a system level TAP “Multitap” 70 <parameters> configuring a CoreSight Debug Access Port “DAP” 72 <parameters> describing debug and trace “Components” 76 <parameters> which are “Deprecated” 86 SYStem.CPU Select the used CPU 90 SYStem.CpuAccess Run-time memory access (intrusive) 92 SYStem.JtagClock Define JTAG frequency 93 SYStem.LOCK Tristate the JTAG port 95 SYStem.MemAccess Run-time memory access 96 SYStem.Mode Establish the communication with the target 100 SYStem.Option Special setup 103 SYStem.Option ABORTFIX Do not access memory area from 0x0 to 0x1f 103 SYStem.Option AHBHPROT Select AHB-AP HPROT bits 103 SYStem.Option AMBA Select AMBA bus mode 103 SYStem.Option ASYNCBREAKFIX Asynchronous break bugfix 104 SYStem.Option AXIACEEnable ACE enable flag of the AXI-AP 104 ©1989-2017 Lauterbach GmbH ARM Debugger 2 SYStem.Option AXICACHEFLAGS Select AXI-AP CACHE bits 104 SYStem.Option AXIHPROT Select AXI-AP HPROT bits 105 SYStem.Option BUGFIX Breakpoint bug fix 105 SYStem.Option BUGFIXV4 Asynch. break bug fix for ARM7TDMI-S REV4 106 SYStem.Option BigEndian Define byte order (endianness) 107 SYStem.Option BOOTMODE Define boot mode 107 SYStem.Option CINV Invalidate the cache after memory modification 108 SYStem.Option CFLUSH FLUSH the cache before step/go 108 SYStem.Option CacheParam Define external cache 108 SYStem.Option DACR Debugger ignores DACR access permission settings 109 SYStem.Option DAPDBGPWRUPREQ Force debug power in DAP 109 SYStem.Option DAP2DBGPWRUPREQ Keep forcing debug power in DAP2 110 SYStem.Option DAPSYSPWRUPREQ Force system power in DAP 110 SYStem.Option DAP2SYSPWRUPREQ Force system power in DAP2 111 SYStem.Option DAPNOIRCHECK No DAP instruction register check 111 SYStem.Option DAPREMAP Rearrange DAP memory map 112 SYStem.Option DBGACK DBGACK active on debugger memory accesses 113 SYStem.Option DBGNOPWRDWN DSCR bit 9 will be set in debug mode 113 SYStem.Option DBGUNLOCK Unlock debug register via OSLAR 113 SYStem.Option DCDIRTY Bugfix for erroneously cleared dirty bits 114 SYStem.Option DCFREEZE Disable data cache linefill in debug mode 114 SYStem.Option DEBUGPORTOptions Options for debug port handling 114 SYStem.Option DIAG Activate more log messages 115 SYStem.Option DisMode Define disassembler mode 116 SYStem.Option DynVector Dynamic trap vector interpretation 117 SYStem.Option EnReset Allow the debugger to drive nRESET (nSRST) 117 SYStem.Option ETBFIXMarvell Read out on-chip trace data 117 SYStem.Option ETMFIX Shift data of ETM scan chain by one 118 SYStem.Option ETMFIXWO Bugfix for write-only ETM register 118 SYStem.Option ETMFIX4 Use only every fourth ETM data package 118 SYStem.Option EXEC EXEC signal can be used by bustrace 118 SYStem.Option EXTBYPASS Switch off the fake TAP mechanism 119 SYStem.Option FASTBREAKDETECTION Fast core halt detection 119 SYStem.Option HRCWOVerRide Enable override mechanism 119 SYStem.Option ICEBreakerETMFIXMarvell Lock on-chip breakpoints 120 SYStem.Option ICEPICK Enable/disable assertions and wait-in-reset 120 SYStem.Option ICEPICKONLY Only ICEPick registers accessible 121 SYStem.Option IMASKASM Disable interrupts while single stepping 121 SYStem.Option IMASKHLL Disable interrupts while HLL single stepping 121 SYStem.Option INTDIS Disable all interrupts 122 SYStem.Option IRQBREAKFIX Break bugfix by using IRQ 122 SYStem.Option KEYCODE Define key code to unsecure processor 122 SYStem.Option L2Cache L2 cache used 123 ©1989-2017 Lauterbach GmbH ARM Debugger 3 SYStem.Option L2CacheBase Define base address of L2 cache register 123 SYStem.Option LOCKRES Go to 'Test-Logic Reset' when locked 123 SYStem.Option MACHINESPACES Address extension for guest OSes 124 SYStem.Option MEMORYHPROT Select memory-AP HPROT bits 125 SYStem.Option MemStatusCheck Check status bits during memory access 125 SYStem.Option MMUSPACES Enable space IDs 125 SYStem.Option MonitorHoldoffTime Delay between monitor accesses 126 SYStem.Option MPU Debugger ignores MPU access permission settings 127 SYStem.Option MultiplesFIX No multiple loads/stores 127 SYStem.Option NODATA No data connected to the trace 127 SYStem.Option NOIRCHECK No JTAG instruction register check 128 SYStem.Option NoPRCRReset Do not cause reset by PRCR 128 SYStem.Option NoRunCheck No check of the running state 128 SYStem.Option NoSecureFix Do not switch to secure mode 129 SYStem.Option OVERLAY Enable overlay support 129 SYStem.Option PALLADIUM Extend debugger timeout 130 SYStem.Option PC Define address for dummy fetches 130 SYStem.Option PROTECTION Sends an unsecure sequence to the core 130 SYStem.Option PWRCHECK Check power and clock 131 SYStem.Option PWRCHECKFIX Check power and clock 131 SYStem.Option PWRDWN Allow power-down mode 131 SYStem.Option PWRDWNRecover Mode to handle special power recovery 132 SYStem.Option PWRDWNRecoverTimeOut Timeout for power recovery 132 SYStem.Option PWROVR Specifies power override bit 132 SYStem.Option ResBreak Halt the core after reset 133 SYStem.Option ResetDetection Choose method to detect a target reset 134 SYStem.Option RESetREGister Generic software reset 134 SYStem.Option RESTARTFIX Wait after core restart 135 SYStem.Option RisingTDO Target outputs TDO on rising edge 135 SYStem.Option ShowError Show data abort errors 135 SYStem.Option SOFTLONG Use 32-bit access to set breakpoint 136 SYStem.Option SOFTQUAD Use 64-bit access to set breakpoint 136 SYStem.Option SOFTWORD Use 16-bit access to set breakpoint 136 SYStem.Option SPLIT Access memory depending on CPSR 136 SYStem.Option StandByTraceDelaytime Trace activation after reset 137 SYStem.Option STEPSOFT Use software breakpoints for ASM stepping 137 SYStem.Option SYSPWRUPREQ Force system power 137 SYStem.Option TIDBGEN Activate initialization for TI derivatives 138 SYStem.Option TIETMFIX Bug fix for customer specific ASIC 138 SYStem.Option TIDEMUXFIX Bug fix for customer specific ASIC 138 SYStem.Option TraceStrobe Deprecated command 139 SYStem.Option TRST Allow debugger to drive TRST 139 SYStem.Option TURBO Speed up memory access 139 ©1989-2017 Lauterbach GmbH ARM Debugger 4 SYStem.Option WaitReset Wait with JTAG activities after deasserting reset 140 SYStem.Option ZoneSPACES Enable symbol management