DOCSLIB.ORG

MSP430 Based Wireless Sensor Network Master Thesis (30 ECTS)

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
MSP430 Based Wireless Sensor Network Master Thesis (30 ECTS) TALLINN UNIVERSITY OF TECHNOLOGY Faculty of Information Technology Thomas Johann Seebeck Department of Electronics Electronics and Bionics Sven Kautlenbach MSP430 Based Wireless Sensor Network Master Thesis (30 ECTS) Supervisor: Olev Märtens Tallinn 2014 Abstract Structural health monitoring has been the extensive research topic for years. Solutions are mostly applied to the civil engineering constructions, where the monitoring could avoid accidents, caused by the malfunction and cracking of the structures. With the rapidly developing semiconductor technologies the researches have started to design and evaluate wireless monitoring nodes. The advantages of wireless sensing nodes over wired ones are disparate. Using wireless data communication enables more mobility, less dependability on environment, faster installation times, less costs, more expandability and in general more dynamic system. The small size associated with the wireless nodes mean that they could also be integrated into the materials. The problems with the energy consumption, wireless link data throughput and latency are the main issues halting the widespread adaptation of these systems. Alleviating the cons of wireless systems are in focus of the research topics. Therefore testing new semiconductor devices and designs is needed. This work gives condensed overview of different wireless sensor designs covering different approaches to the problems. The state of the art of transceiver devices of different manufacturers and their portfolio is given. Finally the Texas Instruments MSP430 platform is taken into the focus of this work. The CC430 family of transceiver microcontrollers is evaluated. The Texas Instruments SimpliciTI wireless network library, which is part of Chronos development kit, is modified and adapted for the requirements set in the work. The work grades the performance of the system, measures the basic properties and proposes solutions to overcome the shortcomings and the problems of the system. The work was conducted as a part of the Archimedes project AR 12139 “Smart Composites – Design and Manufacturing”. 2 3 Table of contents Abstract .................................................................................................................................. 2 Table of contents................................................................................................................. 4 Table of figures .................................................................................................................... 7 List of tables .......................................................................................................................... 8 Abbreviations ....................................................................................................................... 9 1 Introduction .............................................................................................................. 12 1.1 Motivation ......................................................................................................................12 1.2 Objectives .......................................................................................................................13 1.3 Outline .............................................................................................................................14 2 Overview of the technology ................................................................................. 15 2.1 Prototype SHM systems.............................................................................................15 2.1.1 RQEM ........................................................................................................................................ 15 2.1.2 WiMMS ..................................................................................................................................... 17 2.1.3 RIMS .......................................................................................................................................... 20 2.1.4 Reconfigurable 6LoWPAN based sensor network ................................................. 21 2.1.5 Mobile agent SHM network ............................................................................................. 23 2.1.6 Summary and comparisons............................................................................................. 23 2.2 Low power transceiver devices ..............................................................................27 2.2.1 Microchip ................................................................................................................................ 28 2.2.2 Nordic Semiconductor....................................................................................................... 29 2.2.3 STMicroelectronics ............................................................................................................. 29 2.2.4 NXP Semiconductors .......................................................................................................... 30 2.2.5 Freescale ................................................................................................................................. 30 2.2.6 Silicon Labs ............................................................................................................................ 31 2.2.7 Atmel ........................................................................................................................................ 32 2.2.8 Texas Instruments .............................................................................................................. 32 4 2.2.9 Table of summary................................................................................................................ 34 3 Sensor network development on MSP430 ..................................................... 37 3.1 Development .................................................................................................................37 3.1.1 Development environments ........................................................................................... 37 3.1.2 Wireless development kits .............................................................................................. 42 3.1.3 Texas Instruments Chronos software ......................................................................... 45 3.1.4 CC1101 Chipcon radio transceiver .............................................................................. 48 3.1.5 SimpliciTI library ................................................................................................................. 50 3.1.6 Tools ......................................................................................................................................... 52 3.1.7 Software improvements ................................................................................................... 54 3.1.8 Radio network ...................................................................................................................... 59 3.2 Evaluation of wireless nodes ..................................................................................63 3.2.1 Data rate tests ....................................................................................................................... 63 3.2.2 Line of sight tests ................................................................................................................. 65 3.2.3 Energy consumption tests ............................................................................................... 65 3.2.4 Demo application ................................................................................................................ 67 3.2.5 Results ...................................................................................................................................... 68 4 Summary and future work ................................................................................... 70 5 Acknowledgments .................................................................................................. 71 6 References ................................................................................................................. 72 7 MSP430 platformil baseeruv sensorvõrk....................................................... 77 8 Appendices ................................................................................................................ 78 Appendix A Radio link data rate test bed .....................................................................78 Appendix B SmartRF Packet Sniffer records of the SimpliciTI traffic ................79 Appendix C SmartRF Packet Sniffer „.psd“ file parser logic ..................................80 Appendix D Snapshot of the SmartRF Studio tool ......................................................82 Appendix E Hyperlink to all the contents of the work ............................................83 5 Appendix F Git snapshots of the access point and the end device software development history ................................................................................................................83 Appendix G Access point command line tool’s packet parsing logic ..................84 6 Table of figures Figure 1: RQEM prototype along with the test circuitry on a common PCB .......... 17 Figure 2: First WiMMS prototype functional schematic ................................................ 18 Figure 3: Second WiMMS prototype functional schematic ..........................................
Load more

Recommended publications
  • Fill Your Boots: Enhanced Embedded Bootloader Exploits Via Fault Injection and Binary Analysis
    IACR Transactions on Cryptographic Hardware and Embedded Systems ISSN 2569-2925, Vol. 2021, No. 1, pp. 56–81. DOI:10.46586/tches.v2021.i1.56-81 Fill your Boots: Enhanced Embedded Bootloader Exploits via Fault Injection and Binary Analysis Jan Van den Herrewegen1, David Oswald1, Flavio D. Garcia1 and Qais Temeiza2 1 School of Computer Science, University of Birmingham, UK, {jxv572,d.f.oswald,f.garcia}@cs.bham.ac.uk 2 Independent Researcher, [email protected] Abstract. The bootloader of an embedded microcontroller is responsible for guarding the device’s internal (flash) memory, enforcing read/write protection mechanisms. Fault injection techniques such as voltage or clock glitching have been proven successful in bypassing such protection for specific microcontrollers, but this often requires expensive equipment and/or exhaustive search of the fault parameters. When multiple glitches are required (e.g., when countermeasures are in place) this search becomes of exponential complexity and thus infeasible. Another challenge which makes embedded bootloaders notoriously hard to analyse is their lack of debugging capabilities. This paper proposes a grey-box approach that leverages binary analysis and advanced software exploitation techniques combined with voltage glitching to develop a powerful attack methodology against embedded bootloaders. We showcase our techniques with three real-world microcontrollers as case studies: 1) we combine static and on-chip dynamic analysis to enable a Return-Oriented Programming exploit on the bootloader of the NXP LPC microcontrollers; 2) we leverage on-chip dynamic analysis on the bootloader of the popular STM8 microcontrollers to constrain the glitch parameter search, achieving the first fully-documented multi-glitch attack on a real-world target; 3) we apply symbolic execution to precisely aim voltage glitches at target instructions based on the execution path in the bootloader of the Renesas 78K0 automotive microcontroller.
    [Show full text]
  • MSP430FR2433 Mixed-Signal Microcontroller
    Product Order Technical Tools & Support & Folder Now Documents Software Community MSP430FR2433 SLASE59C –OCTOBER 2015–REVISED AUGUST 2018 MSP430FR2433 Mixed-Signal Microcontroller 1 Device Overview 1.1 Features 1 • Embedded Microcontroller Storage – 16-Bit RISC Architecture – 1015 Write Cycle Endurance – Clock Supports Frequencies up to 16 MHz – Radiation Resistant and Nonmagnetic – Wide Supply Voltage Range From 3.6 V Down – High FRAM-to-SRAM Ratio, up to 4:1 to 1.8 V (Minimum Supply Voltage is Restricted • Clock System (CS) by SVS Levels, See the SVS Specifications) – On-Chip 32-kHz RC Oscillator (REFO) • Optimized Ultra-Low-Power Modes – On-Chip 16-MHz Digitally Controlled Oscillator – Active Mode: 126 µA/MHz (Typical) (DCO) With Frequency-Locked Loop (FLL) – Standby: <1 µA With VLO – ±1% Accuracy With On-Chip Reference at – LPM3.5 Real-Time Clock (RTC) Counter With Room Temperature 32768-Hz Crystal: 730 nA (Typical) – On-Chip Very Low-Frequency 10-kHz Oscillator – Shutdown (LPM4.5): 16 nA (Typical) (VLO) • High-Performance Analog – On-Chip High-Frequency Modulation Oscillator – 8-Channel 10-Bit Analog-to-Digital Converter (MODOSC) (ADC) – External 32-kHz Crystal Oscillator (LFXT) – Internal 1.5-V Reference – Programmable MCLK Prescalar of 1 to 128 – Sample-and-Hold 200 ksps – SMCLK Derived from MCLK With • Enhanced Serial Communications Programmable Prescalar of 1, 2, 4, or 8 – Two Enhanced Universal Serial Communication • General Input/Output and Pin Functionality Interfaces (eUSCI_A) Support UART, IrDA, and – Total of 19 I/Os on
    [Show full text]
  • Using Energia (Arduino)
    Using Energia (Arduino) Introduction This chapter of the MSP430 workshop explores Energia, the Arduino port for the Texas Instruments Launchpad kits. After a quick definition and history of Arduino and Energia, we provide a quick introduction to Wiring – the language/library used by Arduino & Energia. Most of the learning comes from using the Launchpad board along with the Energia IDE to light LED’s, read switches and communicate with your PC via the serial connection. Learning Objectives, Requirements, Prereq’s Prerequisites & Objectives Prerequisites Basic knowledge of C language Basic understanding of using a C library and header files This chapter doesn’t explain clock, interrupt, and GPIO features in detail, this is left to the other chapters in the MSP430 workshop Requirements - Tools and Software Hardware Windows (XP, 7, 8) PC with available USB port MSP430F5529 Launchpad Software Already installed, if you Energia Download have installed CCSv5.x Launchpad drivers (Optional) MSP430ware / Driverlib Objectives Define ‘Arduino’ and describe what is was created for Define ‘Energia’ and explain what it is ‘forked’ from Install Energia, open and run included example sketches Use serial communication between the board & PC Add an external interrupt to an Energia sketch Modify CPU registers from an Energia sketch MSP430 Workshop - Using Energia (Arduino) 8 - 1 What is Arduino Chapter Topics Using Energia (Arduino) ............................................................................................................
    [Show full text]
  • Design Considerations When Using the MSP430 Graphics Library, and Provides an Example of Implementation and Optimization
    www.ti.com 1 Trademarks MSP430, MSP430Ware are trademarks of Texas Instruments. Stellaris is a registered trademark of Texas Instruments. All other trademarks are the property of their respective owners. SLAA548–October 2012 1 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Application Report SLAA548–October 2012 Design Considerations When Using MSP430 Graphics Library Michael Stein ABSTRACT LCDs are a growing commodity in today’s market with products as diverse as children’s toys to medical devices. Modern LCDs, along with the graphics displayed on them, are growing in complexity. A graphics library can simplify and accelerate development while creating the desired user experience. TI provides the MSP430 Graphics Library for use in developing products with the MSP430™ MCU. This application report describes design considerations when using the MSP430 Graphics Library, and provides an example of implementation and optimization. Project collateral discussed in this application report can be downloaded from the following URL: www.ti.com/lit/zip/SLAA548. Contents 2 Introduction to the MSP430 Graphics Library............................................................................ 2 3 System Overview ............................................................................................................ 3 4 Hardware Implementation - LCD Bus Type .............................................................................. 4 5 Software Implementation- LCD Display Driver Layer ..................................................................
    [Show full text]
  • Differences Between the TI MSP430 and MC9S08QE128 And
    Freescale Semiconductor Document Number: AN3502 Application Note Rev. 0, 09/2007 Differences between the TI MSP430 and MC9S08QE128 and MCF51QE128 Flexis Microcontrollers by: Inga Harris 8-bit Microcontoller Applications Engineer East Kilbride, Scotland 1 Introduction Contents 1 Introduction . 1 From the RS08 to our highest-performance ColdFire® 2 Top Level Specification Comparison . 2 3 Module Comparisons. 3 V4 devices, the Controller Continuum provides 3.1 12-bit Analog to Digital Convertor (ADC). 3 compatibility for an easy migration path up or down the 3.2 Analog Comparators . 4 performance spectrum. The connection point on the 3.3 Real Time Counter / Clock (RTC) . 5 3.4 I/O and Keyboard Interrupts . 6 Controller Continuum is where complimentary families 3.5 Hardware Multiplier . 7 of the S08 and ColdFire V1 (CFV1) microcontrollers 3.6 Low Voltage Detect (LVD). 7 3.7 Timer . 8 share a common set of peripherals and development tools 3.8 Interrupt Request (IRQ). 9 to deliver the ultimate in migration flexibility. 3.9 Watchdog . 9 Pin-for-pin compatibility between many devices allows 3.10 Flash Comparison . 9 3.11 Communications Peripherals. 11 controller exchanges without redesigning the board. The 3.12 Debugger. 13 MC9S08QE128 and the MCF51QE128 are the first 4 Clock Generator Module . 14 4.1 Functional Differences. 17 products in this series known as Flexis. 4.2 Clock Modes . 18 4.3 Clock Gating . 18 The term Flexis means a single development tool to ease 5 CPU Cores . 19 migration between 8-bit (S08) and 32-bit (CFV1), a 5.1 CPU Performance . 19 common peripheral set to preserve software investment 5.2 CPU Modes .
    [Show full text]
  • Ti Msp430 Microcontrollers
    TI MSP430 MICROCONTROLLERS BY ADITYA PATHAK THE MSP FAMILY • Ultra-low power; mixed signal processors • Widely used in battery operated applications • Uses Von Neumann architecture to connect CPU, peripherals and buses • AVR is commonly used debugger The MSP family (cont.) • 1 to 60 kB flash • 256B to 2kB RAM • With or without Hardware multipliers, UART and ADC • SMD package with 20 to 100 pins • MSP 430 family has 4 kB flash, 256B RAM, 2 timers and S0-20 package Memory Organization Architecture: Basic Elements • 16 bit RISC processor • Programmable 10/12 bit ADC • 12 bit Dual DAC for accurate analog voltage representation • Supply voltage supervisor for detection of Gray level • Programmable timers, Main and Auxiliary crystal circuits CPU features • Reduced Instruction Set Computer Architecture • 27 instructions wide instruction set • 7 orthogonal addressing modes • Memory to Memory data transfer • Separate 16 bit Address and Data buses • 2 constant number generators to optimize code Instruction Set • 27 “CORE” instruction and 24 “EMULATED” instructions • No code or performance penalties for Emulated instructions • Instructions can be for word or byte operands (.W / .B) • Classified into 3 groups Single Operand Instructions: RR, RRC, PUSH, CALL Dual Operand Instructions: MOV, ADD, SUB Jumps: JEQ, JZ, JMP Clock sub-system Basic Clock module includes: • LFXT1 – LF/HF crystal circuit, that uses either 32,768 Hz crystal (LF); or standard resonators in 450K-8MHz range • XT2 – optional HF oscillator that can be used with standard crystals
    [Show full text]
  • MSP430 Family Architecture
    MSP430 Family Architecture CPE621 Advanced Microcomputer Techniques Dr. Emil Jovanov CPE 621 MSP430 Architecture 1 Technology • Ultra low power – The MSP430 platform of ultra-low-power 16-bit RISC mixed-signal processors • 0.1 µA RAM retention • 0.8 µA real-time clock mode • 250 µA/MIPS active – MSP430x5xx – new Flash-based family featuring the lowest power consumption • up to 25 MIPS with 1.8 to 3.6V operation starting at 12 MIPS • New features include an innovative Power Management Module for optimizing power consumption, an internally controlled voltage regulator, and 2x more memory than previous devices. • Low power & high performance – TMS320C550x DSPs Industry’s lowest power fixed-point DSP • Large on-chip memory • optimized FFT co-processor for faster, cost- and energy-efficient performance – One-half the power consumption of existing TMS320C55x™ DSPs • 6.8 µW* in deep sleep mode (all peripheral clocks off) • 18/46 mW at 60/100 MHz • Applications: medical monitoring, noise cancellation headphones and portable audio/music recording CPE 621 MSP430 Architecture 2 1 MSP430 Family • MSP430x1xx – 1.8V to 3.6V operation –up to 60kB – 8MIPs with Basic Clock – from a simple low power controller with a comparator, to complete systems on a chip including high- performance data converters, interfaces and multiplier. • MSP430F2xx – up to 16 MHz – an integrated ±1% on-chip very lowpower oscillator, – software-selectable, internal pullup/pull-down resistors – increased number of analog inputs – the in-system programmable Flash has also been improved with smaller 64-byte segments and a lower 2.2-V programming voltage – Available in low-pin count options.
    [Show full text]
  • Msp430fg461x, Msp430cg461x Mixed-Signal Microcontrollers
    Product Order Technical Tools & Support & Reference Folder Now Documents Software Community Design MSP430FG4619, MSP430FG4618, MSP430FG4617, MSP430FG4616 MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616 SLAS508K –APRIL 2006–REVISED MAY 2020 MSP430FG461x, MSP430CG461x Mixed-Signal Microcontrollers 1 Device Overview 1.1 Features 1 • Low supply-voltage range: 1.8 V to 3.6 V • Universal serial communication interface • Ultra-low power consumption – Enhanced UART supports automatic baud-rate – Active mode: 400 µA at 1 MHz, 2.2 V detection – Standby mode: 1.3 µA – IrDA encoder and decoder – Off mode (RAM retention): 0.22 µA – Synchronous SPI • Five power-saving modes – I2C • Wakeup from standby mode in less than 6 µs • Serial onboard programming, programmable code • 16-bit RISC architecture, extended memory, protection by security fuse 125‑ns instruction cycle time • Brownout detector • Three-channel internal DMA • Basic timer with real-time clock (RTC) feature • 12-bit analog-to-digital converter (ADC) with • Integrated LCD driver up to 160 segments with internal reference, sample-and-hold and autoscan regulated charge pump feature • Device Comparison summarizes the available • Three configurable operational amplifiers family members • Dual 12-bit digital-to-analog converters (DACs) – MSP430FG4616, MSP430FG4616, with synchronization 92KB+256B of flash or ROM, • 16-bit Timer_A with three capture/compare 4KB of RAM registers – MSP430FG4617, MSP430CG4617, • 16-bit Timer_B with seven capture/compare-with- 92KB+256B of flash or ROM, shadow
    [Show full text]
  • MSP430 Ultra-Low-Power Microcontroller Family Product
    ™ R EAL W ORLD S IGNAL P ROCESSING MSP430 Ultra-Low-Power MCUs 2004 Modular Architecture Key Features • Ultra-low-power architecture extends battery life: ACLK - 0.1 µA RAM retention Clock Flash RAM Port - 0.8 µA real-time clock mode System - 250 µA/MIPS active SMCLK • High-performance analog ideal MCLK for precise measurement MAB • Modern 16-bit RISC CPU enables new applications at RISC CPU 16-Bit a fraction of the code size MDB • In-system programmable Flash JTAG/Debug permits flexible code changes, field upgrades and data logging ACLK • Complete integrated develop- Analog Digital Watchdog ment environment starting Peripheral Peripheral at $49 SMCLK • Device pricing as low as $0.49 MSP430 von-Neumann architecture — all program, data memory and peripherals share a Key Applications common bus structure. Consistent CPU instructions and addressing modes are used. • Utility metering • Portable instrumentation Modern 16-Bit RISC CPU MSP430 Modern Orthogonal 16-Bit • Intelligent sensoring • Large register file eliminates RISC CPU accumulator bottleneck MDB MAB MSP430 Architecture • Optimized for C and 15 0 A 16-bit RISC CPU, peripherals and assembler programming R0/PC Program Counter flexible clock system are combined by • Compact core design reduces R1/SP Stack Pointer using a von-Neumann common power and cost R2/SR Status memory address bus (MAB) and • Up to 8 MIPS of performance R3/CG Constant Generator memory data bus (MDB). Partnering available R4 General Purpose a modern CPU with modular memory- R5 General Purpose mapped analog and digital peripherals, The MSP430’s orthogonal archi- General Purpose the MSP430 offers solutions for tecture provides the flexibility of R6 today’s and tomorrow’s mixed-signal 16 fully addressable, single-cycle R7 General Purpose applications.
    [Show full text]
  • Embedded Systems: Principles and Practice
    Embedded Systems: Concepts and Practices Part 2 Christopher Alix Prairie City Computing, Inc. ECE 420 University of Illinois November 27, 2017 Outline (Part 2) • Software challenges in Embedded Systems • Key decisions in ES software development • ARM and DSP Architectures • Low-cost ES Prototyping Platforms • Trends and opportunities in the ES industry Embedded System Definition • A dedicated computer performing a specific function as a part of a larger system • High-reliability systems operating in a resource-constrained environment (typically cost, space & power) • Essential Goal: Turn hardware problems into software problems. Software Challenges "Black Box" Problem Limited input/output and user interface presents challenges, especially during debugging. Much embedded software is cross developed— written and debugged in the comfort of a desktop PC, and then downloaded into the system under development for final testing and deployment. Software Challenges "Black Box" Problem Embedded processors typically include a hardware interface (usually JTAG) for loading software and for doing remote debugging from a host computer. A development version of the hardware is often built first with extra interfaces for testability, which are then stripped out of the final design. Systems often include a connector for a "debug board" or "breakout board" which includes extra connections for debugging. Software Architecture Realtime Requirements Many ES have tasks that must be performed reliably at a specific rate. (e.g., capture a new audio sample every
    [Show full text]
  • A Self-Optimizing Embedded Microprocessor Using a Loop Table
    A Self-Optimizing Embedded Microprocessor using a Loop Table for Low Power Frank Vahid* and Ann Gordon-Ross Department of Computer Science and Engineering University of California, Riverside http://www.cs.ucr.edu/~vahid {vahid/ann}@cs.ucr.edu *Also with the Center for Embedded Computer Systems at UC Irvine. ABSTRACT additional transistor capacity is to reduce power in a mass- We describe an approach for a microprocessor to tune itself to its produced embedded microprocessor by, adding tunable fixed application to reduce power in an embedded system. We components to the architecture, and extra circuitry that tunes those define a basic architecture and methodology supporting a components to the particular fixed application. Essentially, the microprocessor self-optimizing mode. We also introduce a loop microprocessor is self-optimizing. A designer using such a part table as a tunable component, although self-optimization can be gets reduced power through some customization while still getting done for other tunable components too. We highlight the benefits of a mass-produced IC. experimental results illustrating good power reductions with no In this paper, we describe a basic architecture and methodology performance penalty. for a self-optimizing microprocessor that tunes itself to an application to reduce power. Such a microprocessor represents an Keywords instance of post-fabrication tuning [16], namely tuning done after System-on-a-chip, self-optimizing architecture, embedded an IC has been fabricated. We introduce self-profiling circuitry systems, parameterized architectures, cores, low-power, tuning, and a designer-controlled self-optimization mode, in which platforms. configurable architectural components would be tuned based on an application’s profile.
    [Show full text]
  • The ZEN of BDM
    The ZEN of BDM Craig A. Haller Macraigor Systems Inc. This document may be freely disseminated, electronically or in print, provided its total content is maintained, including the original copyright notice. Introduction You may wonder, why The ZEN of BDM? Easy, BDM (Background Debug Mode) is different from other types of debugging in both implementation and in approach. Once you have a full understanding of how this type of debugging works, the spirit behind it if you will, you can make the most of it. Before we go any further, a note on terminology. “BDM” is Motorola’s term for a method of debugging. It also refers to a hardware port on their microcontroller chips, the “BDM port”. Other chips and other manufacturers use a JTAG port (IBM), a OnCE port (Motorola), an MPSD port (Texas Instruments), etc. (more on these later). The type of debugging we will be discussing is sometimes known as “BDM debugging” even though it may use a JTAG port! For clarity, I will refer to it as “on-chip debugging” or OCD. This will include all the various methods of using resources on the chip that are put there to enable complete software debug and aid in hardware debug. This includes processors from IBM, TI, Analog Devices, Motorola, and others. This paper is an overview of OCD debugging, what it is, and how to use it most effectively. A certain familiarity with debugging is assumed, but novice through expert in microprocessor/microcontroller design and debug will gain much from its reading. Throughout this paper I will try to be as specific as possible when it relates to how different chips implement this type of debugging.
    [Show full text]