System in a Package (SiP) Technical Solution Sheet
SiP and Module Definitions SiP is an assembly of 2 or more semiconductor devices (IC and or Discrete chips or packaged devices) with passive components or integrated passive devices (IPD) into a standard package format to complete a sub-system printed circuit board assemblies in an LGA, BGA or leadless chip carrier (QFN) format. The SiP technology has ability to bring together multi chips and package assembly and test techniques to create highly integrated products with optimized cost, size and performance. Note: UTAC offers SiP standard packages (leadframe, laminate based) that characterized by combination of one or multiple chips of different functionality either side by side or stacked , which may include passive components and/ or integrated passive devices (IPD) using wire bonding or flip chip technology interconnect. UTAC offers in SiP design, assembly and Test with integration and size reduction by using different package forms, factors and assembly capabilities and technology. Power amplifier (PA/RF) module, USB drives and Power management are examples of Multiple & Stacked Die Bonding standard SiP UTAC assembles and tests. UTAC SiP / Module Solutions Advantages • Laminate based LGA or BGA or FCBGA System miniaturization through package sub-system • • Leadless leadframe TLA, QFN or GQFN or MIS (array option) integration form factor benefits. • Multi Chip package (MCP) for PA/RF Power Amplifier module Electrical performance optimization through short • • Power management solutions interconnects and well characterized component • Memory, Multimedia cards and USB drives integration that facilitate system design. • 3D Embedded Chip solution EMI/RFI shielding is an option for SiP or • • High Density Passives & Pre-packaged IC integration solution modules which can include isolation between RF and digital sections of a SiP or module. UTAC Capabilities Summary • Thermal performance optimization through integration of • SiP is a strategic segment for UTAC with multi-chip and SMT established package design, assembly and materials capabilities in multiple factories technologies that can provide 2 sided chip cooling and • Stacked Die, Embedded Die, Flip Chip engineered management of die hot spots. • Wirebond (Au, PdCu, AuPdCu) • Mechanical performance optimization leveraging • EMI/RFI shielding established package thermal cycle and shock data, • Extremely thin configurations and mold caps material properties and finite element modeling simulation • Thick mold caps for large components (inductors) capabilities. • Film assist molding for exposed die (thermal management or • System design optimization and time to market benefits sensor solutions) through well characterized SiP or module performance • Wide range of passives integrated, planar 2D and 3D pkg data that enable plug/play and bill of material reduction/ architectures i.e. Passive components minimum of 01005, management. crystal, large inductors, PiP (Pre-packaged QFN, LGA, WLCSP) and Connector integration • High Density passive components integration • Package co-design and simulation technology • Full turnkey assembly and test servies Edition: Q1 2019, rev B w ww.utacgroup.com
System in a Package (SiP) 2 Technical Solution Sheet
SiP Package Selection Considerations
LGA-SiP / BGA-SiP Substrate Based 3D w/ Embedded (Multi Layers Specific Specific Capability) QFN/LGA Performance Electrical & Functionality
Routable QFN-SiP Power LGA SiP
QFN-SiP Thick Mold Cap. : 3.4 ~7.2mm Reliability Thermal & Leadframe Based (1 Layer Capability) Low Pin Count High Pin Count I/O Count & Design Complexity
SiP Module Design Flow
C6
C10 R8 C13 C67
C69
C3
R7
C9 C5
C11 U3
C7 C37 C12 C15 C36
L1 R6
U2 C8 C35 C4
C14 C34
C2 U5 C26
R4
R3
C18 C33
C32
R13
R5 C68 C25 C17
C42 C19 C62 C24
C1 R1 R2
C61 C66
C57 C65
C64
C63
C60 C43
C41 C20
C44
C38
L2 L3 C21 C54
C50 C49
C45
C39 C22 C53
C74
C40
C58 C23 C52 C59
C51
C16 C46 R10
C48 C47
C56 C55
C71
C70
U1 R9 U4
R12 R11
C72
C73
C31
C29
C28
C30
C27
FB3 FB2 FB1 Package Design Feasibility Design Input Package Design, Package Package Studies & Documents, Feasibility Design Review & Layout & Simulation Manufacturing Schematic & BOM Packaging Approval (order) Functional Robustness Risk Assessment Optimization Solution Verification Review
UTAC SiP Package Types
QFN Routable QFN /GQFN BGA / LGA Package size Package size 2.8x1.6mm – 15x15mm Package size 3x3mm – 21x21mm Mold thickness 4x2mm – 18x23mm Mold thickness 0.5mm – 3.8mm Mold thickness 0.5mm – 2.0mm Leadframe Surface Finishes/Thickness 0.5mm – 7.2mm Substrate Matte Sn, PPF / 8 mils Leadframe Finish and Thickness 2L – 6L Features Single layer Cu, PPF / 5 and 8 mils Features 0402, PiP (QFN), Solder die attach, Features 01005, PiP (QFN/ BGA/ WLCSP), Large Inductor 0201, PiP (QFN), Solder die attach, Solder die attach Application Large 3D Inductor Application Power, Data servers, DC/DC & Buck Application RF, PA/FEM, Power, Servers, Converters Power, Data servers, Converters Infotainment
FET FET QFN Die
4L UDP 110L LGA 256L BGA 4L 2.8x1.6mm 64L 15x15mm 24L 17x19mm 42L 18x23mm 11.1x16.0mm 10x14mm 21x21mm
Note: UTAC SiP and Module solutions are constructed with standard or customer specified materials. www.utacgroup.com Edition: Q1 2019, rev B SiP Design to Qualification Flow 3
Design from customer netlist and eBOM 1. Package Package stackup Design Design Tool (UPD, APD, CAM 350, AutoCAD…etc) Customer requirements to design rule check
2.Design DFS report + Risk assessment Feasibility Study Package Simulations (DFS) & Thermal/Electrical/M Simulation echanical) DFMEA
Process flow characterization 3.Process Parameter Characterization Characterization DOE optimization Failure Analysis
Process and parameter ready Confirmation Run 4. Validation Pre-Qual lot Reliability Study Failure Analysis
Assembly Report Reliability 5. Qualification Report MSL test, Stress test Temperature HAST Autoclave Cycling Chambers Chambers Chambers
Note: UTAC SiP and Module solutions are constructed with standard or customer specified materials. www.utacgroup.com Edition: Q1 2019, rev B