Impedance Networks Matching Mechanism and Design of Impedance Networks Converters

DISSERTATION zur Erlangung des akademischen Grades DOKTOR-INGENIEUR

der FakultätfürMathematik und Informatik der FernUniversitätin Hagen

von Guidong Zhang Shantou/China

Hagen, 2015

Preface

Thanks to my Ph.D. supervisor, Prof. Bo Zhang, for his recommendation, I made a decision in June 2011 to pursue a second Ph.D. degree in Germany under the supervision of Prof. Halang and Prof. Li. Such a small decision would definitely greatly change my future life, just like the “butterfly effect” in a chaotic system, because the four years’ experience in Germany has deeply changed my thought and broadened my view of the world. As I just came to Hagen in October 2011, everything was novel to me: the mentality, culture, human behaviour, and many details in daily life. I tried my best to adapt to and integrate into the new life and learn how to rightly think and behave. I went to play soccer at the TSV Hagen 1860 e.V. on Wednesdays and Saturdays. What impressed me is that all teammates, aged from 20 to 77 years old, punctually start to play at 6pm and end at 7:30pm in any weather conditions. I was deeply touched by their passion for soccer and earnest attitude. Actually, German rigor is reflected in all aspects of life. Also in my research work, Prof. Halang and Prof. Li helped me revise my scientific articles word by word until they became perfect. The serious attitude to work and life will benefit me for life. Although Germans are rigorous, they are warm-hearted. Not only from my supervisors and colleagues but also from my landlord and other German friends I received much help in all aspects of my life and work, which greatly eased my life here. Here I had chances to get to know many famous scientists and students with various cultural backgrounds from all over the world, as well to attend international conferences, workshops, and summer schools. For instance, I attended the summer school of complex networks in Pescara, Italy in 2012, where I met many Ph.D. students from Italy, Russia, Romania, etc. and professors. We went together for a walk or to drink beer, and had much fun. We have become friends even after the summer school and the friendship lasts. With the help of my supervisors, I could gradually get into my research topics. Firstly I was engaged in the project “suppressing electromagnetic interference in electronic devices via chaos control”, then in the theme of exploring the emergent behaviour of complex power grids, and finally I extended my research to the topic of revealing the impedance networks matching mechanism and designing novel impedance source converters for renewable energy industrial applications. This topic is of both theoretic and practical significance in the sense that the impedance networks matching mechanism is for the first time revealed and it lays II the foundation for proposing a systematic design methodology of specified impedance source converters. This work lets me stand in the forefront of the discipline of power electronics. This thesis has agglomerated painstaking efforts of many persons. It could never be com- pleted without their help. Here, I would first express my deep gratitude to my supervisor in China, Prof. Bo Zhang, who encouraged and inspired me to engage in the investigation of impedance source converters. I am also very grateful to Prof. Halang and Prof. Li for their patient instructions, so that I could learn how to do research and finish my research work in Hagen. I owe special thanks to Prof. Li’s wife, Mrs. Mei, and their son, Yifan, for their meticulous care, which made me feel at home. Moreover, I would thank Liqiang Yang for helping me do part of the experiments, as well I thank Profs. Dongyuan Qiu, Guiping Du, Yanfeng Chen, Xuemei Wang, Wenxun Xiao and Dr. Fan Xie for the fruitful discussions. Thanks also go to my classmates at the South China University of Technology, Wei Hu, Xiangfeng Li, Lei Wang, Min Li, Junfeng Han, Hongfei Ma, Xi Chen, Dongdong Wang, and Jiali Zhou for giving me a lot of good advices on my thesis, and to my colleagues in Hagen, Mrs. Jutta During, Mrs. Junying Niu, Prof. Yuhong Song, and Mrs. Renate Zielinski for the kind help. Sincere thanks are owed to my friends in Hagen and Guangzhou for their help in my life, Kai Chen, Li Chen, Jianqiu Xu, Jiamin Lu, Lei Xu, Xuqin Liao, Jianhui Liu, and Wei Li. Furthermore, my greatest gratitude goes to my parents and grandparents for their forever love and spiritual support, and to my sister and brothers for their contributions to family, without which I could not focus on my study abroad. At last but not least, I would mention that this work was partly supported by German AiF, Alexander von Humboldt Foundation, and the Key Program of National Natural Science Foundation of China.

Guidong Zhang

September 2015 in Hagen III

Abstract (in German)

Zunächst wird in dieser Dissertation der Hintergrund der durchgeführtenUntersuchungen zusam- men mit einem kurzen historischen Uberblick¨ zur Entwicklung der Leistungselektronik und dem Stand der Technik von Impedanzquellenwandlern unter Auflistung typischer Beispiele dargestellt.

Daran schließt sich eine Untersuchung der Eigenschaften von Impedanznetzen und deren Auswirkungen auf den Aufbau hochwertiger Stromrichter an. Eine qualitative Analyse liefert die Gründe,warum konventionelle Spannungs- und Stromquellenwandler unter Problemen wie Uberlappungsspitzen,¨ Leerlauf, eingeschränkter Verstärkungvon Ausgangsstrom oder - spannung oder Nichtanwendbarkeit auf induktive und kapazitive Lasten leiden und warum Impedanzquellenwandler diese Probleme überwinden können.Die Analyse ermöglicht, den für nichtlineare geschaltete Stromrichter wesentlichen Impedanznetzanpassungsmechanismus, der sich von Impedanzanpassung in lineareren Schaltkreisen deutlich unterscheidet, eingehend zu verstehen. Der Mechanismus passt sowohl die Impedanzen der Ein- und Ausgängeals auch die Phasen der Lasten an.

In Bezug auf den Impedanznetzanpassungsmechanismus wird eine systematische Methodik zur Entwicklung neuer Impedanzquellenstromrichter dargestellt, die geeignet ist, die tradi- tionelle, manuell-m¨uhsameEntwurfsmethodik zu ersetzen.

Im Hinblick auf einige spezielle industrielle Anwendungen werden vier neue Impedanzquel- lenwandler als Beispiele fürden Einsatz der vorgeschlagenen Entwurfmethodik entworfen, und zwar zwei 3-Z-Netz-Gleichspannungsaufwärtswandler nach Spezifikationen der Photovoltaik, ein fürelektrochemische Netzteile geeigneter Z-Quellenhalbbrückenwandler und ein Z-Quellen- halbbrückenwandler mit dualem Ausgang fürElektrofahrzeuge. IV

Abstract

This thesis ﬁrstly introduces the background of this research with a brief history of the development of power electronics, and the state of the art of impedance source converters by listing typical examples.

Then, the properties of impedance networks and their effects for constructing high-quality power converters are investigated. A qualitative analysis reveals the reasons why traditional voltage- and current-source converters suffer from the shoot-through or the open-circuit problems, from limited output current or voltage gains, and from inapplicability to both inductive and capacitive loads, and why impedance source converters can overcome these problems. This analysis lays a foundation to understand well the intrinsic impedance network matching mechanism in non-linear switched power converters, which is different from impedance matching in linear circuits. The impedance network matching mechanism deals with input impedance matching, output impedance matching and load phase matching.

Further, in terms of the impedance network matching mechanism, a systematic methodology for the design of novel power converters to replace traditional tedious, manual designs is presented.

With regard to some special industrial applications, four novel impedance source converters are devised as examples to apply this design methodology, namely two 3-Z-network DC-DC boost converters speciﬁed for solar energy systems, a Z-source half-bridge converter for electrochemical power supplies, and a dual-output Z-source half-bridge converter for electric vehicle systems. CONTENTS V

Contents

Preface I

Abstrakt (In German) III

Abstract (In English) IV

1 Introduction 1 1.1 Power Electronics: A Brief History ...... 1 1.2 Contributions ...... 4 1.3 Outline ...... 5

2 Impedance Networks and Impedance Source Converters 7 2.1 Preliminaries ...... 7 2.1.1 Voltage Sources and Current Sources ...... 7 2.1.2 Impedance Network and Z-Source ...... 8 2.2 Voltage-Source- and Current-Source-Inverters ...... 11 2.2.1 Voltage Source Inverters ...... 13 2.2.2 Current Source Inverters ...... 14 2.3 Z-Source Inverters ...... 16 2.4 State-of-The-Art of Impedance Source Converters ...... 20 2.4.1 Quasi-Z-Source Converters ...... 20 2.4.2 Trans-Z-Source Converters ...... 24 2.4.3 Embedded-Z-Source Converters ...... 28 2.4.4 Other Impedance Source Converters ...... 28 2.5 Summary ...... 30

3 Impedance Networks Matching Mechanism 33 3.1 Impedance Matching ...... 33 3.2 Input Impedance Matching ...... 34 3.3 Output Impedance Matching ...... 36 3.4 Load Phase Matching ...... 40 VI CONTENTS

3.5 Matching Optimization ...... 42 3.6 Design Methodology of Power Converters ...... 44 3.6.1 Topology Design ...... 45 3.6.2 Selection of An Impedance Network ...... 46 3.6.3 Input Impedance ...... 50 3.6.4 Output Impedance ...... 51 3.6.5 Analysis of the Operational Status ...... 52 3.6.6 Parameters Design ...... 53 3.6.7 Simulations and Experiments ...... 53 3.7 Summary ...... 53

4 A 3-Z-Network Boost Converter 55 4.1 System Design ...... 56 4.1.1 Disadvantage of Traditional Boost Converters ...... 56 4.1.2 Selection of Impedance Networks ...... 57 4.1.3 Calculation of Input and Output Impedances ...... 58 4.2 Operational Modes Analysis ...... 60 4.3 CCM ...... 62 4.3.1 Case 1 ...... 62 4.3.2 Case 2 ...... 65 4.4 DCM ...... 65 4.4.1 Case 3 ...... 66 4.4.2 Case 4 ...... 68 4.4.3 Case 5 ...... 68 4.4.4 Case 6 ...... 69 4.5 Parameters Design ...... 70 4.5.1 Output Voltage and Voltage Stress of Electrical Components ...... 71 4.5.2 Parameters of Inductors ...... 73 4.5.3 Parameters of Capacitors ...... 74 4.6 Simulations and Experiments ...... 75 4.7 Summary ...... 78

5 A Z-Source Half-Bridge Converter 83 5.1 System Design ...... 84 5.1.1 Disadvantages of A Traditional Half-Bridge Inverter ...... 84 5.1.2 Impedance Matching of Traditional Half-Bridge Inverters ...... 85 5.1.3 Calculation of Input and Output Impedances ...... 86 5.2 Operational Status Analysis ...... 86 CONTENTS VII

5.2.1 Case 1 ...... 86 5.2.2 Case 2 ...... 87 5.3 Midpoint Balance of Input Capacitors ...... 94 5.3.1 Midpoint Voltage in Conventional Half-Bridge Converters ...... 94 5.3.2 Midpoint Voltage in Z-Source Half-Bridge Converters ...... 95 5.4 Parameters Design ...... 97 5.4.1 Parameters of Capacitors ...... 97 5.4.2 Parameters of Inductors ...... 98 5.5 Simulations and Experiments ...... 99 5.6 Summary ...... 102

6 A Dual-Output Z-Source Half-Bridge Converter 105 6.1 System Design ...... 106 6.2 Control Strategy ...... 107 6.3 Operational Modes Analysis ...... 109 6.4 Deduction of Output Voltages ...... 113 6.5 Parameters Design ...... 115 6.5.1 Parameters of Capacitors ...... 115 6.5.2 Parameters of Inductors ...... 116 6.6 Simulations and Experiments ...... 117 6.7 Summary ...... 120

7 Conclusions 121

References 123

Appendix: Curriculum Vitae 137 VIII CONTENTS 1 Introduction 1

Chapter 1

Introduction

1.1 Power Electronics: A Brief History

Thunder, lightning and electric fish, which are related to electricity [1], were just natural phenomena in human history, and treated as myths but not energy in human life until the discovery of electrostatic phenomena by Thales of Miletus (640-540 BC) [2, 3]. Much later in 1752, B. Franklin discovered electricity [4] and in 1820 H.C. Orsted¨ revealed electromagnetism [5]. Since then, a series of great discoveries about the principles of electricity and magnetism have been done by Volta, Coulomb, Gauss, Henry, Faraday, and others, leading to many inventions such as the batteries (1800), generators (1831), electric motors (1831), telegraphes (1837), and tele- phones (1876), to list just a few. Until the early 19th century the electrical science has been established and in the late 19th century the greatest progress has been witnessed in electrical engineering [6]. In 1882, the first power grid, which was a direct-current (DC) distribution system and invented by T. Edison, was set up in New York, providing 110 V DC power to supply over 1,000 bulbs in a short distance. Then, the problem was how to transfer energy from power plants over a long distance to customers at a low loss through transmission lines [7]. It is now well known that electricity must be transmitted at high voltages and in the form of alternative- current (AC) because DC voltage cannot be increased or decreased by DC systems at that time [8]. In 1885, L. Gaulard and J.D. Gibbs developed a device, named a transformer, which can increase or decrease the electrical voltage of AC systems. Then, G. Westinghouse applied the transformer in AC distribution systems to make the electricity available to be transported over long distances efficiently, which promoted the development of electrical engineering [9]. Transformers played a vital rôlein electricity transmission, especially in the energy conversion between different voltages. However, transformers can only increase or decrease AC voltage (AC-AC) at the same frequency. Moreover, energy loss of transformers, magnetic ra- diations, huge volume, and high economic cost of copper became severe problems of applying 2 1 Introduction transformers [10]. In practical applications, electric energy was expected to convert from one form to another, for instance, between AC and DC, or just to different voltages or frequencies, or some combinations of those, which cannot be fully fulfilled by transformers. Hence, novel techniques were required to solve these problems. With the developments of semiconductor switches, power electronics appeared and has developed to be a discipline [11]. Power electronics refers to electric power, electronics and control systems. Electric power deals with the static and rotating power equipments for the generation, transmission and distribution of electric power; while electronics deals with the study of solid state semiconductor power devices and circuits together with specified control systems for power conversion to meet the desired control objectives [12]. Power electronics is one of the main technologies to realize energy conversion with high efficiency. It is known that about 70% electric energy should be converted first to the load with power electronics techniques. Nowadays, techniques of power electronics have become a fundamental and critical technology in the development of energy conservation, especially for renewable energy [13, 14, 15, 16]. The history of power electronics is linked up with the break-through and evolution of power semiconductor devices [17]. The first power electronics device developed was the mercury arc rectifier in 1900. Then, the other power devices like metal tank rectifier, grid controlled vac- uum tube rectifier, ignitron, phanotron, thyratron and magnetic amplifier, were developed and used gradually for power control applications until 1950. The second electronics revolution began in 1958 with the development of the commercial grade thyristor by the General Electric company (GE). Thus, the new era of power electronics began. Since 1975, more turn-off power semiconductor elements were developed and implemented during the next 20 years, which had vastly improved modern electronics. Included here are improved bipolar transistors (with fine structures, and also shorter switching times), metal-oxide-semiconductor field effects transistors (MOSFETs), gate turnoff thyristors (GTOs) and insulated gate bipolar transistors (IGBTs). Thereafter, many different types of power semiconductor devices and power conversion techniques have been introduced. The power electronics revolution has endowed us the ability to convert, shape and control power [18]. With the development of semiconductor devices, different kinds of control strategies are also correspondingly developed to realize specified purposes. For example, high-accuracy and high-frequency control methods based on chips like DSP, FPGA and CPLD were applied to meet the desired requirements and gain better control of the load; more accurate mathematical modeling methods of power converters offered better platforms to gain better output features, reduce the energy loss and increase the efficiency; and improved control algorithms were utilized to improve the efficiency and robustness, reduce the complexity, and gain better output features. Power electronics converters fall into four categories, i.e. AC-DC, AC-AC, DC-DC, and DC-AC converters, and they have been invented and found a wide spectrum of applications in, 1 Introduction 3 for instance, the transportation (electric/hybrid electric vehicles, electric locomotives, electric trucks), utilities (line transformers, generating systems, grid interface for alternative energy resources like solar, wind, and fuel cells, and energy storage), industrial/commercial (motor drive systems, electric machinery and tools, process control, and factory automation), consumer products (air conditioners/heat pumps, appliances, computers, lighting, telecommunications, un-interruptible power supplies, and battery chargers), and medical equipments. Moreover, with the advanced power electronics converters, high-voltage direct current (HVDC) systems are also available to replace AC transmission systems with unique features. Nowadays, power electronics has become a scientific discipline [19]. With rapid development of modern industry, more severe problems are faced by power electronics: how to meet the requirements of the load; how to improve the efficiency and reliability of power semiconductor devices; how to realize power conversion with smaller volume, less weight, and lower cost; how to reduce the number of power switches and thus the complexity and improve the robustness of the whole system; and how to minimize negative influence on other equipments in the electric power systems and on the electromagnetic environment [20]. In order to solve these problems, some advances were witnessed in the semiconductor switches in power converters, for example, integrated gate-commutated thyristors (IGCT) were invented to have lower conduction loss compared to the traditional high capacities switches. However, due to high switching losses, typical operating frequency is normally set up to 500 Hz. Accordingly, control strategies were also improved in algorithms with higher accuracy and speed [21]. To design a new power electronics converter, one can, on the one hand, develop a new control strategy. On the other hand, one can design a novel power converter topology, so as to obtain specific outputs, more simple control, higher efficiency, less complexity, lower weight, minimal cost, and better robustness. In fact, a control strategy is specified to a certain topology, and the topology determines the control system. Therefore, it is of great significance to coin new power converter topologies to fulfill various requirements in applications, which will thus be the main concern of the dissertation. Due to an input source of a converter being either a voltage source or a current source, various traditional converters can fall to two categories: voltage source and current source converters. It is, however, known that voltage source converters suffer from shoot-through problems, applicability only to capacitive loads, and limited output voltage gains; while current source converters have open-circuit problems, applicability only to inductive loads, and limited output current gains [22]. In order to solve these problems, Z-source converters were firstly proposed by Peng in 2002 [23], by coupling an LC impedance network (a two-port network with a combination of two basic linear energy storage elements, i.e. L and C) with the DC source to form a novel source, named Z-source, which is a kind of impedance source (an impedance is denoted by 4 1 Introduction

Z) [24, 25]. Impedance source can be regarded as a general source, including the current and the voltage sources as two extreme cases, i.e. impedance source can be regarded as the current source when the equivalent impedance is equal to infinity, while as the voltage source when the equivalent impedance is equal to zero. Therefore, the topology of impedance source converters has been widely studied and applied due to its unique features and its design method; for example, a Z-network is applied to couple with the traditional converters to improve their functions. Inspired from this design method, more impedance source converters, such as quasi-Z-source converters, trans-Z-source converters, embedded-Z-source converters, have been coined and widely applied in practice, e.g. wind energy systems [26, 27, 28], motor drives [29]-[32], vehicle systems [33]-[37], and solar energy systems [38]-[48]. In fact, the design methodology of Z-source and other extended impedance source converters is essentially is based on the impedance network matching mechanism, which instructs how an impedance network can be matched to the sources to fulfill certain requirements. However, the essential impedance matching mechanism has not yet been well understood and revealed, and the design of specific impedance source converters is still an art, lacking of a systematic design methodology. In this dissertation, a profound analysis of voltage and current sources converters is to be conducted in order to well understand why impedance source converters have the unique features over traditional converters. Furthermore, the impedance network matching mechanism is to be revealed, which leads to a systematic methodology of designing impedance source converters for various specific applications.

1.2 Contributions

The contributions of the thesis are listed as follows.

1. Qualitative analysis is for the ﬁrst time conducted to explain the reasons why traditional voltage and current sources converters have the problems, like the shoot-through or the open-circuit, limited output current or voltage gains, and applicability just to inductive or capacitive loads, and why impedance source converters can overcome these problems.

2. The impedance network matching mechanism, including input impedance matching, output impedance matching and load phase matching, has been revealed. It acts as a criterion to follow for designing an impedance source converter.

3. Based on the impedance network matching mechanism, a systematic methodology has been proposed for designing a novel impedance source converter. 1 Introduction 5

4. In terms of the proposed methodology, two novel 3-Z-network DC-DC boost converters have been coined by cascading three active impedance networks to realize high output voltage gains. These are speciﬁed to the applications in solar energy systems.

5. Similarly, a novel Z-source half-bridge converter has been designed by coupling a Z- network into a half-bridge converter for input impedance matching, which also balances the mid-voltage of input capacitors. It is especially applicable to electrochemistry power supplies.

6. A novel dual-output Z-source half-bridge converter has been devised by parallelizing two impedance networks for output impedance matching. Here, one forth of switches and capacitors are reduced, which also decreases the cost but increases the power density in electric vehicle systems.

1.3 Outline

The rest of the dissertation is constructed as follows. Chapter 2 introduces ﬁrst the fundamental concepts of voltage sources, current sources, Z-source and impedance networks. Then a qualitative analysis is conducted to explain why traditional voltage and current sources converters have the problems, like the shoot-through or the open-circuit, limited output current or voltage gains, and applicability just to inductive or capacitive loads, while impedance source converters can overcome these problems. Finally, the state-of-the-art of impedance source converters is presented with a detailed list of typical Z-source converters. Chapter 3 reveals the impedance network matching mechanism in power converters. Dif- ferent to impedance matching in linear circuits, the impedance networks matching mechanism contains input impedance matching, output impedance matching and load phase matching. It follows with a general and systematic design methodology for designing power converters to be proposed to replace the traditional tedious, manual design of Z-source converters. Chapter 4 follows the proposed methodology to design two 3-Z-network boost DC-DC converters. Therein, impedance networks are cascaded to realize output impedance matching, which greatly increases the output voltage gain (theoretically reaching 350) and solves the low output voltage problem in solar energy systems. The system analysis, parameters determination, simulations and experiments will be given. Chapter 5 proposes a novel Z-source half-bridge converter, where an impedance network is subtly embedded into the half-bridge converter to realize input impedance matching, which also balances the mid-voltage of its input capacitors, and fulﬁlls the rigorous requirements of electrochemical power supplies. Similarly, the system analysis, parameters determination, simulations and experiments will be presented. 6 1 Introduction

Chapter 6 devises a dual-output Z-source half-bridge converter with two impedance networks being parallelized to realize output impedance matching. Such a design reduces one forth of switching components and capacitors and fulﬁlls the requirements of dual-output, thus it not only minimizes the cost but also increases the watt density of electric vehicles. Furthermore, the system analysis, parameters determination, simulations and experiments are also given. Chapter 7 draws a conclusion of the whole thesis. 2 Impedance Networks and Impedance Source Converters 7

Chapter 2

Impedance Networks and Impedance Source Converters

Some preliminaries are ﬁrst introduced, such as voltage sources and current sources, and impedance network and Z-source, which are fundamental for further exploring the mechanism of impedance network matching and the methodology of design high-quality impedance source converters. A qualitative analysis is then conducted to understand the existing problems of the traditional voltage source and current source converters and the advantages of Z-source converters. Finally, the state-of-the-art of impedance source converters is presented.

2.1 Preliminaries

2.1.1 Voltage Sources and Current Sources

A power converter processes the flow of energy between two sources, generally between a generator and a load, as illustrated in Fig. 2.1. An ideal static converter is assumed to transmit electric energy between the two sources with 100% efficiency. The conversion efficiency is the main concern in designing a converter. Therefore, in practice, power converter design aims at improving the efficiency. There are two types of sources, namely voltage and current sources, any of which could be a generator or a load. A real voltage source can be represented as an ideal voltage source in series with a resistance

rVS, with the ideal voltage source having zero resistance, to ensure its output voltage to be constant. The voltage source is normally equivalent to a capacitor C with inﬁnite capacitance, 1 i.e. C = ∞, so that rC = ZC = −j ωC ≈ 0, where ZC denotes the resistance of the capacitor. Similarly, a real current source can be represented as an ideal current source in parallel

with a resistance rCS, with the ideal current source having inﬁnite resistance, so that its output current is constant, which is normally equivalent to an inductor with inﬁnite inductance, i.e. 8 2 Impedance Networks and Impedance Source Converters

Fig. 2.1: A power converter

L = ∞, which implies also rL = ZL = jωL ≈ ∞, where ZL represents the resistance of the inductor. Correspondingly, converters can be classiﬁed into voltage source converters and current source converters.

2.1.2 Impedance Network and Z-Source

Impedance

The term, resistance, is associated with DC circuits, which is extended to impedance when facing both DC and AC circuits. For DC circuits, resistance and impedance are equivalent. Unlike resistance, which has only magnitude and is represented as a positive real number (ohms (Ω)), impedance possesses both magnitude and phase and can be represented as a complex number with the imaginary part denoting the reactance and the real part representing the resistance. Impedance is used to measure the opposition that a circuit presents to a current when a voltage is applied [49], and is deﬁned as the frequency domain ration of the voltage to the current. For a sinusoidal current or voltage input, the polar form of the complex impedance relates the amplitude and phase of the voltage and current. In particular,

• the magnitude of the complex impedance is the ratio of the voltage amplitude to the current amplitude, and

• the phase of the complex impedance is the phase shift by which the current lags the voltage. 2 Impedance Networks and Impedance Source Converters 9

Impedance Network and Two-port Network

Like a resistor network, which is a collection of interconnected resistors in series or/and parallel, an impedance network in the context of power electronics, where exist nonlinear switches, is a network of impedance components like switches, sources, inductors, and capacitors, interconnected in series or/and parallel. An impedance network can be a passive one, if it is just composed of inductors and/or capacitors, or an active one, if it is constituted of switches and/or diodes, inductors and/or capacitors. It is diﬃcult, if not impossible, to analyze an impedance network using (linear) circuit theory due to the nonlinear switch components in the impedance network. A useful procedure is to simplify the analysis of the impedance network by reducing the number of components, which is then normally done by replacing the actual components with notional components of the same functions. Among some analysis methods, such as Nodal and Mesh analyses, a two-port network is well suited for analysis of the impedance network. A two-port network, as shown in Fig. 2.2, is an electrical network or a device with four terminals, which are arranged into pairs called ports, i.e. each pair of terminals is one port. As shown in Fig. 2.2, the left port is usually considered as the input port, while the right one is the output port. Therefore, a two-port network is represented by four external variables, i.e. voltage U1(s) and current I1(s) at the input port, and voltage U2(s) and current I2(s) at the output port, so that the two-port network can be treated as a black box modeled by the relationships between the four variables U1(s), I1(s), U2(s), and I2(s) [50]-[53].

Fig. 2.2: Two-port networks

The transmission equation of a two-port network is given by [54]-[57] " # " # U (s) U (s) 1 = A(s) · 2 , (2.1) I1(s) −I2(s) where A(s) is the transmission matrix and written as " # A (s) A (s) A(s) = 11 12 , (2.2) A21(s) A22(s) 10 2 Impedance Networks and Impedance Source Converters whose elements are deﬁned as  U (s)  1  A11(s) = ,  U2(s)  I (s)=0  2  U (s)  1  A12(s) = ,  −I2(s)  U (s)=0 2 (2.3) I (s)  1  A21(s) = ,  U2  I (s)=0  2  I (s)  1  A22(s) = .  −I2(s) U2(s)=0 Therefore, (2.1) can be rewritten as ( U (s) = A (s)U (s) + A (s)(−I (s)) , 1 11 2 12 2 (2.4) I1(s) = A21(s)U2(s) + A22(s)(−I2(s)) . The two-port network model is a mathematical circuit analysis technique to isolate portions of larger circuits. A two-port network is regarded as a “black box” with its properties speciﬁed by a matrix of numbers, which allows the response of the network to signals applied to the ports to be calculated easily, without solving all the internal voltages and currents in the network. Impedance networks can have multiple ports connecting external circuits, but generally have two ports, and can thus be equivalent to a two-port network. In terms of Thevenin’s equivalent impedance theorem, the input impedance of a two-port network is the equivalent impedance of the two-port network with an open input port and an output port connecting a load; while the output impedance (also named as source impedance or internal impedance) is the equivalent impedance of the two-port network with a short-circuited input port and an open output port. Further in terms of Ohm’s law, the input impedance of a two-port network

Zi(s) reads

U1(s) A11(s)ZL(s) + A12(s) Zi(s) = = , (2.5) I1(s) A21(s)ZL(s) + A22(s) where ZL(s) is the load impedance of the two-port network’s output port.

Similarly, the output impedance of two-port network Zo(s) writes

U2(s) A22(s)ZS(s) + A12(s) Zo(s) = = , (2.6) I2(s) A21(s)ZS(s) + A11(s) where ZS(s) is the source impedance of the two-port network’s input port.

Impedance Source Converters (Z-Source Converters)

An impedance network together with a source constitute an impedance source (also named a Z-source), with its equivalent impedance Z ∈ [0, +∞). The impedance source is a general 2 Impedance Networks and Impedance Source Converters 11

source, including voltage- and current sources as its extreme cases; that is, it becomes a voltage source for Z = 0; and a current source for Z → ∞. It exhibits rich properties for 0 < Z < ∞.

Correspondingly, a novel impedance source converter is thus coined, which possesses unique advantages over traditional voltage and current sources converters and can well meet more stringent requirements from today’s industry. It is known that voltage source converters suffer from shoot-through problems, the inapplicability to a capacitive load, and limited gains of output voltages; while current source converters have open-circuit problems, the inapplicability to an inductive load, and limited gains of output currents. A well-designed impedance source converter can be immune to those above-mentioned problems.

2.2 Voltage-Source- and Current-Source-Inverters

A converter is a general term for AC-DC rectifiers, DC-DC choppers, DC-AC inverters, and AC-AC converters. AC-DC rectifiers and AC-AC converters may have the shoot-through, open-circuit and limited output gains problems; while DC-DC choppers may suffer from the shoot-through and open-circuit problems and inapplicability to a capacitive or inductive load, and DC-AC inverters may have all of the problems. For simplicity, voltage-source- and current- source-inverters are taken as examples to be qualitatively analyzed from the perspective of impedance networks.

Voltage-source- and current-source-inverters are depicted in Fig. 2.3, where VVS(s) and

IVS(s) in Fig. 2.3(a) represent the voltage and current of the voltage source; while VCS(s)

and ICS(s) in Fig. 2.3(b) stand for the voltage and current of the current source, respectively.

Furthermore, their equivalent circuits are drawn in Fig. 2.4, where ZVS(s) and ZL(s) are the equivalent source impedance and equivalent load impedance of the voltage source inverter in Fig. 2.4(a), whose corresponding two-port network is indicated in the dashed box in Fig. 2.4(a),

where ZVS(s) is the unique component in the two-port network; while YCS(s) and YL(s) are the equivalent source admittance and load admittance of the current source inverter in Fig. 2.4(b),

whose corresponding two-port network is shown in the dashed box in Fig. 2.4(b), where YCS(s) is also the unique component in the two-port network. 12 2 Impedance Networks and Impedance Source Converters

(a) Voltage source inverters (b) Current source inverters

Fig. 2.3: Voltage source and current source inverters

(a) Voltage source inverters (b) Current source inverters

Fig. 2.4: Equivalent circuits of voltage-source- and current-source-inverters with two-port networks 2 Impedance Networks and Impedance Source Converters 13

2.2.1 Voltage Source Inverters

Shoot-Through

In terms of (2.3), the transmission matrix of the voltage source inverter in Fig. 2.4(a) reads  AV11(s) = 1 ,   A (s) = Z (s) , V12 VS (2.7) A (s) = 0 ,  V21  AV22(s) = 1 . Substituting (2.7) into (2.5) results in the input impedance of the voltage source inverter as AV11(s)ZL(s) + AV12(s) Zi(s) = = ZL(s) + ZVS(s) , (2.8) AV21(s)ZL(s) + AV22(s) while the input current of the voltage source is thus obtained as

VVS(s) VVS(s) IVS(s) = = . (2.9) Zi(s) ZL(s) + ZVS(s)

It is obvious that ZL(s) = 0 in case that the switches of the voltage source inverter on a bridge are turned on simultaneously. Moreover, the source impedance ZVS(s) is normally very

small, i.e. ZVS(s) ≈ 0. Therefore, Zi(s) = ZL(s) + ZVS(s) ≈ 0, which implies IVS(s) → ∞. Thus, the voltage source is shorted and a very large current will break down the switches. This is the so-called shoot-through problem. In order to prevent the occurrence of the shoot-through, the dead-time compensation technique is often used to prevent switches from turning on simultaneously [58].

Limited Output Voltage Gains

In terms of Fig. 2.4(a), substituting ZS(s) = 0 and (2.7) into (2.6) results in its output impedance as

AV22(s)ZS(s) + AV12(s) Zo(s) = = ZVS(s) . (2.10) AV21(s)ZS(s) + AV11(s) Obviously, the voltage of the load can be expressed as

VVL(s) = VVS(s) − IL(s)ZVS(s) . (2.11)

It is straightforward from (2.11) that ZVL(s) ≤ VVS(s)(ZVS(s),IL(s) ≥ 0); namely, the

load voltage VVL(s) is lower than or equal the source voltage VVS(s). In order to fulﬁll the high output voltage gain requirements in industrial applications like solar energy applications [59]-[62], DC-DC boost front stage converters can be cascaded to boost the output voltage, which actually changes its output impedance features to increase its output voltage gains. 14 2 Impedance Networks and Impedance Source Converters

Inapplicability to Capacitive Loads

It is known that the electrical loads can be classified into resistive, capacitive, and inductive ones. A capacitive load is an AC electrical load in which the current wave reaches its peak before the voltage, like the flash of the camera; while an inductive load is a load that pulls a large amount of current when first energised, for example, motors, transformers, and wound control gear, and a resistive load is a load which consumes electrical energy in a sinusoidal manner. This means that the current flow is in time with and directly proportional to the voltage, such as incandescent lighting and electrical heaters.

The impedance ZVS(s) in a two-port network is equivalent to a capacitor with very large 1 capacitance, which implies that ZVS(s) = −j ωC ≈ 0. In term of (2.11), one has VVL(s) = VVS(s). It is remarked if the load impedance ZL(s) is capacitive, a capacitive source oﬀers energy to a capacitive load, while VVL(s) = VVS(s) at a steady state implies that the voltage source inverter does not function, and is thus inapplicable to capacitive loads. It is concluded that, due to the impedance of a two-port network between the voltage source and the inverter bridges, the voltage source inverter has the problems of the shoot- through, limited output voltage gains, and inapplicability to capacitive loads, which restrain its wide applications.

2.2.2 Current Source Inverters

Open-Circuit

In terms of (2.3), the transmission matrix of the current source inverter in Fig. 2.4(b) reads

 AC11(s) = 1 ,   A (s) = 0 , C12 (2.12) A (s) = Y (s) ,  C21 CS  AC22(s) = 1 , where YCS(s) is the source admittance of the current source inverter, which is the reciprocal of its source impedance. Substituting (2.12) into (2.5) results in the input admittance of the current source inverter

1 AC21(s) + AC22(s) 1 YL(s) Yi(s) = = = YL(s) + YCS(s) , (2.13) Zi(s) 1 AC11(s) + AC12(s) YL(s) where YL(s) and YCS(s) are the load admittance and source admittance, respectively, as shown 2 Impedance Networks and Impedance Source Converters 15

in Fig. 2.4(b), while the input voltage of the current source is thus obtained as

ICS(s) VCS(s) = . (2.14) YL(s) + YCS(s) where ICS(s) is the current of current source, as shown in Fig. 2.4(b). An inverter normally includes at least one inverter bridge, while one inverter bridge is normally composed of one upper switch and one lower switch. At least one of the upper switches and one of the lower switches in the current source inverter must be kept on; otherwise, an open-circuit problem occurs and thus YL(s) = 0 in (2.14). Moreover, the source admittance

YCS(s) is normally very small, i.e. YCS(s) ≈ 0. Therefore, Yi(s) = YL(s) + YCS(s) ≈ 0, which

implies VCS(s) → ∞. Thus, the current source is an open-circuit and a very large voltage will break down the switches. In order to prevent the open-circuit problems, the overlapped time technique on upper and lower switches is normally utilized to ensure at least one of the upper switches and one of the lower switches being on at any time [58].

Limited Output Current Gains

In terms of (2.6), one can obtain the output admittance of the current source inverter as

1 AC21(s) + AC11(s) 1 YCS(s) Yo(s) = = = YCS(s) , (2.15) Zo(s) 1 AC22(s) + AC12(s) YCS(s) while the output current is

ICL(s) = ICS(s) − VCS(s)YCS(s) . (2.16)

For VCS(s),YCS ≥ 0, one has ICL ≤ ICS, namely, the load current ICL(s) is lower than or

equal to the source current ICS(s).

Inapplicability to Inductive Loads

The admittance YCS(s) in a two-port network is equivalent to an inductor with very large 1 inductance, which implies that YCS(s) = −j ωL ≈ 0. It is remarked if the load admittance YL(s) is inductive, an inductive source oﬀers energy to an inductive load, while ICL(s) = ICS(s) at a steady state implies that the current source inverter does not work and is thus inapplicable to inductive loads. It is concluded that, due to the admittance of the two-port network between the current source and the inverter bridges, the current source inverter has the problems of open-circuit, limited output current gains, and inapplicability to inductive loads. 16 2 Impedance Networks and Impedance Source Converters

2.3 Z-Source Inverters

Peng [23] has proposed to use an impedance network (named as Z-network) in 2002, as shown in Fig. 2.6, to couple with a DC source to form a novel source, as shown in the rectangles in Fig. 2.7, including voltage- and current-type Z-source inverters. Applying this Z-source technology in other converters results in Z-source DC-DC converters (Fig. 2.5(a)), Z-source AC-DC rectifiers (Fig. 2.5(b)), and Z-source AC-AC converters (Fig. 2.5(c)).

(a) DC-DC converters

(b) AC-DC rectifiers

Fig. 2.5: Other typical Z-source converters

Similarly, voltage-type Z-source inverters are also taken as examples, for simplicity, to explain the reasons that Z-source converters can overcome the problems of voltage source and current source converters. The diagram of a voltage-type Z-source inverter is drawn in Fig. 2.7(a), 2 Impedance Networks and Impedance Source Converters 17 whose equivalent two-port network is illustrated in the dashed box in Fig. 2.8.

Assume L1 = L2 = L and C1 = C2 = C, and denote the impedance of diode D by ZZS(s).

Fig. 2.6: A Z-network

(a) Voltage-type (b) Current-type

Fig. 2.7: Z-source inverters

In terms of (2.2), one can obtain the transmission matrix of the Z-network as follows " # AZ11(s) AZ12(s) AZ(s) = , (2.17) AZ21(s) AZ22(s) where, in terms of (2.3), the elements write

 2  1 + s LC  AZ11(s) = ,  1 − s2LC   2sL   AZ12(s) = 2 , 1 − s LC (2.18)  2sC  A (s) = ,  Z21 2  1 − s LC  2  1 + s LC  AZ22(s) = . 1 − s2LC 18 2 Impedance Networks and Impedance Source Converters

Fig. 2.8: Equivalent circuit of voltage-type Z-source inverters with two-port network

Substituting ZS(s) = ZZS(s), ZL(s) = ZZL(s) and (2.18) into (2.5) and (2.6) results in the input and output impedances of the Z-network as

 2 AZ11(s)ZZL(s) + AZ12(s) (s LC + 1)ZZL(s) + 2sL  Z (s) = = ,  Zi 2  AZ21(s)ZZL(s) + AZ22(s) s LC + 2sCZZL(s) + 1 (2.19)  2  AZ22(s)ZZS(s) + AZ12(s) (s LC + 1)ZZS(s) + 2sL   ZZo(s) = = 2 , AZ21(s)ZZS(s) + AZ11(s) s LC + 2sCZZS(s) + 1 where ZZS(s) is the source impedance of the input port of the Z-network and ZZL(s) is the load impedance of the output port of the Z-network, described as ( 0, if D is on, ZZS(s) = (2.20) ∞, otherwise, and  0, at a shoot-through state,  ZZL(s) = ∞, at an open-circuit state, (2.21)   ZZ(s), at a normal state, where ZZ(s) is the load impedance of the inverter bridge. Substituting (2.20) and (2.21) into (2.19) leads to the input and output impedances as   2sL  , at a shoot-through state,  s2LC + 1     s2LC + 1 ZZi(s) = , at an open-circuit state, (2.22)  2sC     (s2LC + 1)Z (s) + 2sL  Z  2 , at a normal state,  2sCZZ(s) + s LC + 1 2 Impedance Networks and Impedance Source Converters 19

and   2sL  , if D is on,  2  s LC + 1 ZZo(s) = (2.23)   s2LC + 1  , otherwise.  2sC

Immunity to the Shoot-Through

The input current of the Z-source inverter is expressed as

VZS(s) IZS(s) = , (2.24) ZZi(s) where ZZL(s) = 0 if the switches on a bridge are turned on simultaneously. It is obvious that

ZZi(s) 6= 0 holds in all cases in terms of (2.22). Therefore, the Z-source inverter can operate at shoot-through states. Compared to the voltage source inverter, Z-source inverter is immune to the shoot-through problem, so that the short-circuit phenomenon at the source can be avoided because the Z-network increases the input impedance.

High Output Voltage Gains

Denote the duty cycle of the diode D as d and assume d ∈ [0, 1]. In terms of (2.23), one can obtain the average output impedance as   2(1 + d) ! 1 4 2 s + s +  (1 − d)L  (1 − d)LC L2C2   ZZo(s) =   , (2.25) 2  1   s3 + s  LC

while the output voltage of the Z-source inverter, VZL(s), is expressed as

VZL(s) = VZS(s) − IZL(s)ZZo(s) . (2.26)

It is obvious that ZZo(s) is the function of the duty d in terms of (2.25). Adjusting ZZo(s)

to be negative or positive via d, one can obtain either VZL(s) > VZS(s) or VZL(s) < VZS(s), which implies that the Z-source inverters can overcome the limited voltage gains of traditional voltage source inverters.

Applicability both to Capacitive and Inductive Loads

Assume that ZZ(s) is capacitive. Then, in terms of (2.23), one has 1 ZZ(s) = , (2.27) sCL 20 2 Impedance Networks and Impedance Source Converters

where CL is the capacitance of the load. By adjusting the duty d, and the inductance L, capacitance C of the Z-network, the output impedance of the Z-network can exhibit the inductive feature, implying that the Z- source inverter is applicable to a capacitive load.

Similarly, assume that ZZ(s) is inductive and one can also prove that the Z-source inverter is also capable of an inductive load. It is thus concluded that due to the embedded Z-network, Z-source inverters have unique advantages over traditional ones, i.e. immunity to the shoot-through, higher output voltage gains, and applicability both to capacitive and inductive loads, which have a great potential in renewable energy applications.

2.4 State-of-The-Art of Impedance Source Converters

Based on the typical Z-source converters proposed by Peng, various impedance source converters have been proposed for diﬀerent speciﬁed applications, such as quasi-Z-source converters, trans- Z-source converters, embedded-Z-source converters, which are to be reviewed in this section.

2.4.1 Quasi-Z-Source Converters

Inspired by the typical Z-source converters, Anderson and Peng have firstly proposed quasi- Z-source converters in 2008, which are mainly applied in motor systems, new energy systems, and micro-grid systems. According to the operational modes in voltage-type or current-type and continuous or discontinuous current, quasi-Z-source converters can be classiﬁed into four categories, i.e. voltage-fed quasi-Z-source inverters with continuous input current, voltage-fed quasi-Z-source inverters with discontinuous input current, current-fed quasi-Z-source inverters with continuous input current, and current-fed quasi-Z-source inverters with discontinuous input current, which are shown in Fig. 2.9 [63]. It is found by Cao and Peng [64] that all of the impedance networks in Fig. 2.9 can be derived from the one in Fig. 2.6. For instance, a voltage-fed quasi-Z-source inverter with continuous input current in Fig. 2.9(a) is equivalent to that in Fig. 2.10, whose switches S1 and S2 are equivalent to the diode D and the inverting bridge in Fig. 2.9(a), respectively. It is remarked that the impedance network in Fig. 2.10 is a typical quasi-Z-network, based on which various quasi-Z-networks can be derived. For example, Cao and Peng have proposed a family of quasi-Z-source DC-DC converters [64], and Vinikov et.al. have also proposed some novel quasi-Z-source DC-DC converters for renewable energy systems [65]. Similar to the analysis of the typical Z-source converters, features of quasi-Z-source converters can also be analyzed in terms of the two-port network theory. Here, the voltage-fed quasi-Z-source inverter is taken as an example and its equivalent circuit with the two-port 2 Impedance Networks and Impedance Source Converters 21

(a) Voltage-fed one with continuous current

(b) Voltage-fed one with discontinuous current

(d) Current-fed one with discontinuous current

Fig. 2.9: Quasi-Z-source inverters [63] 22 2 Impedance Networks and Impedance Source Converters

Fig. 2.10: Equivalent circuit of the converter in Fig. 2.9 [64]

network is shown as Fig. 2.11. Therein, assume L1 = L2 = L, C1 = C2 = C, and denote the inverter bridge with the load by ZQL(s).

Fig. 2.11: Equivalent circuit of voltage-fed quasi-Z-source inverters with two-port network

In terms of (2.2), one can obtain the transmission matrix of quasi-Z-network as follows

" # AQ11(s) AQ12(s) AQ(s) = , (2.28) AQ21(s) AQ22(s) where  2 AQ11(s) = s LC + 1 ,   A (s) = 2sL ,  Q12 AQ21(s) = sC , if D is on. (2.29)  2  2s LC + 1  AQ22(s) = , 1 + s2LC 2 Impedance Networks and Impedance Source Converters 23

Substituting ZS(s) = ZQS(s) and ZL(s) = ZQL(s) into (2.5) and (2.6) results in the input and output impedances of the quasi-Z-network as

 2  (s LC + 1)ZQL(s) + 2sL  ZQi(s) = ,  2  2s LC + 1  sCZQL(s) + s2LC + 1 if D is on. (2.30)    2sL  Z (s) = ,  Qo s2LC + 1 As diode D turns off, the elements in the transmission matrix (2.28) write

 A (s) = 2 ,  Q11  2  1 + s LC  AQ12(s) = , sC if D is oﬀ. (2.31)  sC  AQ21(s) = ,  1 + s2LC   AQ22(s) = 1 , Similarly, one can obtain its input and output impedances as

 2 2 2 2(s LC + 1)sCZQL(s) + (s LC + 1)  Z (s) = ,  Qi 2 2 2  s C ZQL(s) + sC(s LC + 1) if D is oﬀ. (2.32)  2  s LC + 1  ZQo(s) = , sC Denote the duty cycle of the diode D as d ∈ [0, 1]. The averages of the input and output impedances are given by  (s2LC + 1)Z (s) + 2sL 2s(s2LC + 1)CZ (s) + (s2LC + 1)2  QL QL  ZQi(s) = d + (1 − d) ,  2 s2C2Z (s) + sC(s2LC + 1)  2s LC + 1 QL  sCZ (s) +  QL s2LC + 1   2 !  2sdL s LC + 1  ZQo(s) = + (1 − d) .  s2LC + 1 sC (2.33)

Immunity to Shoot-Through

The input current of the quasi-Z-source inverter is expressed as

VQS(s) IQS(s) = . (2.34) ZQi(s) 24 2 Impedance Networks and Impedance Source Converters

In terms of (2.30) and (2.32), it is obvious that ZQi(s) 6= 0 holds in any conditions, i.e. the current will not be inﬁnite according to (2.34), which implies that the quasi-Z-source inverter is immune to the shoot-through problems.

High Output Voltage Gains

The output voltage of the quasi-Z-source inverter VQL(s) reads

VQL(s) = VQS(s) − IQL(s)ZQo(s). (2.35)

In terms of (2.33), it is found that ZQo(s) varies with d. In addition, one can obtain

VQL(s) > VQS(s) by adjusting d, which implies that the output voltage of the quasi-Z-source inverters can be higher than the input voltage.

Applicability both to Capacitive and Inductive Loads

Assume that the load impedance in (2.33) is capacitive. By adjusting the duty d, and the inductance L, capacitance C of the quasi-Z-network, the output impedance of the quasi-Z- network can exhibit the inductive feature, which implies that the energy is exchanged between the inductive quasi-Z-network and the capacitive load for inversion, i.e. the quasi-Z-source converter is applicable to a capacitive load. Similarly, it can be proved that the quasi-Z-source inverter is also applicable to an inductive load. It is thus concluded that due to the embedded quasi-Z-network, quasi-Z-source inverters have unique advantages over traditional ones, i.e. immunity to the shoot-through, higher output voltage gains, and applicability both to capacitive and inductive loads.

2.4.2 Trans-Z-Source Converters

Compared with traditional voltage source converters, whose voltage gains are normally in scale of 5 ∼ 6, typical Z-source and quasi-Z-source converters can obtain much larger voltage gains in scale of 20, which are, however, still not large enough for some special applications. For example, voltage gains of converters utilized in solar energy systems need to reach the scales of decades or even hundreds. In 2010, Qian and Peng et.al have integrated the transformers or coupled inductors into the Z-networks (shown in Fig. 2.6) and quasi-Z-networks (shown in Fig. 2.10) to construct trans-Z-networks as shown in the dashed box in Fig. 2.12 [66], and thus various trans-Z-source converters can be coined. In terms of different operational modes of input current and coupled inductors, trans- Z-source converters can be classified into six categories, i.e. voltage-fed trans-quasi-Z-source 2 Impedance Networks and Impedance Source Converters 25

(a) Voltage-fed one (b) Current-fed one

(e) Voltage-fed trans-quasi-Z-source one (f) Current-fed trans-quasi-Z-source one

Fig. 2.12: Typical trans-Z-source converters [66] inverters, current-fed trans-quasi-Z-source inverters, voltage-fed trans-quasi-Z-source inverters with coupled inductors, current-fed trans-quasi-Z-source inverters with two coupled inductors, voltage-fed trans-quasi-Z-source inverters, and current-fed trans-quasi-Z-source inverters, as shown in Fig. 2.12. Therein, trans-Z-source converters not only maintain the main features of traditional Z-source converters, but also exhibit some unique advantages, i.e. increased voltage gains and reduced voltage stress in the voltage-fed trans-Z-source inverters due to the transformers or coupled inductors, and the expanded operation quadrant in the current-fed trans-Z-source inverters. However, transformers and coupled inductors increase volume and cost. Similar to the typical Z-source converters, trans-Z-source converters can be also analyzed using the two-port network theory. Here, the voltage-fed quasi-Z-source inverter is taken as an example and its equivalent circuit with a two-port network is depicted in Fig. 2.11. 26 2 Impedance Networks and Impedance Source Converters

Denote the mutual inductance between the coupled inductors L and L as M, and the 1 2 √ inverter bridge with the load as ZTL(s), assume L1 = L2 = L, then one has M = n L1L2 = nL, where n is the turn ratio between L1 and L2.

Fig. 2.13: Equivalent circuit of trans-Z-source inverters with two-port networks

In terms of (2.2), the transmission matrix of trans-Z-network is given as " # AT11(s) AT12(s) AT(s) = . (2.36) AT21(s) AT22(s) When the diode D is on, the elements in (2.36) write  A (s) = 1 ,  T11     (1 + ns2LC)sL  A (s) = sL + ,  T12 (n + 1)s2LC + 1 if D is on, (2.37)    AT21(s) = 0 ,      AT22(s) = 1 , then, the input impedance ZTi(s) and the output impedance ZTo(s) are given by

 (ns2LC + 1)sL  Z (s) = Z (s) + sL + ,  Ti TL 2  (n + 1)s LC + 1 if D is on, (2.38)   (ns2LC + 1)sL  Z (s) = sL + ,  To (n + 1)s2LC + 1 2 Impedance Networks and Impedance Source Converters 27

where ZTS(s) and ZTL(s) are the equivalent source and load impedances, respectively. When the diode D is off, the elements in (2.36) read  A (s) = 1 ,  T11     1   AT12(s) = (n + 1)sL + , sC if D is off. (2.39)    AT21(s) = 0 ,      AT22(s) = 1 ,

Similarly, one can obtain the input impedance ZTi(s) and the output impedance ZTo(s) as  1   ZTi(s) = ZQL(s) + (n + 1)sL + ,  sC if D is off. (2.40)   1  Z (s) = (n + 1)sL + ,  To sC Denote the duty cycle of the diode D as d ∈ [0, 1]. The average of the input and output impedance are then obtained as  (2 + (2n + 1)s2LC)sL 1 !   ZTi(s) = ZTL(s) + d + (1 − d) (n + 1)sL + ,  1 + (n + 1)s2LC sC  (2.41)  2 !  (2 + (2n + 1)s LC)sL 1  ZTo(s) = d + (1 − d) (n + 1)sL + .  1 + (n + 1)s2LC sC

Immunity to the Shoot-Through

The input current of the trans-Z-source inverter is derived as

VTS(s) ITS(s) = . (2.42) ZTi(s)

In terms of (2.41), the input impedance ZTi(s) can prevent the shoot-through occurring by adjusting the duty d to ensure ZTi(s) 6= 0 at any case, which implies that the trans-Z-source inverter is immune to the shoot-through.

High Output Voltage Gains

The output voltage gain of trans-Z-source inverter VTL(s) reads

VTL(s) = VTS(s) − ITL(s)ZTo(s) . (2.43) 28 2 Impedance Networks and Impedance Source Converters

In terms of (2.41), one can obtain VTL(s) > VTS(s) by adjusting ZTo(s) via duty d, which implies that the output voltage can be higher than the input voltage to realize high voltage gains. The fact that ZTo(s) is proportional to n in (2.41) ensures that the output voltage gains of tran-Z-source inverters can be larger than the ones of traditional Z-source converters.

Applicability both to Capacitive and Inductive Loads

Assume that the load impedance in (2.41) is capacitive. By adjusting the duty d, and the inductance L, capacitance C of the trans-Z-network, the output impedance of the trans-Z- network can exhibit the inductive feature, which enables the energy exchange between the trans-Z-network and the capacitance load. Therefore, the trans-Z-source inverter is applicable to a capacitive load. Similarly, it can be proved that the trans-Z-source inverter is also applicable to an inductive load. It is thus concluded that trans-Z-source inverters not only possess the features of typical Z-source inverters, but also obtain higher voltage gains than traditional ones.

2.4.3 Embedded-Z-Source Converters

In order to obtain smaller volume and higher robustness, P.C. Loh et.al proposed embedded- Z-source converters in 2010 [67]. Instead of using an external LC filter, they proposed an alternative family of embedded-Z-source inverters, which adopts the concept of embedding the input DC sources within the LC impedance network, using its existing inductive elements for current filtering in voltage-type embedded-Z-source inverters, and its capacitive elements for voltage filtering in current-type embedded-Z-source inverters. The typical topologies can be classified into two-level type and three-level type, as shown in Fig. 2.14. Similarly, one can use the two-port network theory to analyze embedded-Z-source inverters. It is concluded that the embedded-Z-source inverters not only maintain the features of typical Z-source inverters, but also produce smaller ripples of input voltage and current.

2.4.4 Other Impedance Source Converters

Since the proposal of Z-source converters in 2002, various Z-source converters have been proposed, e.g. Y-source converters (Fig. 2.15) [68], Γ-Z-source converters (Fig. 2.16) [69]-[72], LCCT-Z-source converters (Fig. 2.17) [73]-[74], and Z-H-source converters (Fig. 2.18) [75], to list just a few. Y-source converters shown in Fig. 2.15 are designed based on trans-Z-source converters, which, however, realize a higher voltage gain by using a smaller duty ratio. 2 Impedance Networks and Impedance Source Converters 29

(a) Two-level type

(b) Three-level type

Fig. 2.14: Typical embedded-Z-source converters [67] 30 2 Impedance Networks and Impedance Source Converters

Fig. 2.15: Y-source converters [68]

Γ-Z-source converters shown in Fig. 2.16 use fewer components and a coupled transformer to provide a high voltage gain, and they are essentially derived from the trans-Z-source converters. Therein, two Γ-shaped inductors (Fig. 2.16(a)) are coupled in trans-Z-source converters to form Γ-Z-source converters. Moreover, a voltage source is embedded in the Γ-shaped network in Fig. 2.16(b); therefore, it is also an embedded-Z-source converter. LCCT-Z-source converters (LCCT stands for the inductor-capacitor-capacitor-transformer) shown in Fig. 2.17 are extended from trans-Z-source inverters and have unique features, such as the converter in Fig. 2.17(b), whose two built-in DC blocking capacitors, cascaded with transformer windings, can prevent the transformer from saturation, while the one in Fig. 2.17(a), whose one built-in DC capacitor, cascaded with transformer windings, possesses the features of both quasi-Z-source and trans-Z-source converters. Fig. 2.18 depicts a Z-H-source converter, which contains fewer components, but own the same functions as traditional Z-source converters.

2.5 Summary

Up to now, there have been more than 1100 papers about impedance source converters published in various professional journals [24, 25], e.g. F.Z. Peng [76], P.C. Loh [77]-[88], Y. Tang [89]-[93], J.W. Jung [94, 95, 96], A.Y. Varjani [97]-[100], D. Vinnikov [101]-[104], to name just a few. It shows that designing new impedance source converters has attracted more and more attentions from scientists and engineers. Rapidly developing renewable energy industry has posed more stringent and higher requirements on power electronics, especially high quality converters. Unfortunately, until now designing an impedance source converter is still an art, lacking a systematic designing methodology, which can not fulﬁl the industrial requirements. Due to the important role of impedance networks, which are coupled with traditional con- 2 Impedance Networks and Impedance Source Converters 31

(a) Source placed in series with diode

(b) Source placed in series with inverter bridge

Fig. 2.16: Γ-Z-source converters [69] verters to construct impedance source converters, the impedance networks matching mechanism is to be investigated in the next chapter, and a systematic designing methodology can thus be proposed. 32 2 Impedance Networks and Impedance Source Converters

(a) One blocking capacitor type

(b) two blocking capacitors type

Fig. 2.17: LCCT-Z-source converters [73]

Fig. 2.18: Z-H-source converters [75] 3 Impedance Networks Matching Mechanism 33

Chapter 3

Impedance Networks Matching Mechanism

This chapter constitutes the key part of the dissertation. The impedance networks matching mechanism is to be investigated and a systematic design methodology is to be proposed.

3.1 Impedance Matching

In electronics, impedance matching is the practice of designing the input impedance of an electrical load or the output impedance of its corresponding signal source to maximize the power transfer or minimize signal reﬂection from the load [105]. In terms of the maximum power-transfer theorem, the load impedance should match the source impedance in order to transfer the maximum amount of power from a source to a load. That is to say, maximum power is transferred from a source to a load when the load resistance equals the internal resistance of the source. For DC, it is well known that maximum power transfer can be achieved if source resistance is equal to the load resistance; while for radio frequency (RF), impedances should be considered, and impedance matching aims to make the real part of the impedance equal to the real part of the load and the real part of reactance equal and opposite in character [50]. The concept of impedance matching deals originally with linear circuits, and is not directly applicable to power converters, which are essentially nonlinear switched circuits. Nevertheless, in each operational mode, a power converter works as a linear circuit, which results in the time-varying characteristics of the impedances matching for impedance networks matching. Therefore, the concept of the impedance matching can be extended to the impedance network matching in three aspects: input impedance matching, output impedance matching, and load phase matching. 34 3 Impedance Networks Matching Mechanism

3.2 Input Impedance Matching

Substituting s = jω into the input impedance of the two-port network in (2.5) results in ! ! A11(jω)ZL(jω) + A12(jω) A11(jω)ZL(jω) + A12(jω) Zi(jω) = Re + jIm . (3.1) A21(jω)ZL(jω) + A22(jω) A21(jω)ZL(jω) + A22(jω)

The shoot-through state implies that ZL(jω) = 0, so the input impedance in shoot-through state is derived as ! ! A12(jω) A12(jω) Zi(jω) = Re + jIm , (3.2) A22(jω) A22(jω) whereas the input current of the voltage source at the shoot-through states is expressed as

VS(jω) VS(jω) IS(jω) = = ! ! . (3.3) Zi(jω) A12(jω) A12(jω) Re + jIm A22(jω) A22(jω)

Since inductive components hinder their current change, it is then obvious that the converter can restrain the short-circuit current if its input impedance in (3.2) is inductive.

! A12(jω) Im > 0. (3.4) A22(jω)

Voltage Source Inverters

Suppose that the inverter bridge of the voltage source inverter is short-circuited. In terms of (3.2), the input impedance of the voltage source inverter writes

Zi(jω) = Re (ZS(jω)) + jIm (ZS(jω)) , (3.5) where ZS(jω) is its equivalent source impedance and ZS(jω) is equivalent to a capacitor with a large capacitance, i.e. Im (ZS(jω)) < 0. Here, in terms of (3.4), the voltage source inverter does not function for cases of inverter bridges being short-circuited.

Typical Z-Source Inverters

In terms of (2.18) and (3.2), the input impedance in the shoot-through case of the typical Z-source inverter reads

j2ωL ! j2ωL ! Z (jω) = Re + jIm , (3.6) i 1 − ω2LC 1 − ω2LC 3 Impedance Networks Matching Mechanism 35

2ωL where the imaginary part of (3.6) is . 1 − ω2LC If the switching frequency f of the diode D and the impedance network parameter LC satisfy the condition 1 f < √ , (3.7) 2π LC

2ωL then > 0, which means that the input impedance is inductive and satisfies the 1 − ω2LC condition (3.4). Consequently, the typical Z-source inverter can operate in shoot-through states.

Quasi-Z-Source Inverters

In terms of (3.2), (3.4), (2.29) and (2.31), the imaginary part of the quasi-Z-source inverter’s input impedance in shoot-through case writes  2ωL(1 − ω2LC)  , if D is on, !  2 AQ12(jω)  1 − 2ω LC Im = (3.8) AQ22(jω)   2ωC  , otherwise.  1 − ω2LC

If the switching frequency f of the diode D and the impedance network parameter LC satisfy the condition 1 f < √ , (3.9) 2π 2LC ! AQ12(jω) then Im > 0, implying that the input impedance is inductive and satisfies the AQ22(jω) condition (3.4). Therefore, the quasi-Z-source converter can operate in shoot-through states.

Trans-Z-Source Inverters

For a trans-Z-source inverter, in terms of (3.2), (3.4), (2.37) and (2.39), when the inverter bridge is short-circuited, the imaginary part of the input impedance reads

 2  ωL(2 − (2n + 1)ω LC)  , if D is on, !  1 − (n + 1)ω2LC AT12(jω)  Im = (3.10) AT22(jω)  2  1 − (n + 1)ω LC  − , otherwise. ωC 36 3 Impedance Networks Matching Mechanism

If the switching frequency f of the diode D and the impedance network parameter LC satisfy the condition 1 f > v , (3.11) u ! u 1 2πt n + LC 2

! AT12(jω) then Im > 0, which implies that the input impedance is inductive and satisfies AT22(jω) the condition (3.4). Therefore, the trans-Z-source inverter can operate in shoot-through states.

3.3 Output Impedance Matching

Substituting s = jω into the output voltage equation VL(s) = VS(s) − IL(s)Zo(s) results in

VL(jω) = VS(jω) − IL(jω)Zo(jω). It is remarked that in order for the output voltage to be higher than the source voltage, the output impedance Zo(jω) should be negative; otherwise, the output impedance Zo(jω) should be positive. Substituting s = jω into (2.6) leads to the output impedance of the two-port network as ! ! A22(jω)ZS(jω) + A12(jω) A22(jω)ZS(jω) + A12(jω) Zo(jω) = Re + jIm , (3.12) A21(jω)ZS(jω) + A11(jω) A21(jω)ZS(jω) + A11(jω) while the corresponding output voltage is

ZL(jω) VL(jω) = VS(jω) . (3.13) ZL(jω) + Zo(jω)

It is obvious that |VL(jω)| > |VS(jω)|, if the voltage gain M satisfies the condition M > 1, namely,

p 2 2 [Re(ZL(jω))] + [Im(ZL(jω))] = p 2 2 [Re(ZL(jω)) + Re(Zo(jω))] + [Im(ZL(jω)) + Im(Zo(jω))]

> 1, 3 Impedance Networks Matching Mechanism 37 from which one has

2 2 2 2 [Re(ZL(jω))] + [Im(ZL(jω))] > [Re(ZL(jω)) + Re(Zo(jω))] + [Im(ZL(jω)) + Im(Zo(jω))] , (3.15) which can be further simplified as

2 2 2[Re(ZL(jω))Re(Zo(jω)) + Im(ZL(jω))Im(Zo(jω))] + [Re(Zo(jω))] + [Im(Zo(jω))] 2 = 2[Re(ZL(jω))Re(Zo(jω)) + Im(ZL(jω))Im(Zo(jω))] + |Zo(jω)| < 0. (3.16) Then, if one has

2 |Zo(jω)| Re(Z (jω))Re(Z (jω)) + Im(Z (jω))Im(Z (jω)) < − < 0 , (3.17) L o L o 2

(3.14) holds. That is, if Re(ZL(jω))Re(Zo(jω) < 0 or Im(ZL(jω))Im(Zo(jω)) < 0, and their sum is smaller than 0, then (3.17) holds. Moreover, it is suggested from (3.17) that the real parts of the load impedance and the output impedance should have opposite signs, or the imaginary parts of the load impedance and the output impedance should have opposite signs. This means that the output impedance should have negative impedance features; otherwise, the output impedance exhibits positive impedance features.

Voltage Source Inverters

For a voltage source inverter, in terms of (2.10) and (3.12), its output impedance reads

Zo(jω) = ZVS(jω). (3.18)

From ZVS(jω) ≈ 0, it is obvious that (3.17) does not hold, the output impedance exhibits positive impedance feature, i.e. the output voltage is lower than the source voltage.

Typical Z-Source Inverters

In terms of (2.18) and (3.12), the average output impedance of a typical Z-source inverter is described by 2ωdL (1 − d)(1 − ω2LC)! Z (jω) = j − . (3.19) Zo 1 − ω2LC 2ωC Substituting (3.19) into (3.17) results in

 (1 − ω2LC)2  1 > d > ,  (1 + ω2LC)2 (3.20)    Im(ZZo(jω)) < −2Im(ZL(jω)) , 38 3 Impedance Networks Matching Mechanism or  (1 − ω2LC)2  0 < d < ,  (1 + ω2LC)2 (3.21)    Im(ZZo(jω)) > −2Im(ZL(jω)) .

If (3.20) or (3.21) is fulﬁlled, then (3.17) holds, which implies that the output impedance exhibits negative impedance feature and the converter realizes boost functions; otherwise, the output impedance exhibits positive impedance feature and the converter acts buck functions. When the parameters in a typical Z-source inverter, i.e. the capacitance, inductance, and frequency, are fixed, one can adjust the average output impedance to match the load impedance by tuning the duty d to realize either buck or boost function. Assume L = 1 µH, C = 63 µF and d = 0.5. The bode diagram of the average output voltage gain is shown in Fig. 3.1, which illustrates the relationships between the duty d and ω2LC in (3.20) and (3.21) with regard to the switching frequency f. It is remarked that the magnitude can be positive or negative, implying that a Z-source inverter can realize both boost and buck functions.

Fig. 3.1: Bode diagram of the output voltage gain of Z-source inverters 3 Impedance Networks Matching Mechanism 39

Quasi-Z-Source Inverters

In terms of (2.33) and (3.12), one obtains the average output impedance of a quasi-Z-source inverter as 2ωdL (1 − ω2LC)! Z (jω) = j − (1 − d) . (3.22) Qo 1 − ω2LC ωC Substituting (3.22) into (3.17) leads to  (1 − ω2LC)2  1 > d > ,  4 1 + ω LC (3.23)    Im(ZQo(jω)) < −2Im(ZL(jω)) , or  (1 − ω2LC)2  0 < d < ,  4 1 + ω LC (3.24)    Im(ZZo(jω)) > −2Im(ZL(jω)) . It is straightforward that (3.17) holds, if (3.23) or (3.24) is satisﬁed, implying that the output impedance exhibits negative impedance features for boost functions; otherwise, the output impedance exhibits positive impedance features for buck functions.

Trans-Z-Source Inverters

From (2.41) and (3.12), one has the average output impedance of a trans-Z-source inverter as

(2 − (2n + 1)ω2LC)ωL 1 − (n + 1)ω2LC!! Z (jω) = j d − (1 − d) . (3.25) To 1 − (n + 1)ω2LC ωC

Substituting(3.25) into (3.17) leads to

 (1 − (n + 1)ω2LC)2  1 > d > ,  (1 − nω2LC)2 (3.26)    Im(ZQo(jω)) < −2Im(ZL(jω)) , or  (1 − (n + 1)ω2LC)2  0 < d < ,  (1 − nω2LC)2 (3.27)    Im(ZZo(jω)) > −2Im(ZL(jω)) . Similarly, (3.17) holds, if (3.26) or (3.27) is satisﬁed, implying that the output impedance exhibits negative impedance features for boost functions; otherwise, the output impedance illustrates positive impedance features for buck functions. 40 3 Impedance Networks Matching Mechanism

In summary, the output impedance matching is to adjust the parameters of the impedance network and the operation conditions in order for the output impedance to be positive or negative. Thus, the inverter can exhibit either buck or boost functions by adapting the duty d to change the sign of the output impedance.

3.4 Load Phase Matching

In order to improve the load ability of the converter, so that the inverter is applicable to both inductive and capacitive loads, the output impedance phase of the inverter should be capacitive or inductive so as to match the load impedance for reducing the impedance phase angle of the inverter. Therein, the total impedance phase is the sum of the output impedance phase and load impedance phase. Moreover, the smaller the total impedance phase is, the larger the power factor of the inverter is. Therefore, the optimal condition is that its total impedance phase is 0◦. The impedance phase angle of the converter is given by

! Im (Zo(jω) + ZL(jω)) ϕ = arctan . (3.28) Re (Zo(jω) + ZL(jω))

In terms of (3.12),

! A22(jω)ZS(jω) + A12(jω) Im (Zo(jω) + ZL(jω)) = Im + ZL(jω) = 0 (3.29) A21(jω)ZS(jω) + A11(jω) implies that its impedance phase angle is 0◦. Moreover, (3.29) also can be further simplified to

! A22(jω)ZS(jω) + A12(jω) Im (ZL(jω)) = −Im (Zo(jω)) = −Im . (3.30) A21(jω)ZS(jω) + A11(jω)

Voltage Source Inverters

For a voltage source inverter, substituting (2.7) into (3.30) results in

Im (ZL(jω)) = −Im (ZS(jω)) . (3.31)

It is obvious that the source impedance of the voltage source inverter is a capacitor with a very large capacitance, thus, one has Im (ZS(jω)) < 0. Therefore, only when the load impedance ZL(jω) is inductive, i.e. Im (ZL(jω)) > 0, (3.31) holds, implying that the voltage source inverter is applicable to a capacitive load. 3 Impedance Networks Matching Mechanism 41

Typical Z-Source Inverters

For a typical Z-source inverter, substituting (2.18) into (3.30) results in

(1 − d)(1 − ω2LC) 2ωdL Im (Z (jω)) = −Im (Z (jω)) = − . (3.32) L Zo 2ωC 1 − ω2LC

(1 − ω2LC)2 1 > d > (3.33) (1 + ω2LC)2

implies that Im (ZZo(jω)) > 0 and Im (ZL(jω)) < 0, which implies that the inverter is applicable

to a capacitive load; otherwise, one has Im (ZZo(jω)) < 0 and Im (ZL(jω)) > 0, which means that the converter is applicable to an inductive load. Therefore, the impedance phase of the typical Z-source inverter can be matched to be 0◦ via duty d for load phase matching. Assume the impedance network parameters of the typical Z-source inverter as L = 1 µH, C = 63 µF and d = 0.5. The bode diagram of the output impedance as shown in Fig. 3.2 illustrates the relationships between the duty d and ω2LC with regard to the switching frequency f. Therein, the phase switches from 90◦ to −90◦, i.e. from inductive to capacitive, which indicates that the typical Z-source converter is applicable of any kind of load.

Fig. 3.2: Output impedance bode diagram of Z-source inverters 42 3 Impedance Networks Matching Mechanism

Quasi-Z-Source Inverters

For a quasi-Z-source inverter, substituting (2.29) and (2.31) into (3.30) results in

(1 − d)(1 − ω2LC) 2ωdL Im (Z (jω)) = −Im (Z (jω)) = − . (3.34) L Qo ωC 1 − ω2LC It is remarked that (1 − ω2LC)2 1 > d > , (3.35) 1 + ω4LC implies Im (ZQo(jω)) > 0 and Im (ZL(jω)) < 0, which means that the inverter is applicable of a capacitive load; otherwise, one has Im (ZQo(jω)) < 0 and Im (ZL(jω)) > 0, implying that the inverter is applicable of an inductive load. Therefore, the impedance of the quasi-Z- source inverter can be matched to be resistive by adapting the duty cycle to realize load phase matching.

Trans-Z-Source Inverters

For a trans-Z-source converter, substituting (2.37) and (2.39) into (3.30) results in

(1 − d)(1 − (n + 1)ω2LC) (2 − (2n + 1)ω2LC)ωdL Im (Z (jω)) = −Im (Z (jω)) = − . (3.36) L To ωC 1 − (n + 1)ω2LC

It is remarked that (1 − (n + 1)ω2LC)2 1 > d > (3.37) (1 − nω2LC)2 implies Im (ZTo(jω)) > 0 and Im (ZL(jω)) < 0, saying that the inverter is applicable of a capacitive load; otherwise, one has Im (ZTo(jω)) < 0 and Im (ZL(jω)) > 0, which means that the converter is applicable of an inductive load. Therefore, the impedance of the trans-Z- source inverter can be matched to be resistive by adapting the duty cycle to realize load phase matching. It is thus concluded that the load phase matching is to adapt the phase of output impedance for matching its load impedance. In detail, the parameters of the impedance network are adjusted to make the converter be suitable for any kind of loads and realize the total impedance phase angle close to 0◦.

3.5 Matching Optimization

The impedance networks matching contains input impedance matching, output impedance matching and load phase matching. Therein, input impedance matching is to increase the input impedance in the short-circuit case for making the input impedance inductive and then 3 Impedance Networks Matching Mechanism 43

to restrain the input current; output impedance matching is to tune the output impedance to be of positive or negative nature, so as to increase or decrease output voltage by connecting an impedance network or adjusting the impedance networks parameters; while load phase matching is to match the output impedance with the load impedance to ensure its impedance phase angle to be 0◦. Therefore, to design a reasonable and feasible impedance source converter, input impedance matching, output impedance matching and load phase matching are overall considered via parameters design to realize an optimal matching. From sections 3.2, 3.3 and 3.4, conditions for impedance network matching can be concluded as  A (jω)!  12  Im > 0 ,  A22(jω)     2  |Zo(jω)| Re(Z (jω))Re(Z (jω)) + Im(Z (jω))Im(Z (jω)) < − , (3.38)  L o L o 2     A (jω)Z (jω) + A (jω)!  22 S 12  Im (ZL(jω)) = −Im .  A21(jω)ZS(jω) + A11(jω)

To satisfy the conditions (3.38), it is concerned with the topologies and parameters of the impedance network, the source impedance, and the load impedance; while the matching process is to calculate the parameters of the impedance network in terms of (3.38) and other known parameters. A typical Z-source inverter is taken as an example to demonstrate the impedance matching process. 1 Assume that the load is capacitive, i.e. ZL(jω) = −j . Substituting the transmission ωCL parameters of the typical Z-source inverter (2.18) into (3.38), one can obtain the relationship equation of the parameters L, C, f and d as

 1   f < √ ,  2π LC     ω = 2πf ,   (3.39)  (1 − ω2LC)2  1 > d > ,  2 2  (1 + ω LC)     (1 − d)(1 − ω2LC) 2ωdL  Im (Z (jω)) = − .  L 2ωC 1 − ω2LC 44 3 Impedance Networks Matching Mechanism

Assume the input voltage of the typical Z-source inverter as 48 V, the switching frequency of the diode d as f = 60 kHz, the load CL = 1 µF, and the input-output voltage gain as M = 1.2. Further, letting d = 0.5 in (3.39), one can calculate L and C as L = 1 µH and C = 63 µF, respectively. Then, with the parameters of the typical Z-source inverter listed above, one can draw the bode diagram of the input current in the short-circuit case with blue color, the output voltage gains with green color and the output impedance with red color in Fig. 3.3, which are all consistent with the analysis above.

Fig. 3.3: Bode diagram of input current in the short-circuit case, output voltage gain and output impedance of typical Z-source inverters

3.6 Design Methodology of Power Converters

From the perspective of the impedance matching, designing a power converter concerns the following three aspects:

Input Impedance Matching: It is to ensure the converter to be immune to shoot-through problems and to improve its stability. 3 Impedance Networks Matching Mechanism 45

Output Impedance Matching: It is to endow the output impedance with positive or negative nature, so as to possess either buck or boost function.

Load Phase Matching: It is to minimize the impedance phase angle of the converter.

In this section, a systematic methodology for designing a power converter is to be proposed, which includes topology design, selection of impedance networks, input and output impedances calculation, operational status analysis, parameters determination, simulations and experiments, which are detailed in the following.

3.6.1 Topology Design

Different impedance networks topologies result in different features of converters. Even the identical impedance network topologies with different connectivity and components locations may result in different input and output impedances, and finally display different features of the converters. Therefore, the topology design of an impedance source converter deals with impedance network connectivity and components location assignment.

Impedance Network Connectivity Design

The impedance network connectivity refers to the terminals connectivity of two impedance networks. There are four terminals in each impedance network, which results in diﬀerent connectivity types of two-port networks, i.e. cascade, parallel, series-parallel, parallel-series, and series-series connectivity, as shown in Tab. 3.1, which also displays the parameter relationships of the impedance networks. Therein, A, Y, H, G, and Z are the transmission parameters matrix, admittance parameters matrix, hybrid parameters matrix, inverse hybrid parameters matrix and impedance parameters matrix, respectively. Moreover, the connectivity of two-port networks shown in Tab. 3.1 can be the connectivity between two impedance networks, between an impedance network and the source, or between an impedance network and a load.

Location of the Impedance Network

The location of an impedance networks can be varied.

1. As shown in Fig. 3.4(a), the impedance network can be located between the source and a part of the original converter, e.g. the converters in Figs. 2.7, 2.5(a), 2.9, 2.12, 2.15, 2.16(a), and 2.17.

2. As shown in Fig. 3.4(b), the impedance network can be located inside the original converter, e.g. the Z-source AC-AC converter in Fig. 2.5(c). 46 3 Impedance Networks Matching Mechanism

Table 3.1: Connectivity types of two-port networks and relationship of their parameters

Type Connectivity Relationships

Cascaded A = A1A2

Parallelled Y = Y1 + Y2

Series-parallel H = H1 + H2

Parallel-series G = G1 + G2

Series-series Z = Z1 + Z2

3. As shown in Fig. 3.4(c), the impedance network can be located between the original converter and the load, e.g. the Z-source AC-DC converter in Fig. 2.5(b) and the Z-H- source converter in Fig. 2.18.

3.6.2 Selection of An Impedance Network

Basic two-port impedance networks and their transmission parameters matrix are listed in

Tab. 3.2, where Zx = Z1Z2Z3Z4.

Denote the source impedance in the input port of the two-port network as Z2S and the load impedance in the output port of the two-port network as Z2L, and the corresponding input and output impedances can be expressed as given in Tab. 3.3 in terms of (2.5) and (2.6). Moreover, the impedance phase angle of two-port impedance network is given as 3 Impedance Networks Matching Mechanism 47

(a) Between source and converter

(b) Between the converter

Fig. 3.4: Location of an impedance network in converters 48 3 Impedance Networks Matching Mechanism

Table 3.2: Basic two-port impedance networks and their transmission parameters matrix

Networks type Figure Transmission matrix A

" # 1 Z Basic cascaded 1 0 1

" # 1 0 Basic parallelled 1 1 Z1

" Zx+Z1Z3+Z2Z4+1 Z1Z2Z4+Z1Z3Z4+Z1+Z4 # X-shaped 1−Zx 1−Zx Z1Z2Z3+Z2Z3Z4+Z2+Z3 Zx+Z1Z2+Z3Z4+1 1−Zx 1−Zx

" Z1+Z3 # Z1 π-shaped Z3 Z1+Z2+Z3 Z1+Z2 Z2Z3 Z2

" # 1 Z Γ-shaped 1 1 Z1+Z2 Z2 Z2

" Z1+Z2 # Z1 Inverse-Γ-shaped Z2 1 1 Z2

" Z1+Z2 Z1Z2+Z1Z3+Z2Z3 # T-shaped Z2 Z2 1 Z3+Z2 Z2 Z2

! Im (Zo + Z2L) ϕ = arctan . (3.40) Re (Zo + Z2L)

Substituting the output impedance Zo in Tab. 3.3 into (3.40) results in the corresponding impedance phase angles, which helps select proper impedance networks. 3 Impedance Networks Matching Mechanism 49

Table 3.3: Input and output impedances of two-port networks

Networks types Zi Zo

Basic cascaded Z2L + Z1 Z2S + Z1

Basic parallelled Z2LZ1 Z2SZ1 Z2L+Z1 Z2S+Z1

X-shaped ZXi ZXo

π-shaped (Z1+Z3)Z2Z2L+Z1Z2Z3 (Z1+Z2)Z3Z2S+Z1Z2Z3 (Z1+Z2+Z3)Z2L+(Z1+Z2)Z3 (Z1+Z2+Z3)Z2S+(Z1+Z3)Z2

Γ-shaped Z2Z2L+Z1Z2 (Z1+Z2)Z2S+Z1 Z2L+Z1+Z2 Z2S+Z+Z2

Inverse-Γ-shaped (Z1+Z2)Z2L+Z1 Z2Z2S+Z1Z2 Z2L+Z+Z2 Z2S+Z1+Z2 T-shaped (Z1+Z2)Z2L+ZT (Z3+Z2)Z2S+ZT Z2L+Z2+Z3 Z2S+Z2+Z1

(Zx + Z1Z3 + Z2Z4 + 1)Z2L + Z1Z2Z4 + Z1Z3Z4 + Z1 + Z4 *note1: ZXi = (Z1Z2Z3 + Z2Z3Z4 + Z2 + Z3)Z2L + Z1Z2 + Z3Z4 + Zx + 1

(Zx + Z1Z2 + Z3Z4 + 1)Z2S + Z1Z2Z4 + Z1Z3Z4 + Z1 + Z4 *note2: ZXo = (Z1Z2Z3 + Z2Z3Z4 + Z2 + Z3)Z2S + Z1Z3 + Z2Z4 + Zx + 1 *note3: ZT = Z1Z2 + Z1Z3 + Z2Z3

For example, the voltage source inverter can be treated as the basic two-port impedance network with its input port cascaded with the source and its output port cascaded with the

inverter bridge. Therefore, substituting the transmission parameters in Tab. 3.2, Z2L = ZVL,

Z2S = ZVS = 0, and Z1 = ZS into the corresponding equations in Tab. 3.3 results in the input, output impedances and its impedance phase angle as

  Zi = ZS + ZVL ,    Zo = ZS , (3.41)  Im (Z + Z )!  S VL  ϕ = arctan .  Re (ZS + ZVL)

An X-shaped two-port network is connected to the voltage source inverter to form a novel impedance source converter. Substituting the transmission parameters of X-shaped two-port network in Tab. 3.2 into corresponding equations in Tab. 3.3 and (3.40) results in the input, 50 3 Impedance Networks Matching Mechanism output impedance and its impedance phase angle as   (Zx + Z1Z3 + Z2Z4 + 1)ZZL + Z1Z2Z4 + Z1Z3Z4 + Z1 + Z4  Zi = ,  (Z1Z2Z3 + Z2Z3Z4 + Z2 + Z3)ZZL + Z1Z2 + Z3Z4 + Zx + 1      (Zx + Z1Z2 + Z3Z4 + 1)ZZS + Z1Z2Z4 + Z1Z3Z4 + Z1 + Z4  Zo = , (Z1Z2Z3 + Z2Z3Z4 + Z2 + Z3)ZZS + Z1Z3 + Z2Z4 + Zx + 1  !  (Zx + Z1Z2 + Z3Z4 + 1)ZZS + Z1Z2Z4 + Z1Z3Z4 + Z1 + Z4  Im + ZZL   (Z Z Z + Z Z Z + Z + Z )Z + Z Z + Z Z + Z + 1    1 2 3 2 3 4 2 3 ZS 1 3 2 4 x   ϕ = arctan   ,   (Z + Z Z + Z Z + 1)Z + Z Z Z + Z Z Z + Z + Z !   x 1 2 3 4 ZS 1 2 4 1 3 4 1 4   Re + ZZL   (Z1Z2Z3 + Z2Z3Z4 + Z2 + Z3)ZZS + Z1Z3 + Z2Z4 + Zx + 1 (3.42) where ZZS and ZZL are the source impedances of the input port and the load impedance of the output port in the X-shaped two-port network, respectively.

3.6.3 Input Impedance

In diﬀerent operational modes, a power converter works as diﬀerent linear circuits, which leads to the time-varying characteristics of impedance matching. Three cases of power converters, i.e. short-circuit, open-circuit, and normal operational cases, correspond to three input impedance cases of a two-port network. In short-circuit case, the output port of the two-port network is short-circuited, and its input impedance is Zis = Zi|Z2L=0. Similarly, the open-circuit case refers to the case that the output port of the two-port network is open-circuit, and its input impedance writes Zio = Zi|Z2L=∞. Further, the input impedance of a two-network in normal case refers to Zic = Zi. Finally, the input impedance in various cases is summarized in Tab. 3.4. short-circuit Case

According to Tab. 3.4, it is straightforward that the input impedance of the basic parallel type in short-circuit case is 0, implying that it lacks the ability of preventing from short-circuit case; while the basic cascade type also cannot prevent from the short-circuit case, when Z1 is very small, i.e. the voltage source inverter is also a typical cascade type but it cannot prevent from the short-circuit case because Z1 is close to 0.

Open-Circuit Case

According to Tab. 3.4, it is obvious that the open-circuit input impedance of the basic cascaded type is infinite, implying that it lacks of the ability preventing the open-circuit case in the load, while the basic parallelled type also cannot prevent the open-circuit case when Z1 = ∞, i.e. the current source inverter. 3 Impedance Networks Matching Mechanism 51

Table 3.4: Input impedances of two-port networks in different cases

Networks types short-circuit case Zis Open-circuit case Zio

Basic cascaded Z1 ∞

Basic parallelled 0 Z1

X-shaped Z1Z2Z4+Z1Z3Z4+Z1+Z4 Z1Z3+Z2Z4+Z1Z2Z3Z4+1 Z1Z2+Z3Z4+Z1Z2Z3Z4+1 Z1Z2Z3+Z2Z3Z4+Z2+Z3

π-shaped Z1Z2 (Z1+Z3)Z2 Z1+Z2 Z1+Z2+Z3

Z1Z2 Γ-shaped Z2 Z1+Z2

Z1 Inverse-Γ-shaped Z1 + Z2 Z2

Z1Z2+Z1Z3+Z2Z3 T-shaped Z1 + Z2 Z2+Z3

Normal Case

When a converter operates in a normal case, its input impedance of each two-port network is given in Tab. 3.3. Normally, one can obtain the average input impedance in one switching period with the corresponding control strategy as

Zi = d1Zis + d2Zio + (1 − d1 − d2)Zic , (3.43) where d1, d2, and 1 − d1 − d2 are the corresponding duty cycles of input impedances in three cases, respectively.

3.6.4 Output Impedance

Similarly, the output impedances of the two-port network can be obtained in three cases as follows.

Case 1: Z2S = 0

Suppose that the input port of the two-port network is connected with an ideal voltage source, i.e. Zos = Zo|Z2S=0. Substituting Z2S = 0 into the output impedance equations in Tab. 3.3 results in the corresponding output impedances in Tab. 3.5.

In terms of Tab. 3.5 that the output impedance of the basic cascade type in this case is Z1, and Z1 determines the features of the output impedance, which leads to low output voltage, e.g. the voltage source inverter in Fig. 2.3(a), where Z1 = ZS. It is obvious that the output 52 3 Impedance Networks Matching Mechanism

Table 3.5: Output impedances of two-port networks in different cases

Networks type Z2S = 0 Z2S → ∞

Basic cascaded Z1 → ∞

Basic parallelled 0 Z1

X-shaped Z1Z2Z4+Z1Z3Z4+Z1+Z4 Z1Z2+Z3Z4+Z1Z2Z3Z4+1 Z1Z3+Z2Z4+Z1Z2Z3Z4+1 Z1Z2Z3+Z2Z3Z4+Z2+Z3

π-shaped Z1+Z3 (Z1+Z2)Z3 Z1+Z3 Z1+Z2+Z3

Z1 Γ-shaped Z1 + Z2 Z2

Z1Z2 Inverse-Γ-shaped Z2 Z1+Z2

Z1Z2+Z1Z3+Z2Z3 T-shaped Z3 + Z2 Z2+Z1 voltage is lower than the input voltage due to the output impedance, and it can only load the inductive loads.

Case 2: Z2S → ∞

Suppose that the input port of the two-port network is open-circuited, i.e. Zoo = Zo|Z2S=∞.

Substituting Z2S = ∞ into the output impedance equations in Tab. 3.3 leads to the corresponding output impedances, given in Tab. 3.5. Case 3: Normal Case

Denote the output impedance in the normal case as Zoc in Tab. 3.3. It is remarked that the average output impedance in one switching period is given by

Zo = d3Zos + d4Zoo + (1 − d3 − d4)Zoc , (3.44) where d3, d4, and 1 − d3 − d4 are the corresponding duty cycles of input impedances in three cases, respectively. Similarly, the impedance phase of a converter can be obtained according to Tab. 3.5 and (3.40). Then, the input impedance matching, output impedance matching, and load phase matching are comprehensively analyzed to realize optimized matching.

3.6.5 Analysis of the Operational Status

Power switches in a power converter lead to different kinds of operational modes, which should be analyzed in detail to understand the overall performances of the converter. The analysis includes the energy transfer process and deductions of voltage and current relationships through 3 Impedance Networks Matching Mechanism 53 the law of conservation of energy, Kirchhoﬀ’s current and voltage laws, and other basic circuit laws.

3.6.6 Parameters Design

According to section and the impedance matching conditions in (3.38), the parameters of the converter are determined via the transmission parameters matrix.

3.6.7 Simulations and Experiments

According to the parameters obtained in section 3.6.6, simulations are conducted to verify the designed converters via circuit simulations softwares, e.g. MatLab-Simulink, PSIM and PSPICE.

3.7 Summary

Based on the analysis in last chapter, an impedance network matching mechanism, including input impedance matching, output impedance matching, and load phase matching, is firstly investigated in this chapter. Then, a systematic designing methodology is proposed for designing novel converters to fulﬁl the industrial requirements. In terms of the proposed designing methodology, four novel converters are designed and analyzed in the following three chapters, which solve the urgent problems in their corresponding industries. 54 3 Impedance Networks Matching Mechanism 4 A 3-Z-Network Boost Converter 55

Chapter 4

A 3-Z-Network Boost Converter

Modern industry, especially renewable energy industry like photovoltaic arrays and fuel cells [106], has posed quite high requirements on power electronics technology [107]–[110]. For instance, high-step-up DC-DC converters have been used to boost low voltages (18–56 V) to high voltages (200–400 V) for feeding into grid-connected inverters [111, 112]. Further, high- step-up and high-efficiency converters are also required in many other industrial applications, e.g. high-intensity discharge lamps for automobile headlights where the battery voltage of 12 V must raise up to 100 V [113], back-up energy conversions like non-interruptible power systems where the low battery voltage of 48 V must be boosted up to 380 V [114, 115], front-end stages of electric vehicles [116] and communication power systems [117, 118], and some other special applications like electroplating [119]. For those purposes, traditional boost converters or flyback converters have been normally adopted [120, 121, 122]. However, conventional boost converters are restricted by parasitic effects of their components and serious energy loss. Moreover, it is difficult to find high- voltage stress semiconductors or too expensive to apply in conventional boost converters due to limitations of semiconductor technology. In practical applications, the voltage gain of a conventional boost converter for a given duty-cycle d of the switching signal, namely Mcon = (1 − d)−1, is limited to about the voltage gain as 5-6, which is far away from industrial needs [123]. The flyback converters possess a higher voltage gain than the one of conventional boost converter, but at the expense of large corresponding leakage inductance and a complex structure [124]. To reach specified voltages, N boost converters can be cascaded to reach the voltage gain −N MN = (1 − d) . Cascaded boost converters are, however, too complex due to the additional switches and control units which also reduce system reliability [125]. A high-frequency isolation DC-DC converter with high transformer turn-ratio is applied to solve this problem [126], even though its efficiency is reduced due to its additional stage. This solution also compromises structure, volume and weight. In industrial applications, quadratic boost converters are the most popular cascaded ones, 56 4 A 3-Z-Network Boost Converter in which two switches and control circuits are excessively used, but which cannot ensure suffi- cient voltage gains. Further, many improvements were realized by cascading towards reducing current ripples and to achieve high voltage gains [127]-[131], e.g. a high-voltage-gain converter based on bootstrap capacitors and boost inductors [132], an optimized cascaded DC-DC converter with a high voltage gain for grid-connected systems [133] and different kinds of interleaved high-step-up converters [134, 135]. Since the insufficient voltage gains in practical applications, power converter with high voltage gains are required especially in solar energy systems. In terms of the impedance network matching mechanism, the disadvantage of traditional boost converter is presented, while in terms of the proposed systematic designing methodology, two kinds of 3-Z-network DC-DC boost converters with high voltage gains are proposed to solve the low output voltage problems in solar energy systems.

4.1 System Design

4.1.1 Disadvantage of Traditional Boost Converters

A traditional boost converter is shown in Fig. 4.1 with the dash diagram indicating the corresponding two-port impedance network.

Fig. 4.1: A boost DC-DC converter

From (2.3), one can obtain the transmission parameters matrix of the boost converter, and substituting the parameters into (3.1) results in the input impedance as

ZBi(jω) = jωL. (4.1) Similarly, one can also obtain different output impedances in different operational modes. Denote the duty cycle of the boost converter as d. Substituting d into (3.44) results in the average output impedance of the boost converter as ω2LC − d ! Z (jω) = j . (4.2) Bo (1 − ω2LC)ωC 4 A 3-Z-Network Boost Converter 57

Assume the source impedance of the boost converter in Fig. 4.1 as ZS(jω) = 0. In terms of (3.14), when ZBo(jω) + ZL(jω) = 0, one can obtain the largest voltage gain as

v u !2 |VL(jω)| u Im(−ZBo(jω)) Mmax = = t1 + . (4.3) |VS(jω)| Re(ZL(jω))

It is obvious that the larger the value Im(ZBo(jω)) is, the larger the voltage gain will be. Moreover, in terms of (4.2) the smaller d is, the larger the output impedance and the voltage gain can be obtained. Therefore, impedance networks are cascaded to increase the output impedance so as to realize high voltage gain. It is thus summarized that the output impedance and the load impedance can not be matched to realize high output voltage in the traditional boost converter. In order to realize higher voltage gains, impedance networks can be cascaded to increase the output impedance for increasing the voltage gain.

4.1.2 Selection of Impedance Networks

The basic cascade type of the two-port impedance network in Tab. 3.2 is adopted in the traditional boost converter. Replacing the inductor in Fig. 4.1 with a cascaded active two-port impedance network shown in Fig. 4.2 leads to the improved boost converter as shown in Fig. 4.3,

where L1 = L2 = L.

Fig. 4.2: A proposed impedance network

In terms of the voltage-second balance characteristics of inductors, one can obtain

Z dT Z T Z dT Z T VS − VC1 (vL1 )dt + (vL1 )dt = VSdt + dt = 0 (4.4) 0 dT 0 dT 2 58 4 A 3-Z-Network Boost Converter

Fig. 4.3: An improved boost converter from Fig. 4.3. Solving (4.4) results in the output voltage as 1 + d! V = V = V . (4.5) o C1 S 1 − d It is seen from (4.5) that the output voltage gain is (1 + d) times of that of the boost converter, which is, however, not large enough for boosting the voltage in solar energy systems. In terms of the equations in Tab. 3.1, one can obtain that the output impedance of two cascaded two-port networks is the multiple of each two-port network, so the cascaded connectivity method can be used to increase the output impedance. Therefore, cascading two identical converters in Fig. 4.3 will give rise to a novel boost converter as shown in Fig. 4.4.

Fig. 4.4: A cascaded boost converter

Such a design leads to some reductant components in the cascaded converters, which need to be simpliﬁed using the method proposed in [136], and two simpliﬁed converters are depicted in Fig. 4.5. One of the converter is analyzed as an example in the following part.

4.1.3 Calculation of Input and Output Impedances

In terms of the input and output impedances of two-port impedance networks in Tab. 3.3, the input impedance (ZBi) and output impedance (ZBo) of the converter in Fig. 4.5(a) write 4 A 3-Z-Network Boost Converter 59

(a) Simpliﬁed circuit 1

(b) Simpliﬁed circuit 2

Fig. 4.5: Simpliﬁed circuits of Fig. 4.4

  1  j ωL , if Q12 is on,  2   ZB(jω) ZBi(jω) = j2ωL + (4.6) 1 + jωZBi(jω)C  j2ωL + , otherwise,  Z (jω) !  B  1 + j2ωL + jωC  1 + jωZBi(jω)C

and  1  −j , if Q is on,  ωC 12 ZBo(jω) = 3 2 (4.7)  − 4ω L C + 4ωL  j , otherwise. 4ω4L2C2 − 6ω2LC + 1

It is remarked that the short-circuited input impedance in (4.6) satisfies the condition in (3.4), i.e. the short-circuited input impedance is inductive, therefore, it realizes input impedance matching. In terms of (4.7), one can obtain the desired high voltage by adjusting d. 60 4 A 3-Z-Network Boost Converter

4.2 Operational Modes Analysis

The converter in Fig. 4.5(a) is taken as an example to be analyzed. The converter contains three active impedance-networks in Fig. 4.6, i.e. Z-networks 1, 2 and 3, and is thus named as 3-Z-network boost converter. Therein, Z-network 1 functions as the first boost part, constituted of inductors L1 and L2, diodes D1, D2 and D3; Z-network 2 serves as the switch part, composed of switch Q, capacitor C1, diodes D4 and D5; and Z-network 3 acts as the second boost part, consisted of L3 and L4, diodes D6, D7 and D8. It is remarked that a distinct feature of the proposed converter is that there is only one switch used [137, 138].

Fig. 4.6: 3-Z-network boost converter

The instability of the output voltage in the solar energy leads to diﬀerent operational modes in the 3-Z-network boost converter, i.e. continue conduction mode (CCM) and discontinue conduction mode (DCM). For simplicity, it is assumed that a) all the components are ideal; b) the free-wheeling diode of the switch is ignored; c) L1 = L2 and L3 = L4. In the periodic states (on and oﬀ) of the switch Q, the inductors charge and discharge alternately. Correspondingly, their currents increase and decrease alternately. Then, there correspond some cases to the discontinuous current states of the inductors, named as discontinuous current cases. The states of the diodes and the currents of the capacitors correspond to six operational cases, including two CCMs and four DCMs, whose corresponding equivalent circuits are shown in Figs. 4.7(a)-4.7(f). Therein, vLi , i = 1, 2,..., 4 are voltages of Li, i = 1, 2,..., 4, respectively. Assume the clockwise direction as the positive direction of the reference currents, and the arrows in Fig. 4.7(a) refer to the positive directions of the inductors reference voltages. Moreover, the states of the components in the circuit are detailed in Tab. 4.1. 4 A 3-Z-Network Boost Converter 61

(a) Mode 1 (b) Mode 2

(e) Mode 5 (f) Mode 6

Fig. 4.7: Equivalent circuits of 3-Z-network boost converter

Table 4.1: States of switching components in different modes Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Q on off off off off off

D1 & D3 on off off off off off

D2 off on on on off off

D4 on off off off off off

D5 off on on on off off

D6 & D8 on off off off off off

D7 off on on off on off

D9 off on on off on off 62 4 A 3-Z-Network Boost Converter

4.3 CCM

It is known from the analysis above that there are continuous or discontinuous currents of inductors under some combinations of the inductances, the load and the duty. When the currents of inductors in Fig. 4.6 are all continuous, the converter operates in the continuous operational modes. Based on the different current directions of the capacitor C1, the continuous modes can be classiﬁed into two modes, i.e. Case 1: Mode 1 → Mode 2; Case 2: Mode 1 → Mode 2 → Mode 3, whose corresponding modes transition diagramms are shown in Fig. 4.8, where a mode stands for an operational mode.

Fig. 4.8: Transitions between modes in CCMs. (a) Case 1; (b) Case 2

4.3.1 Case 1

There are two modes in this case, namely, Modes 1 and 2 as shown Fig. 4.8(a), whose equivalent circuits are illustrated in Figs. 4.7(a) and 4.7(b).

Denote d as the duty of the switch Q, t0 the initial time of one period, t1 the mode transition instant from Mode 1 to Mode 2, and t2 = T the end of the period. In order to describe the operation process of the converter in Case 1, key waveforms of the proposed converter in the steady state are given in Fig. 4.9(a), where two modes are marked in two different colors within one period.

Moreover, Fig. 4.9(a)(1) describes the driven voltage vg of the switch Q; Fig. 4.9(a)(2) illustrates the waveform of iL1 (iL2 ), which is composed of two parts with the blue one referring to the waveform of iD1 (= iD3 ) and the red one to the waveforms of iD2 (= iD5 ); Fig. 4.9(a)(3) depicts the waveform of iL3 (iL4 ), which is also composed of two parts with the blue one referring to the waveform of iD6 (= iD8 ) and the red one to the waveform of iD7 (= iD9 ); Fig. 4.9(a)(4) portrays the waveforms of iC1 . Therein, iLi , i = 1, 2,..., 4, iDj , j = 1, 2,..., 9, and iCk , k = 1, 2 are the currents of Li, i = 1, 2,..., 4, Dj, j = 1, 2,..., 9, and Ck, k = 1, 2, respectively. 4 A 3-Z-Network Boost Converter 63

(a) Case 1 (b) Case 2

Fig. 4.9: Key waveforms of the 3-Z-network boost converter in CCMs

Mode 1: t ∈ [t0, t1]

As shown in Fig. 4.7(a), there are three loops in the circuit, marked in different colors, and the arrows in the circuit refer to the current directions in each loop. As Q turns on, the

diodes D1, D3 and D4 undertake positive voltages and turn on synchronously; meanwhile, D2

bears negative voltage and turns off. Thereafter, L1 and L2 are connected in parallel and then

cascaded with D4, Q and VS to form loop 1 with red lines. The source VS discharges the energy to L1 and L2, then iL1 and iL2 increase, and L1 and L2 store the energy. The waveforms (blue lines) of iD1 , iD3 , iL1 and iL2 are shown in Fig. 4.9(a)(2), where iD1 = iD3 = iL1 = iL2 ; and iD4 ,

which is the current of D4, endures iL1 + iL2 , namely, iD4 = iL1 + iL2 = 2iL1 . Accordingly, one has   iD1 = iD3 = iL1 = iL2 ,   i = 0 ,  D2 iD4 = iD1 + iD3 = 2iL1 , (4.8)  v = V ,  L1 S   vL2 = VS ,

where vL1 and vL2 are the voltages of L1 and L2, respectively.

Meantime, D5 and D7 undertake negative voltages and turn off, yet D6 and D8 endure

positive voltages and turn on. Accordingly, L3 and L4 are connected in parallel and then

cascaded with Q and C1 to form loop 2 in blue color. C1 discharges the energy to L3 and L4,

and iL3 and iL4 increase. Thus, L3 and L4 store energy. The waveforms of iD6 , iD8 , iL3 and iL4

are shown in blue color in Fig. 4.9(a)(3), and the waveform of iC1 is shown in Fig. 4.9(a)(4),

where iD6 = iD8 = iL3 = iL4 and iC1 = −2iL3 , respectively. 64 4 A 3-Z-Network Boost Converter

Then, one has   iD6 = iD8 = iL3 = iL4 ,   i = 0 ,  D5 iC1 = −2iL3 , (4.9)  v = v ,  L3 C1   vL4 = vC1 , where iL3 , iL4 , vL3 , vL4 and vC1 are the currents of L3, L4, and the voltages of L3, L4 and C1, respectively.

Meanwhile, D9 endures the negative voltage and turns off, then the capacitor C2 and the load R are cascaded to form loop 3 in green color. Therein, C2 discharges the energy to R, then the output voltage of the converter vo reads

vo = vC2 , (4.10)

where vC2 is the voltage of capacitor C2.

Mode 2: t ∈ [t1, t2]

At t1, Q turns off, the mode changes from Mode 1 to Mode 2, as shown in Fig. 4.7(b).

As Q is off, D1, D3, D4, D6 and D8 undertake negative voltage and turn off, yet D2, D5,

D7 and D9 turn on and then form three loops in this mode. Therein, loop 1 is marked with red color, namely, VS-L1-D2-L2-D5-C1, where VS, L1 and L2 discharge energy to C1, namely

VS = vL1 + vL2 + vC1 . Moreover, iL1 and iL2 decrease as the red lines shown in Fig. 4.9(a)(2), and the currents of D2 and D5 are equal to iL1 for the cascaded connectivity, and iC1 increases as shown in Fig. 4.9(a)(4), namely  i = i = i = i ,  D2 D5 L1 L2 iD1 = iD3 = iD4 = 0 , (4.11)  vL1 + vL2 = VS − vC1 .

VS, L1, D2, L2, D5, L3, D7, L4, D9 and C2 form loop 2 marked with red and blue lines, where

VS, L1, L2, L3 and L4 discharge the energy to C2 and R, namely, VS = vL1 +vL2 +vL3 +vL4 +vC2 , and iC2 decreases due to the discharge energy to the load R. Moreover, iL3 and iL4 decrease as the red lines shown in Fig. 4.9(a)(3), and the currents of D7 and D9 are equal to iL3 for the cascaded connectivity, namely

 i = i = i = i ,  D7 D9 L3 L4 iD6 = iD8 = 0 , (4.12)  vL3 + vL4 = VS − (vL1 + vL2 + vC2 ) . 4 A 3-Z-Network Boost Converter 65

4.3.2 Case 2

Case 1 and 2 are both CCMs. Nevertheless, different to Case 1, there are three modes in

Case 2 due to the direction of iC1 , i.e. Modes 1, 2 and 3, whose equivalent circuits are shown in Figs. 4.7(a), 4.7(b) and 4.7(c).

Denote t0 the beginning of one period, t1 the mode transition instant from Mode 1 to

Mode 2, i.e. t1 = t0 + dT , t2 the mode transition instant from Mode 2 to Mode 3, and t3 = T the end of the period. In order to describe the operation process of the converter, key waveforms of the proposed converter in Case 2 are shown in Fig. 4.9(b). Therein, three modes are marked with three different colors in one period. The operation process of the proposed converter in a switch period is analyzed in the following section according to the waveforms in Fig. 4.9(b).

Mode 1: t ∈ [t0, t1]

The process is similar as the descriptions of Mode 1 in Case 1.

Mode 2: t ∈ [t1, t2]

The process is similar to the descriptions of Mode 2 in Case 1 except iC1 . Therein, iC1 decreases as shown in Fig. 4.9(b)(4), which is different from the increase of iC1 in Fig. 4.9(a)(4), because the energy stored in the inductors are not enough to charge the load in this case.

Mode 3: t ∈ [t2, t3]

At t2, iC1 and iC2 decrease to 0, then Mode 3 appears, shown as Fig. 4.7(c), where Q, D1, D3,

D4, D6, D7, D8 and D9 are off, D2 and D5 are on. Thus, there are also two loops marked in different colors. Loop 1 is the same as loop 1 in Mode 2.

In loop 2, iC1 decreases from 0 to negative, which means that not only VS, L1 and L2, but also C1 charge the energy to the following circuit, and they fulfill the same equations as in Case 1.

4.4 DCM

In terms of the inductor currents iL1 , iL2 , iL3 , iL4 and the direction of the capacitor current iC1 , there are four DCMs in the proposed 3-Z-network boost converter, i.e. Case 3: Mode 1 → Mode 2 → Mode 4; Case 4: Mode 1→ Mode 2 → Mode 3 → Mode 5; Case 5: Mode 1 → Mode 2 → Mode 4 → Mode 6; Case 6: Mode 1 → Mode 2 → Mode 3 → Mode 5 → Mode 6, as shown in Fig. 4.10, and the corresponding states of the components are shown in Tab. 4.1. 66 4 A 3-Z-Network Boost Converter

Fig. 4.10: Transitions between modes in DCMs. (a) Case 3. (b) Case 4. (c) Case 5. (d) Case 6

4.4.1 Case 3

Different from Case 1 and 2, Case 3 is a DCM when iL3 and iL4 are discontinuous. There are three modes in this case, i.e. Modes 1, 2 and 4, whose equivalent circuits are shown in Figs. 4.7(a), 4.7(b) and 4.7(d).

Denote t0 the beginning of one period, t1 the mode transition instant from Mode 1 to

Mode 2, i.e. t1 = t0 + dT , t2 the mode transition instant from Mode 2 to Mode 4, and t3 = T the end of the period. The key waveforms of the proposed converter in Case 3 shown in Fig. 4.11(a) can describe the operation process, where three modes are marked in three different colors in one period. The operation process of the proposed converter in a switch period is analyzed in the following according to the waveforms in Fig. 4.11(a).

Mode 1: t ∈ [t0, t1]

The process is similar as that one in Mode 1 in Case 1.

Mode 2: t ∈ [t1, t2]

The process is similar as that one in Mode 2 in Case 1.

Mode 4: t ∈ [t2, t3]

When iL3 and iL4 decrease to 0 and Q keeps off, Mode 4 exists, which is described by iD7 = iD9 = iL3 = iL4 = 0. Then D7 and D9 are off, the waveforms are shown in Fig. 4.11(a). As

Fig. 4.7(c) shows, Q, D1, D3, D4, D6, D7, D8 and D9 are off, but D2 and D5 are on, there are also two loops marked in different colors.

From loop 1 marked in red color, i.e. VS-L1-D2-L2-D5-C1, one has iC1 = iD2 = iD5 = iL1 = iL2 . The source VS, L1 and L2 discharge the energy to C1, so that vC1 increases, namely ( i = i = i = i = i , C1 D2 D5 L1 L2 (4.13) iD1 = iD3 = iD4 = 0 . 4 A 3-Z-Network Boost Converter 67

(a) Case 3 (b) Case 4

Fig. 4.11: Key waveforms of 3-Z-network boost converter in DCMs 68 4 A 3-Z-Network Boost Converter

In loop 2 marked in blue color, C2 discharges energy to R.

4.4.2 Case 4

Case 4 is also a DCM. It corresponds to the case when iL1 and iL2 are discontinuous. There are four modes in this case, i.e. Modes 1, 2, 3, and 5, and their equivalent circuits are shown in Figs. 4.7(a), 4.7(b), 4.7(c) and 4.7(e).

Denote t0 the beginning of one period, t1 the mode transition instant from Mode 1 to

Mode 2, i.e. t1 = t0 + dT , t2 the mode transition instant from Mode 2 to Mode 3, t3 the mode transition instant from Mode 3 to Mode 5, and t4 = T the end of the period. Key waveforms of the proposed converter in Case 4 as shown in Fig. 4.11(b) illustrate the operation process. Therein, four modes are marked in four different colors in one period. The operation process in a switch period is analyzed in the following content according to the waveforms in Fig. 4.11(b).

Mode 1: t ∈ [t0, t1]

The process is same as the one of Mode 1 in Case 2.

Mode 2: t ∈ [t1, t2]

The process is same as the one of Mode 2 in Case 2.

Mode 3: t ∈ [t2, t3]

The process is also similar as that one in Mode 2 in Case 2. However, iL1 and iL2 decrease to be 0 shown in Fig. 4.11(b)(2), which is different from the waveforms of iL1 in Fig. 4.9(b)(2). Thereafter, Mode 5 occurs.

Mode 5: t ∈ [t3, t4]

When iL1 and iL2 decrease to be 0, loop 1 is off. Then, C1, L3 and L4 discharge the energy to

C2 and R. Meanwhile, C2 also discharge the energy to R. Hence, iC2 decrease from positive to negative. Thereafter, C2, C1, L3 and L4 discharge the energy to R.

4.4.3 Case 5

When iL1 and iL2 decrease to 0 in Mode 4 of Case 3, there is only loop 3 left, as shown in Fig. 4.7(f). It is Case 5. There are four modes in this case, i.e. Modes 1, 2, 4, and 6, whose equivalent circuits are shown in Figs. 4.7(a), 4.7(b), 4.7(d), and 4.7(f). 4 A 3-Z-Network Boost Converter 69

Denote t0 the beginning of one period, t1 the mode transition instant from Mode 1 to

Mode 2, i.e. t1 = t0 + DT , t2 the mode transition instant from Mode 2 to Mode 4, t3 the mode transition instant from Mode 4 to Mode 6, and t4 = T the end of the period. Key waveforms of the proposed converter in Case 5 as shown in Fig. 4.11(c) illustrate the operation process. Therein, four modes are marked in four different colors in one period. The operational process in a switch period is analyzed in the following content according to the waveforms in Fig. 4.11(c).

Mode 1: t ∈ [t0, t1]

The process is same as the one of Mode 1 in Case 3.

Mode 2: t ∈ [t1, t2]

The process is same as the one of Mode 2 in Case 3.

Mode 4: t ∈ [t2, t3]

The process is same as the one of Mode 3 in Case 3.

Mode 6: t ∈ [t3, t4]

iL1 and iL2 decrease to 0 and Q keeps off, then Mode 6 occurs, as shown in Fig. 4.7(f). Therein,

C2 discharges the energy to R, and iC2 is constant.

4.4.4 Case 6

When iL3 and iL4 decrease to 0 in Mode 5 of Case 4, then there is only loop 3 left shown in Fig. 4.7(f), which is Case 6. There are five modes in this case, i.e. Mode 1, Mode 2, Mode 3, Mode 5, and Mode 6, whose equivalent circuits are shown in Figs. 4.7(a), 4.7(b), 4.7(c), 4.7(e) and 4.7(f).

Denote t0 the beginning of one period, t1 the mode transition instant from Mode 1 to

Mode 2, i.e. t1 = t0 + dT , t2 the mode transition instant from Mode 2 to Mode 3, t3 the mode transition instant from Mode 3 to Mode 5, t4 the mode transition instant from Mode 5 to

Mode 6, and t5 = T the end of the period. Key waveforms of the proposed converter in Case 6 as shown in Fig. 4.11(d) illustrate the operational process. Therein, five modes are marked in five different colors in one period. The operation process in a switch period is analyzed in the following according to the waveforms in Fig. 4.11(d). 70 4 A 3-Z-Network Boost Converter

Mode 1: t ∈ [t0, t1]

The process is same as the one of Mode 1 in Case 4.

Mode 2: t ∈ [t1, t2]

The process is same as the one of Mode 2 in Case 4.

Mode 3: t ∈ [t2, t3]

The process is same as the one of Mode 3 in Case 4.

Mode 5: t ∈ [t3, t4]

The process is same as the one of Mode 5 in Case 4.

Mode 6: t ∈ [t4, t5]

iC1 , iL3 and iL4 decrease to 0 and Q keeps off, then Mode 6 occurs, which is shown in Fig. 4.7(f).

Therein, C2 discharges the energy to R, and iC2 is constant.

4.5 Parameters Design

Normally, the parameters design of a converter is to determine the rated voltages and rated currents of the components in the circuit.

In order to simplify the analysis, the output voltage Vo is deduced firstly. Because the voltage and current stresses of the components in CCMs are largest, the parameters of the proposed converter in CCM will be chosen as the parameters of the converter.

According to the analyses of Cases 1 and 2, the output voltage Vo is deduced as follows. In terms of the voltage-second balance theory, one has

 dT T R (v + v )dt + R (v + v )dt = 0 ,  0 L1 L2 dT L1 L2 (4.14)  R dT R T 0 (vL3 + vL4 )dt + dT (vL3 + vL4 )dt = 0 . Substituting (4.8)–(4.12) into (4.14) leads to ( 2V dT + (V − V )(1 − d)T = 0 , S S C1 (4.15) 2VC1 dT + (VC1 − Vo)(1 − d)T = 0 . From (4.15), one has 2 1 + d! V = V = V , (4.16) o C2 S 1 − d 4 A 3-Z-Network Boost Converter 71

and 1 + d V = V . (4.17) C1 S 1 − d

According to (4.16), the relationships of duty-cycle d and voltage gain M = Vo/VS in conventional boost converters, quadratic boost converters, and 3-Z-network boost converters are depicted in Fig. 4.12 in different colors, respectively, with a zoom-in for 0 < d < 0.5. It is remarked that the proposed converter can reach a much higher voltage-gain than the quadratic and the conventional ones.

Fig. 4.12: Relationship figure of duty-cycle d and voltage gain M

4.5.1 Output Voltage and Voltage Stress of Electrical Components

In terms of (4.16) and (4.17), the voltages of Li, i = 1, 2,..., 4 can be obtained as follows,

therein, VLi , i = 1, 2,..., 4 refer to the average voltages of Li, i = 1, 2,..., 4 when Q is on and off, respectively.  V , if Q is on,  S VL1 = VL2 = d (4.18)  −V , otherwise,  S 1 − d and   1 + d  V , if Q is on,  S 1 − d VL3 = VL4 = (4.19)  d(1 + d)  −VS , otherwise.  (1 − d)2 72 4 A 3-Z-Network Boost Converter

Table 4.2: Voltage stress of each switching component in CCMs Mode 1 Mode 2 or Mode 3 (1 + d)2 v 0 V Q S (1 − d)2 d v & v 0 V D1 D3 S 1 − d

vD2 VS 0 2d(1 + d) v 0 V D4 S (1 − d)2 1 + d v V 0 D5 S 1 − d d(1 + d) v & v 0 V D6 D8 S (1 − d)2 1 + d v V 0 D7 S 1 − d (1 + d)2 v V 0 D9 S (1 − d)2

In terms of the Kirhhoff’s Voltage Law (KVL), one can obtain the voltage of each component in the circuit as shown in Tab. 4.2.

Assuming a lossless circuit leads to VS · Iin = Vo · Io, where Iin and Io are input and output currents, respectively. In terms of (4.16), one has

(1 + d)2 I = I . (4.20) in o (1 − d)2

Moreover, Iin can also be expressed as

R dT R T 2iL dt + iL dt I = 0 1 dT 1 = (1 + d)I . (4.21) in T L1

Substituting (4.21) into (4.20) results in

1 + d I = I = I . (4.22) L1 L2 o (1 − d)2

Similarly, IL3 and IL4 are expressed as

1 I = I = I . (4.23) L3 L4 o 1 − d 4 A 3-Z-Network Boost Converter 73

In terms of (4.8), (4.9), (4.11), (4.12), and Fig. 4.9(a), the average currents of the diodes are written as   d(1 + d)  I = I = dI = I ,  D1 D3 L1 o (1 − d)2   1 + d   ID2 = ID5 = (1 − d)IL1 = Io ,  1 − d   2d(1 + d)  I = 2dI = I , D4 L1 o (1 − d)2 (4.24)   d  I = I = dI = I ,  D6 D8 L3 o 1 − d   I = I = (1 − d)I = I ,  D7 D9 L3 o   4d  IQ = d(2IL + 2IL ) = Io .  1 3 (1 − d)2 Normally, one derives the voltage of the switches in terms of Tab. 4.2, while determines the corresponding current in terms of (4.24). Then, substituting the related parameters into the corresponding equations in Tab. 4.2 and (4.24), one can obtain their largest values and consider their corresponding safety margin to decide their rated values.

4.5.2 Parameters of Inductors

The parameter design of the inductor is to determine the rated current and inductance, given a permitted fluctuation range xL%(xL is pre-assigned), an output voltage Vo, an output current

Io, and a switching period T .

Determination of the Rated Current

The rated currents of inductors can be obtained from (4.22) and (4.23).

Determination of the Rated Inductance

The ripples of the inductors have also great influence on the stability of the converter; consequently, the inductors must be designed in terms of the permitted ripples. The inductors in the converter can be designed based on the differential equation of inductors

VLdtL L = , (4.25) diL where VL is the voltage of the corresponding inductor as Q is on, dtL = d·T is the time interval of Q as it is on , and diL is the current ripple of the corresponding inductor within the time interval dtL. 74 4 A 3-Z-Network Boost Converter

Denote the permitted error of IL by diL. diL is restrained by the permitted fluctuation range xL% as

diL = xL%IL. (4.26)

Substituting (4.26) into (4.25) leads to the inductance of L,

VLdT L = , (4.27) xL%IL thereafter, substituting the average voltage of inductors in (4.18) and (4.19) for Q on, as well (4.22) and (4.23) into (4.27) leads to

 2  VSdT VSd(1 − d) T  L1 = L2 = = ,  x %I x %I (1 + d) L L1 L o (4.28) V (1 + d)dT V (1 + d)dT  S S  L3 = L4 = = . (1 − d)xL%IL3 xL%Io Hence, the range of the inductance can be determined based on 0 ≤ d ≤ 1, and the maximum is taken as the rated inductance.

4.5.3 Parameters of Capacitors

Similar to the parameter design of the inductor, the design of the capacitor is to determine its rated voltage and capacitance, given a permitted fluctuation range, xC %(xC is pre-assigned), an output voltage Vo, an output current Io, and a switching period T .

Determination of the Rated Voltage

The rated voltages of capacitors are determined in terms of (4.16) and (4.17).

Determination of the Rated Capacitance

The ripples of the capacitors have great influence on the stability of the converter, whose permitted fluctuation range can be used to design the capacitance. Then, the capacitors in converter is designed based on the differential equation of capacitors

IC dtC C = , (4.29) dvC where IC is the current of the corresponding capacitor as Q is on, dtC = dT is time interval of Q as it is on , and dvC is the voltage ripple of the corresponding capacitor within the time interval, dtC . 4 A 3-Z-Network Boost Converter 75

Denote the permitted error of VC by dvC . dvC is determined by the permitted fluctuation

range xC % as

dvC = xC %VC . (4.30)

When Q is on, IC1 = 2IL3 and IC2 = Io, then substituting these two equations and (4.30) into (4.29) leads to  2I dT 2I dT  L3 o  C1 = = ,  x %V x %V (1 + d) C C1 C s (4.31) 2  IodT Io(1 − d) dT  C = = .  2 2 xC %Vo xC %(1 + d) Vs Therein, the range of the capacitance can be calculated according to (4.31), and the maximal one is taken as the rated capacitance.

4.6 Simulations and Experiments

To verify the feasibility and validity of the proposed converter, PSIM software is applied for the simulation.

The pre-assigned parameters are as follows, VS = 12 V, Vo = 108 V, f = 100 kHz and

R = 400 Ω. Further, assume the parameters of the converter as: C1 = 220 µF, C2 = 470 µF,

L1 = L2 = 100 µH, L3 = L4 = 200 µH. Setting up all the parameters and d = 0.5 in the simulation circuit of PSIM, one can obtain the simulation results of Case 1 as shown in Fig. 4.13(a).

Then, inductances of Li, i = 1, 2,..., 4, R, and d are reduced so that the energy stored in the inductors is insufficient for supplying to the load, which results in other operational modes withh the corresponding parameters shown as follows:

Case 2: L1 = L2 = 50 µH, L3 = L4 = 200 µH, R = 200 Ω and d = 0.2;

Case 3: L1 = L2 = 50 µH, L3 = L4 = 25 µH, R = 300 Ω and d = 0.5;

Case 4: L1 = L2 = 25 µH, L3 = L4 = 200 µH, R = 300 Ω and d = 0.2;

Case 5: L1 = L2 = 50 µH, L3 = L4 = 100 µH, R = 300 Ω and d = 0.2; and

Case 6: L1 = L2 = 50 µH, L3 = L4 = 100 µH, R = 300 Ω and d = 0.1; which are shown in Figs. 4.13(b)-4.14(d), respectively. The simulation results are shown in Figs. 4.13 and 4.14. In the six sub-figures for six cases, from top to bottom are the driven voltage vg, the current of the inductors L1(L2), L3(L4) and the capacitance C1, and the output voltage vo, respectively. 76 4 A 3-Z-Network Boost Converter

(a) Case 1 (b) Case 2

Fig. 4.13: Simulation results of the 3-Z-network boost converter in CCMs

A prototype of 3-Z-network boost converter is built as shown in Fig. 4.15, where the converter is composed of L1, L2, C1, C2, switch Q (Type:IRFP250N), D1-D8 (Type:SB5100), and D9 (Type:MBRF20200). In addition, IXDN404 IC is used to drive the switch Q.

Assume the parameters as follows for Case 1: C1 = 220 µF, C2 = 470 µF, L1 = L2 =

100 µH, L3 = L4 = 200 µH, R = 400 Ω, and f = 100 kHz. The waveforms of the converter with an input voltage 12 V are shown in Fig. 4.16, where, from top to bottom, are the Gate-

Source voltage of the switch Q, vGS; the Drain-Source voltage of the switch Q, vDS; the current of L1, iL1 ; the current of L3, iL3 ; and the output voltage, vo. Moreover, the output voltage is about 104.5 V, which is 3.5 V lower than the theoretical value 108 V, and it is reasonable for the diodes voltage drops. Furthermore, the mean currents of iL1 and iL3 are about 1.64 A and 0.53 A, respectively. Hence, the experimental results verify the analytical and simulation results.

Fix the inductors parameters to be L1 = L2 = 45 µH, L3 = L4 = 140 µH. Then, tuning the load and the duty results in different cases, i.e. Cases 2-6 as shown in Figs. 4.17-4.21, respectively; where the corresponding parameters settings are: Case 2: d = 0.2, R = 200 Ω; Case 3: d = 0.5, R = 500 Ω; Case 4: d = 0.1, R = 300 Ω; Case 5: d = 0.25, R = 500 Ω; and Case 6: d = 0.1, R = 400 Ω. It is remarked that the experimental results are consistent with the theoretical and simulation results. 4 A 3-Z-Network Boost Converter 77

(a) Case 3 (b) Case 4

Fig. 4.14: Simulation results of the 3-Z-network Boost converter in DCMs 78 4 A 3-Z-Network Boost Converter

Fig. 4.15: Prototype of the proposed converter

Fig. 4.16: Experimental waveforms of Case 1

4.7 Summary

Based on the proposed impedance network matching mechanism and the methodology for designing converters, two novel boost converters with three active Z-networks are designed in this chapter. Therein, impedance networks are cascaded to realize impedance matching, i.e. the output impedance is matched with negative impedance features for realizing high voltage gains. The proposed 3-Z-network boost converter can realize 350 of voltage gain in theory using only one switch, and it can well fulfill the stringent requirements from industry, especially renewable power systems, to boost low voltage from clean sources like photovoltaic (PV) arrays and fuel cells to high voltages for grid-connected converters. Detailed theoretical analysis, parameters 4 A 3-Z-Network Boost Converter 79

Fig. 4.17: Experimental waveforms of Case 2

Fig. 4.18: Experimental waveforms of Case 3 design, simulations and experiments have been conducted to verify the effectiveness of the proposed converter, which also verify the effectiveness and practice of the proposed impedance network matching mechanism and the methodology for designing converters. 80 4 A 3-Z-Network Boost Converter

Fig. 4.19: Experimental waveforms of Case 4

Fig. 4.20: Experimental waveforms of Case 5 4 A 3-Z-Network Boost Converter 81

Fig. 4.21: Experimental waveforms of Case 6 82 4 A 3-Z-Network Boost Converter 5 A Z-Source Half-Bridge Converter 83

Chapter 5

A Z-Source Half-Bridge Converter

Electroplating is a kind of electrochemistry process, whose fundamental operation principle is shown in Fig. 5.1 and described in the following.

Fig. 5.1: Operation principle of electroplating

The electroplating process is a redox reaction, with fundamental components: two elec- trodes (+ and -), a DC source (Vd) and the solution, as shown in Fig. 5.1. The purpose of the electroplating is to make the metal ions cover on the surface of the negative electrode evenly and smoothly. However, due to the nonuniform of the solution, the DC voltage direction and the current density should be adjusted from time to time, which requires complicated designs according to different products and processes [139, 140]. With the rapid growth of the demand on electroplating products with very different voltages and duties, there are more stringent requirements on the electrochemical power supplies to provide a broad range of outputs, asymmetrical positive and negative voltages, step waves, recurrent pulses, square waves, triangular waves, and saw-tooth waves [141]. In order to realize the aforementioned functions, the output voltages of the electrochem- 84 5 A Z-Source Half-Bridge Converter ical power supply are requested to be variable, including variable positive or negative output voltages, and the variable time ratio between positive and negative voltages. For example, in order to realize the smooth electroplating products, the current densities and directions should be varied according to the requests of electroplating technology [139], [140]. Traditionally, the engineer had to compose several cascaded sub-circuits and use complex control methods to generate an overlapped waveform of multi output voltages [141], [142]. However, the disadvantages lie in that it is hard to control and regulate the output voltages, and the use of cascaded sub-circuits not only increases the cost and size, but also leads to a more complex, bulky structure and instability of the system. Moreover, the engineers should cascade the corresponding converters with their experience for different electroplating products. Therefore, the traditional design method is on case by case basis and dependant on experts’ experience, which cannot fulfil the requirements of modern industrial applications. In terms of the impedance network matching mechanism and the proposed designing methodology, this chapter proposes a novel Z-source half-bridge converter with impedance networks, aiming to the applications in electrochemical systems.

5.1 System Design

DC-AC inverters with abundant output voltages are required in electrochemical systems. How- ever, the traditional DC-AC inverters are limited by the sole output voltage. Thereby, the impedance matching mechanism and the design methodology are utilized to realize output impedance matching.

5.1.1 Disadvantages of A Traditional Half-Bridge Inverter

A DC-AC inverter with abundant output voltages is required in electrochemical systems, therefore, a half-bridge DC-AC inverter is chosen as the main topology in electrochemical systems considering the economic cost, which is shown in Fig 5.2. Therein, assume Cd1 = Cd2 = C. In terms of the input and output impedances analysis methodology in Chapter 3, the short-circuited input impedance and average output impedance of the traditional half-bridge converter are expressed by   1  Zi(jω) = −j , ωC (5.1)  1  Z (jω) = −j . o 2ωC It is seen from (5.1) that the imaginary parts of the input and output impedances are both negative. Therefore, similar to voltage source inverters, it has some disadvantages, i.e. 5 A Z-Source Half-Bridge Converter 85

Fig. 5.2: A conventional half-bridge converter

the shoot-through problems, low output voltage, thus cannot fulﬁll the requirements of electrochemical systems, and the inapplicability to capacitive loads.

5.1.2 Impedance Matching of Traditional Half-Bridge Inverters

In order to overcome the disadvantages listed above and improve the typical Z-source converters, the X-shaped two-port impedance network type in Tab. 3.2 is chosen as the impedance network. Then, embedding the Z-network between the capacitors and the inverter bridge in Fig. 5.2 results in the Z-source impedance-network half-bridge converter as shown in Fig. 5.3.

Fig. 5.3: Z-source half-bridge converter

Therein, an LC Z-network, consisting of capacitors C1 and C2 and inductors L1 and L2, is integrated into a traditional half-bridge converter, consisting of capacitors Cd1 and Cd2, switches

S1 and S2, and diode D, which is used to prevent the current from flowing back to the source. 86 5 A Z-Source Half-Bridge Converter

Moreover, the use of the inductors in Z-network is to avoid strong current in the circuit when the switches are in the shoot-through state [143, 144].

5.1.3 Calculation of Input and Output Impedances

Similarly, one can obtain the transmission parameters matrix of X-shaped two-port impedance network in terms of the equations in Tab. 3.2, substituting the corresponding parameters into the input output impedances equations in Tabs. 3.4 and 3.5. Then, it is easy to prove that they all satisfy the impedance matching conditions, i.e. the short-circuited input impedance is unequal to 0 to realize input impedance matching, while the output impedance can be adapted to match the load impedance for realizing the desired abundant output voltage. The process is omitted here because it is similar as the one of typical Z-source converter.

5.2 Operational Status Analysis

For simplicity, it is assumed that a) all the components are ideal; b) the dead time in the driven pulses is ignored; c) L1=L2 and C1=C2 in the Z-network; d) C1, C2, Cd1 and Cd2 are large enough; and e) the free-wheeling diodes of the switches are ignored in the analysis since the load characteristic of the electrochemical solution is resistance or resistance with a small capacitance.

Denote the duties of the switches S1 and S2 by d1 and d2, respectively. The proposed converter performs differently in two cases, i.e. Case 1: d1 + d2 ≤ 1 and Case 2: d1 + d2 > 1.

5.2.1 Case 1

In this case, S1 and S2 are not on at the same time, which is named as the non-shoot-through state. There are three modes corresponding to the states of the switches.

1. Fig. 5.4(a) shows an equivalent circuit of the ﬁrst mode, for which the S1 is on and S2 is

off, where the current flows out of the source, through the diode, the Z-network, S1, and then back to the source. The arrows indicate the current direction.

2. Fig. 5.4(b) illustrates an equivalent circuit of the second mode, for which S1 and S2 are off, where the current also flows out of the source, through the diode, the Z-network, and back to the source. It is noted that here is no output.

3. Fig. 5.4(c) depicts an equivalent circuit of the third mode, for which S2 is on and S1 is off, where the diode undertakes a negative voltage, and thus, turns off. The current flows

out of the source, through the load, S2, Z-network, and then back to the source. Besides, 5 A Z-Source Half-Bridge Converter 87

the current direction is also indicated. The operation process for this case is similar to the traditional one for half-bridge converters, which is not detailed here.

5.2.2 Case 2

In this case, the behavior of the switches in the circuit leads to three modes within a switch

period T , which correspond to three linear equivalent circuits: Mode 1, when S1 and S2 are

on; Mode 2, when S1 is on and S2 is off; and Mode 3, when S1 is off and S2 is on, as shown in Figs. 5.5(a), 5.5(b) and 5.5(c), respectively.

Denote t0 the initial time of one period, t1 the mode transition instant from Mode 1 to

Mode 2, i.e. t1 = t0 + (d2 + d1 − 1)T , t2 the mode transition instant from Mode 2 to Mode 3, i.e. t2 = t1 + (1 − d2)T , and t3 = T the end of the period. In the steady state of the converter, its operational process in a switch period is analyzed in the following and the output voltage vo will be deduced in each mode.

Mode 1: t ∈ [t0, t1]

As shown in Fig. 5.5(a), in loops 1 and 2, capacitors C1 and C2 discharge the energy to inductors

L1 and L2, thereafter, iL1 and iL2 increase. Thus, L1 and L2 store the energy, and one has ( v = v , L1 C1 (5.2) vL2 = vC2 ,

where iL1 , iL2 , vL1 , vL2 , vC1 and vC2 are the currents of L1, L2, and the voltages of L1, L2, C1

and C2, respectively.

The voltage of diode D is −(vC1 + vC2 − Vd), so D undertakes negative voltage stress, and

thus, turns off. The energy of C2 is delivered to the load RL and Cd2 through the C2-RL-Cd2

loop, so Cd2 charges and Cd1 discharges.

In terms of the C2-RL-Cd2 loop, the output voltage of the converter reads

vo = vC2 − vCd2 , (5.3)

where vCd2 is the voltage of Cd2.

Mode 2: t ∈ [t1, t2]

As shown in Fig. 5.5(b), S1 is on and S2 is off. In loop 1, the source Vd and L1 discharge the

energy to C2, so that vC2 increases. In loop 2, the source Vd and L2 discharge the energy to C1,

thereafter, vC1 increases. Then, the energy of C2 is delivered to the load RL and Cd2 through

the C2-RL-Cd2 loop, so Cd2 charges and Cd1 discharges. From loop 1, one has

vL1 = Vd − vC2 . (5.4)

In terms of the C2-RL-Cd2 loop, the output voltage of the converter is the same as (5.3). 88 5 A Z-Source Half-Bridge Converter

(a) S1 on, S2 off

(b) S1 off, S2 off

Fig. 5.4: Equivalent circuits in Case 1 5 A Z-Source Half-Bridge Converter 89

(a) Mode 1: S1 on, S2 on

(b) Mode 2: S1 on, S2 off

Fig. 5.5: Equivalent circuits in Case 2 90 5 A Z-Source Half-Bridge Converter

Mode 3: t ∈ [t2, t3]

In Fig. 5.5(c), S1 is off and S2 is on. In loop 1, the source Vd and L1 discharge the energy to

C2, thus, vC2 increases. Similarly, in loop 2, Vd and L2 discharge the energy to C1, thus, vC1 increases. The energy of L2 and Cd2 is delivered to RL through the L2-Cd2-RL loop, so Cd2 discharges and Cd1 charges. In terms of loop 1, one has the same equation as (5.4).

In terms of the Vd-D-C1-RL-Cd2 loop, the output of the voltage is

vo = −(vCd2 + vC1 − Vd) . (5.5)

As a result, vo can be deduced as follow.

The voltage-second balance characteristic of L1 leads to

Z T

vL1 dt = 0 . (5.6) 0 Substituting (5.2) and (5.4) into (5.6) leads to

(d2 + d1 − 1)TVC1 + (2 − d2 − d1)T (Vd − VC2 ) = 0 . (5.7)

Assume that L1 = L2, C1 = C2, and C1 and C2 are large enough. Due to the structural symmetry of the Z-network, (5.7) can be rewritten as

2 − d1 − d2 VC1 = VC2 = Vd . (5.8) 3 − 2(d1 + d2)

The ampere-second property of Cd2 implies

Z T

iCd2 dt = 0 , (5.9) 0

where iCd2 is the current of Cd2.

Denote the voltage and current of Cd1 by vCd1 and iCd1 , respectively. It is known from

Fig. 5.5 that vCd1 + vCd2 = Vd. Denote the errors of vCd1 and vCd2 by ∆vCd1 and ∆vCd2 , respectively, and due to Vd being a constant, one has ∆vCd1 = −∆vCd2 , and straightforwardly, du iCd1 = iCd2 in terms of i = C dt . io Moreover, from io = iCd1 + iCd2 , one has iCd2 = 2 , where io is the current of the load; thereafter, (5.9) can be rewritten as

(VC2 − VCd2 ) − (VC2 + VCd2 − Vd) d1T + (1 − d1)T = 0 , (5.10) 2RL 2RL and it follows with that

VCd2 = (2VC2 − Vd)d1 − VC2 + Vd . (5.11) 5 A Z-Source Half-Bridge Converter 91

When switch S1 is on, substituting (5.8) and (5.11) into (5.3) results in the positive output of the converter Vp as

(1 − d1) Vp = vo = VC2 − vCd2 = Vd . (5.12) 3 − 2(d1 + d2)

When the switch S2 is on and S1 is off, substituting (5.8) and (5.11) into (5.5) leads to the negative output of the converter Vn as

d1 Vn = vo = Vd − VC2 − VCd2 = − Vd . (5.13) 3 − 2(d1 + d2)

According to (5.12) and (5.13), the relationships of d1, d2 and Vo/Vd are drawn in Fig. 5.6.

Therein, Vo/Vd increases dramatically as d1+d2 is about 1.5, which is zoomed-in in Fig. 5.7. It is remarked from Fig. 5.6 and Fig. 5.7 that the novel converter can generate abundant output voltages by adjusting d1 and d2.

When Vo/Vd < 1, the converter functions as a Buck converter; otherwise, the converter acts as a boost converter; therefore, it is a buck-boost converter. By controlling the duty of the switches, speciﬁed output voltages can be obtained, including the buck-boost voltages, asymmetric and symmetric, positive and negative peak output voltages, and the time ratio between positive and negative voltages.

Fig. 5.6: Relationship ﬁgure of d1, d2, and Vo/Vd

Additionally, according to (5.12) and (5.13), the values of Vp and Vn are not equal when d1 6= 0.5, but they are equal when d1 = 0.5, which will be explained as below. 92 5 A Z-Source Half-Bridge Converter

Fig. 5.7: Zooming in of Fig. 5.6

Firstly, when d1 = 0.5, the key waveforms of the Z-source half-bridge converter in Case 2 is drawn in Fig. 5.8 according to the analysis for three modes, where QS1 and QS2 stand for the driving voltages of switches (S1 and S2), id the current of diode (D), iL1 and iL2 the currents of inductors (L1 and L2), vC1 , vC2 , vCd1 and vCd2 the voltages of the capacitors (C1, C2, Cd1 and

Cd2), and vo the output voltage, respectively. Additionally, Modes 1, 2, and 3 are distinguished in red, blue, and green colors, respectively. The limited output voltages of the traditional half- bridge converter, Vd/2 and −Vd/2, are marked at the output voltage waveform vo, and it is shown that the output voltages of the proposed converter can exceed the limited one.

Secondly, the corresponding waveforms for d1 6= 0.5 are shown in Fig. 5.9. It is remarked that the output voltage vo in Fig. 5.9 is different from that in Fig. 5.8; and the positive and negative values of vo in Fig. 5.8 are symmetrical, but they are asymmetrical in Fig. 5.9. This means that the proposed converter generates many kinds of output voltages, fulfilling the requirements of the electrochemical power supply, such as, various positive or negative output voltages, and the regulated duration at negative or positive output voltage, which has prominent advantages over traditional methods by using complicated control methods and multiple cascaded sub-circuits.

Moreover, the efficiency of the converter η is given by 5 A Z-Source Half-Bridge Converter 93

Fig. 5.8: Key waveforms of the Z-source Half-bridge converter in Case 2 when d1 = 0.5 and d2 = 0.7

Pout η = Pin 2 2 vp vn d1 + (1 − d1) = R R VdIav (5.14) 2 2 d1v + (1 − d1)v = p n RVdIav d1(1 − d1)Vd = 2 , (3 − 2(d1 + d2)) RIav

2 2 d1v + (1 − d1)v where P = p n, P = V I , I are the output power, the input power, and out R in d av av the average input current, respectively. Here, the conduction and switching loss is taken into

account, and indicated in Pin − Pout. 94 5 A Z-Source Half-Bridge Converter

Fig. 5.9: Waveforms of the Z-source half-bridge converter in Case 2 when d1 = 0.7 and d2 = 0.5

5.3 Midpoint Balance of Input Capacitors

The stability of the midpoint voltage in the converter plays a key role for the system’s stability. The midpoint voltages of the input capacitors in the conventional converter and the proposed converter will be analyzed and compared in this section.

5.3.1 Midpoint Voltage in Conventional Half-Bridge Converters

In conventional half-bridge converters, there are always some problems caused by the midpoint unbalance of the input capacitor voltage. In this subsection, the midpoint voltage in conventional half-bridge converters will be analyzed and the fluctuation equation of the midpoint voltage will be derived. Fig. 5.10 shows the equivalent circuits of that in Fig. 5.2.

In a switching period, S1 is on and S2 is off as t ∈ [0, d1T ], while S1 is off and S2 is on as 5 A Z-Source Half-Bridge Converter 95

(a) Mode 1: S1 on, S2 off (b) Mode 2: S1 off, S2 on

Fig. 5.10: Equivalent circuits of the conventional half-bridge converter

t ∈ [d1T,T ].

Denote the initial voltage of Cd2 by VCd20. In terms of the Kirhhoff’s Voltage Law (KVL), vCd2 can be derived in frequency domain as

Vd Vd − VCd20 vC (s) = − . (5.15) d2 s 1 s + Cd2R Employing Laplace Inverse Transformation to (5.15) results in

− t Cd2R vCd2 (t) = Vd − (Vd − VCd20)e . (5.16)

Denote the maximal and the minimal voltages of vCd2 by vCd2max and vCd2min, respectively, and the maximal fluctuation of vCd2 by ∆V . Following (5.16), one has

∆V =vCd2max − vCd2min − d1T Cd2R =(Vd − VCd20)(1 − e ) . (5.17)

In the high-frequency power supply, T is normally very small, and the input capacitance

Cd2 and load are quite large in electrochemical application, which implies that d1T is much smaller than Cd2R, then (5.17) can be approximated by

d1t ∆V ≈ (Vd − VCd20) . (5.18) Cd2R

5.3.2 Midpoint Voltage in Z-Source Half-Bridge Converters

It is described in [145] that the input part can be regarded as a DC voltage source or a DC current source due to the Z-network. Similarly, the output part of the Z-network can be treated as a DC current source. Hence, the equivalent circuits are derived as follows. 96 5 A Z-Source Half-Bridge Converter

(a) Mode 1: S1 on, S2 off (b) Mode 2: S1 off, S2 on

Fig. 5.11: Equivalent circuits of the Z-source half-bridge converter

The differential equation of the circuit shown in Fig. 5.11(a) can be described as

dvC C d2 = I , (5.19) d2 dt p where Ip is the current of the constant current source. Integrating both sides of (5.19) leads to

Z Ip vCd2 (t) = VCd20 + dt . (5.20) Cd2

Denote the maximal fluctuation of vCd2 as shown in Fig. 5.11 by ∆VZ. Then, from (5.20), one has

∆VZ =vCd2max − vCd2min d T Z 1 Ip Ip = dt = d1T . (5.21) 0 Cd2 Cd2

Ip can be derived by Kirhhoff’s Current Law (KCL) as

Vd − VC 0 − VI I = d2 p , (5.22) p R where VIp is the voltage of the constant current source. Substituting (5.22) into (5.21) leads to

Vd − VCd20 − VIp ∆VZ = d1T . (5.23) Cd2R 5 A Z-Source Half-Bridge Converter 97

Therein, the ratio of ∆VZ to ∆V can be derived from (5.18) and (5.23) as

∆VZ Vd − VC 0 − VI = d2 p × 100% . (5.24) ∆V Vd − VCd20

∆VZ It is obvious that ∆VZ < ∆V , if VIp is positive; and the smaller ∆V is, the smaller the ∆VZ ripple in the proposed converter, consequently, the more stable the proposed converter is. ∆V will become very small, or even zero, if VIp is very close to the value of Vd − VCd20 , and VIp can be designed by the parameters of the Z-network. It is remarked that the proposed converter is more stable than the traditional one with regard to the problem of the input capacitor stability.

5.4 Parameters Design

The parameters of the Z-network are designed in this section, including capacitor and inductor parameters design.

5.4.1 Parameters of Capacitors

Normally, the design of the capacitor is to determine the rated voltage and capacitance with a permitted fluctuation range, xC %(xC is pre-assigned), a given output voltage Vo, a given output current Io, and a given switching period T . From (5.8), (5.12), and (5.13), one has

2 − d1 − d2 vC2 = Vo, when (S1) = (on), (5.25) d1 and 2 − d1 − d2 vC2 = Vo, when (S1,S2= (off, on)). (5.26) 1 − d1 In terms of Kirchhoﬀ’s current law (short for KCL), the equations of the connected nodes of L2-C1-S2 in Fig. 5.5(a), L1-C2-S1 in Fig. 5.5(b), and L2-C1-S2 in Fig. 5.5(c) can be derived as   iL2 = iC1 + io, when (S1,S2) = (on, on),   iL1 = iC2 + io, when (S1,S2) = (on, off), (5.27)    iL2 = io − iC1 , when (S1,S2) = (off, on).

Denote the root-mean-square (rms) currents of L2 and C2 by IL2 and IC2 , respectively. Then, from (5.27), one has

Io I ≈ I = . (5.28) C2 L2 2 98 5 A Z-Source Half-Bridge Converter

Determination of the Rated Voltage

The range of vC2 is determined by (5.25) and (5.26). Thereby, the rated voltage of C2 can be determined by the maximal VC2M. Considering the safety margin, the rated voltage of C2 is normally set between 1.5VC2M and 2VC2M.

Determination of the Rated Capacitance

The ripples of the capacitors have great influence on the stability of the converter, whose permitted fluctuation range can be used to design the capacitance. Then, the capacitors in Z-network can be designed according to the differential equation of capacitors

iC2 dt C2 = . (5.29) dvC2 The high harmonic frequency of the capacitance is nearly equal to the switching frequency of the converter, as shown in Fig. 5.8, namely

dt ≈ (d1 + d2 − 1)T. (5.30)

Denote the permitted error of VC2M by dvC2 , according to the permitted fluctuation range xC %, dvC2 is expressed as

dvC2 = xC %VC2M . (5.31) Substituting (5.28), (5.30) and (5.31) into (5.29) leads to

Io(d1 + d2 − 1)T C2 = . (5.32) 2xC %VC2M Therein, the range of the capacitance can be calculated, and the maximal is taken as the rated capacitance.

5.4.2 Parameters of Inductors

Similar to the parameter design of the capacitor, the parameter design of the inductor is to determine the rated current and inductance with a permitted fluctuation range xL%(xL is pre- assigned), a given output voltage Vo, a given output current Io, and a given switching period T .

Determination of the Rated Current

IL2 can be determined by (5.28). Considering the safety margin, the rated current of L2 is normally taken as 2IL2 . 5 A Z-Source Half-Bridge Converter 99

Determination of the Rated Inductance

The ripples of the inductors also have great influence on the stability of the converter; therefore, the inductance can be designed in terms of the permitted ripples. The inductors in the Z-network can be designed according to the differential equation of inductances

vL2 dtL L2 = . (5.33) diL2

In the L1-C2-L2-C1 loop, the KVL equation can be expressed as vL2 + vC1 = vL1 + vC2 . In

the Z-network, the rms voltages of C1, C2, L1, and L2 are denoted by VC1 , VC2 , VL1 and VL2 ,

respectively; and one has vC1 ≈ VC2 and VL2 ≈ VL1 . Thereby, the maximal of vL2 is derived as

VL2M ≈ VC2M. (5.34)

The high harmonic frequency of the inductor is nearly equal to the switching frequency of

the converter, as shown in Fig. 5.8, so the time interval dtL in (5.33) can be obtained as

dtL ≈ (d1 + d2 − 1)T. (5.35)

Denote the permitted error of IL2 by diL2 . According to the permitted fluctuation range

xL%, diL2 is expressed as

diL2 = xL%IL2 . (5.36) Substituting (5.25), (5.26), (5.28), (5.34), (5.35) and (5.36) into (5.33) leads to the induc-

tance of L2 as

2VC2M(d1 + d2 − 1)T L2 = . (5.37) xL%Io

5.5 Simulations and Experiments

To verify the feasibility and validity of the proposed converter, Simulink software is applied for the simulation of the converter.

The pre-assigned parameters are as follows, xC % = 1%, xL% = 10%, Vd = 48 V, Vo =

100 V, Io = 10 A, and T = 20 µs. According to the design, the parameters of the converter can be calculated: C1 = C2 = 482.5 µF, L1 = L2 = 105.5 µH. However, in practice, the parameters can be chosen as follows: C1 = C2 = 470 µF, L1 = L2 = 100 µH. The simulation results are shown in Figs. 5.12 and 5.13, which are consistent to theoretical analyses shown in Figs. 5.8 and 5.9. A prototype of the Z-network converter is built as shown in Fig. 5.14, and the parameters are chosen as follow: Cd1 = Cd2 = 470 µF, C1 = C2 = 470 µF, L1 = L2 = 100 µH, R = 100 Ω, and T = 20 µs. 100 5 A Z-Source Half-Bridge Converter

Fig. 5.12: Simulation waveforms when d1 = 0.5 and d2 = 0.7

The main circuit is in the left side in Fig. 5.14, composed of L1, L2, C1, C2, switches (Type:IRFP450) and the resistive load R; while the driving circuit is in the right side, composed of two SG3525 ICs being applied to generated two synchronous overlapped driving signals, and TLP250 ICs being used to drive the switches, whose working frequency and duties can be adapted by the adjustable resistors.

The waveforms of the converter at d1 = 0.5 and d2 = 0.7 with an input voltage 40 V are shown in Fig. 5.15. Therein, the upper waveform refers to VGS(Gate-Drain voltage) of the switch S1; the middle one is VSD(Source-Drain voltage) of the switch S2, which is not, but can be synchronized to the driving waveform of S2; the lower one is the output voltage of the load R, whose negative and positive output voltages are symmetric, and they are all about 50 V. This verifies the analytical and simulation results.

Fig. 5.16 depicts the experimental waveforms of the converter when d1 = 0.7 and d2 = 0.5. Therein, the negative and positive output voltages are asymmetric, the positive one is about

20 V, which is nearly equal to Vd/2, and the width is d1T ; while the negative one is 40 V, which is much larger than Vd/2. The experimental results are also consistent with the simulation results. In order to verify that the proposed converter has a balanced midpoint voltage, the experimental result is shown in Fig. 5.17. Therein, the ripples of vCd2 in the proposed converter have 5 A Z-Source Half-Bridge Converter 101

Fig. 5.13: Simulation waveforms when d1 = 0.7 and d2 = 0.5

Fig. 5.14: Prototype of the proposed converter maximal peak-to-peak values just about 98.4 mV.

Substituting Pout = 200·N W(N = 1, 2, ...10) into (5.14), one can obtain the corresponding efficiencies in theory, which are compared with the corresponding experimental efficiencies in the Fig. 5.18. It is found that the experimental results are nearly consistent with the theoretical results, moreover, the efficiency of the proposed converter reaches the high efficiency when the power is 80% rated power. 102 5 A Z-Source Half-Bridge Converter

Fig. 5.15: Experimental waveforms in shoot-through case (d1 = 0.5, d2 = 0.7)

Fig. 5.16: Experimental waveforms in shoot-through case (d1 = 0.7, d2 = 0.5)

Fig. 5.17: The ripple experiment waveform of vCd2 in the proposed converter

5.6 Summary

Based on the impedance networks matching mechanism and the proposed methodology for designing converters, a novel Z-source half-bridge converter has been proposed and analyzed in this chapter. Similar to the design of the typical Z-source converter, a Z-network is inserted into the traditional half-bridge converter to increase the input impedance, balance the mid- voltage of the input capacitors, and satisfy the stringent requirements of the electrochemistry power supply. Moreover, the proposed converter is more stable and its eﬃciency is higher compared to other electrochemistry power supplies. The detailed operational status analysis, 5 A Z-Source Half-Bridge Converter 103

Fig. 5.18: Comparison between the experimental and the estimation efficiency parameters design, simulations, and experiments are conducted to validate the the effectiveness and practical applications of the proposed mechanism and methodology. 104 5 A Z-Source Half-Bridge Converter 6 A Dual-Output Z-Source Half-Bridge Converter 105

Chapter 6

A Dual-Output Z-Source Half-Bridge Converter

Under the pressure of the energy crisis and environmental pollution in the last decades, govern- ments have been making the greatest eﬀorts to seek new solutions[146, 147], one of which is to develop hybrid electric vehicles (HEV) [148], whose diagram is shown in Fig. 6.1, including a battery Vd (Batt.), a bidirectional DC-DC boost converter, DC buses (negative and positive), two DC-AC inverters, a generator (Gen.), an electric motor (Mot.), and an internal combustion engine (ICE). Therein, the DC-DC boost converter is used to increase the voltage of the battery to realize the DC bus voltage, while the DC bus offers or absorbs energy to/from two inverters. The interface between the DC bus and the electric motor is one of the inverters. The inverter operates as a DC-AC converter when the electric motor consumes power to drive the vehicle, while operates as an AC-DC converter in the deceleration or braking to save the energy. The other inverter is to connect the DC bus and the electric generator, and works as a DC-AC converter to start the ICE and be an AC-DC converter to absorb energy [98].

To reduce the number of switches, a dual-output converter with nine switches is proposed in [98]. Therein, two inverters share three common switches, resulting in the reduction of three switches. However, there are still the limited voltage and shoot-through problems. In order to solve these problems, the DC-DC boost converter in Fig. 6.1 is replaced with a Z-network in [98], in which 5 switches are reduced compared to the one in Fig. 6.1. However, there are still 9 switches in it.

Further to reduce the number of switches, a dual-output Z-source half-bridge converter with only three switches for hybrid electric vehicle systems is proposed [149, 150]. along with the impedance networks matching mechanism and the designing methodology in this chapter. 106 6 A Dual-Output Z-Source Half-Bridge Converter

Fig. 6.1: Structure of conventional hybrid vehicle systems

6.1 System Design

As aforementioned above, electric vehicles required power supplies systems with dual-output DC-AC converters because there are two energy systems. Moreover, speciﬁc features of few switches, being immunity to the shoot-through problems, and high output voltage gains are eagerly required. Therefore, in terms of the impedance network matching mechanism and the designing methodology, impedance matching mechanism is used to analyze the disadvantages of traditional one and improve it. Similar to the topology in Chapter 5, half-bridge DC-AC converters are chosen as the topology because the main purpose of this chapter is to reduce the number of switches and there are only two switches in it. Since paralleled connectivity can reduce the impedance, paralleled connectivity is used to reduce the output impedance to realize output impedance matching. Moreover, in order to realize two output voltage, two half-bridge DC-AC converters are paralleled. In order to realize features of few switches and inspired from the nine switches converter, one capacitor and one switches are shared by two converters, which results in the novel converter as shown in Fig. 6.2. Further in order to realize features of being immunity to the shoot-through problems and high output voltage gains, an X-shaped two-port impedance network is embedded into the traditional half-bridge converter in terms of Tab. 3.3, which ﬁnally results in the novel converter as shown in Fig. 6.3. 6 A Dual-Output Z-Source Half-Bridge Converter 107

Fig. 6.2: A dual-output half-bridge converter with three switches

Fig. 6.3: A dual-output Z-source half-bridge converter with three switches

The proposed converter is depicted in Fig. 6.3, in which two outputs share the same

capacitor Cd2 and the same switch S2. Then, the proposed converter own the same features

as the features of two Z-source half-bridge converter in Fig. 5.3. Therein, capacitors Cd1 , Cd2 , switches S1, S2 offer a loop for the load Gen, while capacitors Cd2 , Cd3 , switches S2, S3 form another loop for the load Mot, and these two loops share the same Z-network, consisting of

capacitors C1 and C2 and inductors L1 and L2. Due to the Z-network, the proposed converter well solve the shoot-through and limited voltage problems [149, 150]. The unique feature of the proposed converter is that there are only three switches, which well reduces the economic cost and increase the efficiency of the electric vehicle.

6.2 Control Strategy

Corresponding to the on and off states of three switches, there are 8 kinds of modes, which result in different output results in the proposed converter. As shown in Fig. 6.4, the time 108 6 A Dual-Output Z-Source Half-Bridge Converter sequence indicates the driving waveforms of the three switches. According to Fig. 6.4, one can obtain different control strategy by adjusting the duties and phase-shift of three switches.

Fig. 6.4: Waveforms of the three switches

Therein, d1, d2 and d3 are the duties of switches S1, S2 and S3, respectively. Moreover,

∆d12, ∆d23 and ∆d31 are the phase shift ratios from S1 to S2, S2 to S3, and S3 to S1, respectively.

Denote three binary coded digits B1, B2 and B3 as the states of S1, S2 and S3. Bi = 1(i = 1, 2, 3) means that the switch Si is on and Bi = 0 implies that the switch Si is off. Hence, B1B2B3 corresponds to 8 modes, i.e. 000, 001, 010, 011, 100, 101, 110, and 111. One mode is taken as example to be introduced in detail in this chapter. 1 For simplicity, assume that ∆d12 = ∆d23 = ∆d31 = ∆d = 3 , and d1 = d2 = d3 = dc. In order to avoid the saturations of inductors, the time interval of shoot-through states should be smaller than that of non-shoot-through states in the proposed converter, then one can obtain 5 dc − 2∆d < 1 − dc from Fig. 6.4, namely, 0 < dc < 6 . Therefore, there are five cases due to the conducted switches in each operational mode:

1 Case 1: one or zero conducted switch, namely, 0 < dc < 3 ;

1 Case 2: one conducted switch, namely, dc = 3 ;

1 2 Case 3: two or one conducted switches, namely, 3 < dc < 3 ;

2 Case 4: two conducted switches, namely, dc = 3 ; and

2 5 Case 5: two or three conducted switches, namely, 3 < dc < 6 , which are demonstrated in Fig. 6.5.

It is thus clear that Case 5 contains other four cases as special cases. Therefore, Case 5 is taken as an example to be analyzed. 6 A Dual-Output Z-Source Half-Bridge Converter 109

(a) Case 1 (b) Case 2

Fig. 6.5: Modes transition diagram in five different cases

6.3 Operational Modes Analysis

For simplicity, it is assumed that a) all the components are ideal; b) the dead time in the driven pulses is ignored; c) L1=L2 and C1=C2 in the Z-network; and d) C1, C2, Cd1 , Cd2 and Cd3 are large enough. Then, assume the voltages of Cd1 , Cd2 , Cd3 , C1, and C2 to be constant in steady states, denoted by V , V , V , V and V , respectively. Cd1 Cd2 Cd3 C1 C2 For simplicity, Z1 and Z2 are used to represent loads Gen. and Mot. in Fig. 6.3, respectively. There are four switching modes in Case 5 due to the behavior of the switches, which correspond to four equivalent circuits as shown in Figs. 6.6(a), 6.6(b), 6.6(c), and 6.6(d), respectively. Therein, the corresponding operational modes are: Mode 1, S1, S2 and S3 are on,

D is off (B1B2B3 = 111); Mode 2, S1, D and S3 are on, S2 is off (B1B2B3 = 101); Mode 3, S1,

S2 and D are on, S3 is off (B1B2B3 = 110); and Mode 4, when D, S2 and S3 are on, S1 is off

(B1B2B3 = 011).

Denote t0 the initial time of one period, t1 the mode transition instant from Mode 1 to

Mode 2, i.e. t1 = t0 +(dc +∆d−1)T ; t2 the mode transition instant from Mode 2 to Mode 1, i.e. t2 = t0+∆dT ; t3 the mode transition instant from Mode 1 to Mode 3, i.e. t3 = t2+(dc+∆d−1)T ; t4 the mode transition instant from Mode 3 to Mode 1, i.e. t4 = t2 +∆dT ; t5 the mode transition instant from Mode 1 to Mode 4, i.e. t5 = t4 + (dc + ∆d − 1)T ; and t6 = T the end of the period. 110 6 A Dual-Output Z-Source Half-Bridge Converter

(a) Mode 1 (b) Mode 2

Fig. 6.6: Equivalent circuits in Case 5. 6 A Dual-Output Z-Source Half-Bridge Converter 111

In the steady state of the converter, its operational process in a switch period is analyzed in the following and the key waveforms of Case 5 are shown in Fig. 6.7, which depicts the driven voltages of switches S1, S2, and S3, namely, QS1, QS2 and QS3; the voltage of diode D, namely vD; the currents of inductors L1 and L2, namely, iL1 and iL2 ; and the output voltages vo1 and vo2 , accordingly.

Fig. 6.7: Key waveforms of the dual-output Z-source half-bridge converter in Case 5: Shoot- through case

In the following, the output voltages are to be derived in each mode.

Mode 1 (t ∈ ([t0, t1] ∪ [t2, t3] ∪ [t4, t5]))

As shown in Fig. 6.6(a), the diode D is off and three switches are on. Then, the shoot-through state occurs. Therein, the source and Z-network transfer energy to Z1 and Z2. In detail, the source Vd and capacitor C2 transfer energy to Z1 via Vd-Cd1 -Z1-S1-C2 loop, then the voltage of Z is v = V + V − V . Moreover, C and C discharge energy to Z through C -C - 1 o1 Cd1 C2 d d3 2 2 d3 2 S -S -Z loop, namely, v = V − V . Due to the shoot-through state, the voltages of L 1 2 2 o2 C2 Cd3 1 and L2 are equal to the voltages of capacitors C1 and C2, namely vL1 = vL2 = VC1 = VC2 . This mode lasts so long as (dc + ∆d − 1)T . Therefore, one can obtain the output voltages as ( vo = VC + VC − Vd , 1 d1 2 (6.1) v = V − V . o2 C2 Cd3 112 6 A Dual-Output Z-Source Half-Bridge Converter

Mode 2 (t ∈ [t1, t2])

As shown in Fig. 6.6(b), D, S1 and S3 are on, S2 is off. Therein, Vd transfers energy to Z- network through D, hence, one can obtain that vL1 = Vd − VC2 . In the Vd-Cd1 -Z1-S1-C2 loop, V and C discharge energy to Z , namely, v = V + V − V . Moreover, Z obtains energy d 2 1 o1 Cd1 C2 d 2 from the V -D-C -S -Z -C loop, then, v = V − V − V = V − V − V . This mode d 1 3 2 d3 o2 d C1 Cd3 d C2 Cd3 lasts (1 − dc)T . Then, one can obtain the output voltages as ( vo = VC + VC − Vd , 1 d1 2 (6.2) v = V − V − V . o2 d C2 Cd3

Mode 3 (t ∈ [t3, t4])

In Fig. 6.6(c), D, S1 and S2 are on, S3 is off. Vd transfers energy to Z-network through D, then one can obtain that vL1 = Vd − VC2 . Z1 obtains energy as Modes 1 and 2. Meanwhile,

Z2 receives energy according to C2-S1-S2-Z2-Cd3 loop. This mode lasts (1 − dc)T . Hence, the output voltages are given by ( vo = VC + VC − Vd , 1 d1 2 (6.3) v = V − V . o2 C2 Cd3

Mode 4 (t ∈ [t5, t6])

As shown in Fig. 6.6(d), D, S2 and S3 are on, S1 is off. Therein, the source Vd charges the

Z-network through D, then one can obtain that vL1 = Vd − VC2 . Z1 obtains energy in terms of the C -D-C -S -S -Z loop, namely, v = V − V = V − V . Z gets energy from d1 1 3 2 1 o1 Cd1 C1 Cd1 C2 2 the V -D-C -S -Z -C loop, then v = V − V − V = V − V − V . This mode lasts d 1 3 2 d3 o2 d C1 Cd3 d C2 Cd3 (1 − dc)T . Therefore, one can obtain the output voltages as ( vo = VC − VC , 1 d1 2 (6.4) v = V − V − V . o2 d C2 Cd3 According to the analysis above, it concludes that ( V + V − V , for t ∈ [t , t ] , Cd1 C2 d 0 5 vo = (6.5) 1 V − V , for t ∈ [t , t ] , Cd1 C2 5 6 ( V − V , for t ∈ ([t , t ] S[t , t ]) , C2 Cd3 0 1 2 5 vo = (6.6) 2 V − V − V , for t ∈ ([t , t ] S[t , t ]) , d C2 Cd3 1 2 5 6 and ( V , for t ∈ ([t , t ] S[t , t ] S[t , t ]) , v = v = C2 0 1 2 3 4 5 (6.7) L1 L2 S S Vd − VC2 , for t ∈ ([t1, t2] [t3, t4] [t5, t6]) . 6 A Dual-Output Z-Source Half-Bridge Converter 113

6.4 Deduction of Output Voltages

R T Based on the voltage-second characteristic of L1, namely, 0 vL1 dt = 0, vL1 can be derived as

R T 0 vL1 dt

= 3 R (dc+∆d−1)T v dt + R ∆dT v dt 0 L1 (dc+∆d−1)T L1 (6.8) = 3 R (dc+∆d−1)T V dt + R ∆dT (V − V )dt 0 C2 (dc+∆d−1)T d C2

= 0 .

Then, one obtains VC1 and VC2 as

1 − dc VC1 = VC2 = Vd . (6.9) 2 − (∆d + 2dc) Substituting (6.9) into (6.7) leads to

 1 − dc  V , for t ∈ ([t , t ] S[t , t ] S[t , t ]) ,  d 0 1 2 3 4 5  2 − (∆d + 2dc) vL1 = vL2 = (6.10)   1 − (∆d + dc) S S  Vd, for t ∈ ([t1, t2] [t3, t4] [t5, t6]) . 2 − (∆d + 2dc)

The ampere-second property of Cd1 , Cd2 and Cd3 implies

 R T  0 iCd dt = 0 ,  2   R T R T R T (6.11) 0 iCd dt = 0 (iCd − io1 )dt = 0 io1 dt = 0 ,  1 2    R T i dt = R T (i + i )dt = R T i dt = 0 , 0 Cd3 0 Cd2 o2 0 o2 where i , i ,i , i and i are the currents of C , C , C , Z and Z , respectively. Cd1 Cd2 Cd3 o1 o2 d1 d2 d3 1 2 Then, one obtains  vo  R T i dt = R T 1 dt = 0 ,  0 o1 0  Z1 (6.12)   vo2  R T R T  0 io2 dt = 0 dt = 0 . Z2 Substituting (6.5) and (6.6) into (6.12) leads to 114 6 A Dual-Output Z-Source Half-Bridge Converter

 VC + VC − Vd VC − VC  d1 2 d1 2  dcT + (1 − dc)T = 0 ,  Z1 Z1 (6.13)   VC − VC Vd − VC − VC  2 d3 2 d3  (2dc − 1)T + (2 − 2dc)T = 0 . Z2 Z2 From (6.13), one obtains V and V as Cd1 Cd3

  1 − dc − dc∆d  VC = VC (1 − 2dc) + Vddc = Vd ,  d1 2  2 − (∆d + 2dc) (6.14)   (1 − dc)(1 − 2∆d)  V = V (4d − 3) + V (2 − 2d ) = V .  Cd3 C2 c d c d 2 − (∆d + 2dc) Substituting (6.14) and (6.9) into (6.5) and (6.6) leads to   ∆d − ∆ddc  Vd, for t ∈ [t0, t5] ,  2 − (∆d + 2dc) vo = (6.15) 1 − ∆dd  c  Vd, for t ∈ [t5, t6] , 2 − (∆d + 2dc) and   2∆d(1 − dc) S  Vd, for t ∈ ([t0, t1] [t2, t5]) ,  2 − (∆d + 2dc) vo = (6.16) 2 ∆d(1 − 2d )  c S  Vd, for t ∈ ([t1, t2] [t5, t6]) . 2 − (∆d + 2dc) Assume ∆d = 1/3, then in terms of (6.15) and (6.16), one can obtain two output voltage gain M1 and M2 as  1 − d  c  , for t ∈ [t0, t5] , 5 − 6dc M1 = (6.17) − d  c  , for t ∈ [t5, t6] , 5 − 6dc and  2 − 2d  c S  , for t ∈ ([t0, t1] [t2, t5]) , 5 − 6dc vo = (6.18) 2 1 − 2d  c S  , for t ∈ ([t1, t2] [t5, t6]) . 5 − 6dc In order to make the proposed converter operate in Case 5, there is a constraint condition in (6.17) and (6.18), i.e. 2/3 < dc < 5/6. Then, one can obtain the relationships between them, which are shown in Fig. 6.8, and the zoomed-in figure is shown in Fig. 6.9. 6 A Dual-Output Z-Source Half-Bridge Converter 115

Fig. 6.8: Curves of dual output voltage gains

Fig. 6.9: Zooming in of Fig. 6.8

6.5 Parameters Design

6.5.1 Parameters of Capacitors

Normally, the design of the capacitor is to determine the rated voltage and capacitance with a permitted fluctuation range, xC %(xC is pre-assigned), given output voltages Vo1 and Vo2 , output currents Io1 and Io2 , and the switching period T . 116 6 A Dual-Output Z-Source Half-Bridge Converter

Determination of the Rated Voltage

From (6.9), the rated voltage of C2 can be determined by the maximal VC2 , namely, VC2M.

Determination of the Rated Capacitance

The ripples of the capacitors have great influence on the stability of the converter, whose permitted fluctuation range can be used to determine the capacitance. Then, the capacitors in Z-network can be determined according to the differential equation of capacitors

iC2 dt C2 = . (6.19) dvC2 The high harmonic frequency of the capacitance is nearly equal to triple to the switching frequency of the converter, namely T dt ≈ . (6.20) 3

Denote the permitted error of VC2M by dvC2 , according to the permitted fluctuation range xC %, dvC2 is expressed as

dvC2 = xC %VC2M . (6.21)

Substituting (6.20) and (6.21) into (6.19) leads to

T I o2 3 C2 = . (6.22) xC %VC2M

Therein, the range of the capacitance can be calculated, and the maximal one takes the rated capacitance.

6.5.2 Parameters of Inductors

Similarly, the parameter determination of the inductor is to determine the rated current and capacitance with a permitted fluctuation range xL%(xL is pre-assigned), given output voltages

Vo1 and Vo2 , output currents Io1 and Io2 , and the switching period T .

Determination of the Rated Current

In fact, the rms current of L2 is approximated to be Io2 . Considering the safety margin, the rated current of L2 is normally taken as 2Io2 . 6 A Dual-Output Z-Source Half-Bridge Converter 117

Determination of the Rated Inductance

The ripples of the inductors also have great influence on the stability of the converter; therefore, the inductance can be determined in terms of the permitted ripples. The inductances in the Z-network can be determined according to the differential equation of inductances as

vL2 dtL L2 = . (6.23) diL2

In Z-networks, one can obtain the maximal value of vL2 from (6.10), namely, VL2M. The high harmonic frequency of the inductance is nearly equal to triple to the switching

frequency of the converter, so the time interval dtL in (6.23) can be obtained as T dt ≈ . (6.24) L 3

Denote the permitted error of IL2 by diL2 . According to the permitted fluctuation range

xL%, diL2 is expressed as

diL2 = xL%IL2 . (6.25)

Then, one has the inductance of L2 as T V L2M 3 L2 = . (6.26) xL%Io2

6.6 Simulations and Experiments

To verify the feasibility and validity of the proposed converter, PSIM software is applied for the simulation of the converter. The pre-assigned parameters are set as follows: xC % = 1%,

xL% = 10%, Vd = 30 V, Cd1 = Cd2 = Cd3 = 470 µF, Z1 = Z2 = 50 Ω, ∆d = 1/3, dc = 0.75 and T = 100 µs.

According to the settings, the parameters of the converter can be calculated: C1 = C2 =

182.5 µF, L1 = L2 = 105.5 µH, based on which the parameters can be practically selected as

follows: C1 = C2 = 220 µF, L1 = L2 = 100 µH. The simulation results are shown in Fig. 6.10, which depicts the driven voltages of switches

S1, S2, and S3; the voltage of diode D; the currents of inductors L1 and L2; and the output

voltages vo1 and vo2 , accordingly. Moreover, the output voltages are given by ( 15 V, for t ∈ [t0, t5] , vo1 = (6.27) −45 V, for t ∈ [t5, t6] , and ( 30 V, for t ∈ ([t , t ] S[t , t ]) , v = 0 1 2 5 (6.28) o2 S −30 V, for t ∈ ([t1, t2] [t5, t6]) . 118 6 A Dual-Output Z-Source Half-Bridge Converter

1 Fig. 6.10: Simulation waveforms of Case 5 when ∆d = 3 and dc = 0.75

It is remarked that the simulation results are consistent with the results of the theoretical analysis. Moreover, the positive and negative voltages of two outputs can be regulated by the variations of ∆d and dc. Generally speaking, the positive and negative amplitudes of two output voltages, and the duties of these two outputs can be modulated by d1, d2, d3, ∆d12,

∆d23, ∆d31, and f, which are the very results required in HEVs. A prototype of the Z-network converter is then built as shown in Fig. 6.11, and the parameters are chosen as follow: Cd1 = Cd2 = Cd3 = 470 µF , C1 = C2 = 200 µF , L1 = L2 = 100 µH,

Z1 = Z2 = 50 Ω, and T = 100 µs.

The prototype shown in Fig. 6.11 is composed of Cd1 , Cd2 , Cd3 , L1, L2, C1, C2, diode D

(Type: MBRF20200), switches S1, S2, S3 (Type: IRFP250A), and the resistive loads Z1 and

Z2, with the driving circuits located in the left side of each switch. There three driving circuits are composed of three generated synchronous driving signals coming from RT-lab equipment (Type: OP5600), and driving ICs TLP2. 1 Fig. 6.12 presents the experimental waveforms of the converter when ∆d = 3 and dc = 0.75. Therein, Fig. 6.12 depicts the driven voltages of three switches, vg1, vg2, vg3, the diode voltage vD, the current of L1, iL1 and two output voltages, vo1 , vo2 , accordingly. In detail, the negative and positive output voltages of Z1 are asymmetric. The positive one is about 15 V, and the negative one is nearly equal to Vd/2, and the width is dcT ; while the negative one is -45 V, 6 A Dual-Output Z-Source Half-Bridge Converter 119

Fig. 6.11: Prototype of the proposed converter

Fig. 6.12: Experimental waveforms in shoot-through case: Case 5

which is much larger than Vd/2. Moreover, the negative and positive output voltage of Z2 are symmetric in amplitude, namely, ±30 V, and its width can be modulated. The experimental results are also consistent with the simulation results. 120 6 A Dual-Output Z-Source Half-Bridge Converter

6.7 Summary

In terms of the impedance networks matching mechanism and converter design methodology, a novel dual-output Z-source half-bridge converter with only three switches has been proposed. Two impedance networks are parallelized to reduce the output impedance. Therein, one fourth of the capacitors and switches are reduced. Moreover, the proposed converter can output two buck-boost voltages, which reduces the economic cost and increases the watt density. Finally, detailed theoretical analysis, parameters design, simulation and experiment have been conducted to verify the effectiveness of the proposed converter, which in turn verifies the effectiveness of the impedance networks matching mechanism and the design methodology. 7 Conclusions 121

Chapter 7

Conclusions

This thesis aims to reveal the impedance network matching mechanism and to propose a systematic methodology for designing impedance source converters. It provides a solution for traditionally tedious, manual, experience-dependent design methods. First of all, a profound qualitative analysis of voltage and current sources converters has been conducted to well understand and reveal the reasons why traditional voltage and current sources converters suffer from the shoot-through or the open-circuit problems, limited output current or voltage gains, and inapplicability to both inductive and capacitive loads, and why impedance source converters with impedance networks can overcome these problems. Following this analysis, the intrinsical impedance network matching mechanism in nonlinear switched power converters has been then revealed, which is different to impedance matching in linear circuits. The impedance network matching mechanism refers to input impedance matching, output impedance matching and load phase matching. In detail, input impedance matching is to increase the input impedance in the short-circuit case, so that the input impedance becomes inductive and the input current is restrained; output impedance matching is to tune the output impedance to be positive or negative, so as to increase or decrease output voltage by connecting an impedance network or adjusting the impedance networks parameters; while load phase matching is to match the output impedance with the load impedance to ensure its impedance phase angle to be 0◦. In terms of the impedance network matching mechanism, a systematic methodology has been proposed for designing novel power converters to replace traditional tedious, manual designs. The proposed methodology includes topology design, selection of impedance networks, input and output impedances calculation, operational status analysis, parameters determination, simulations and experiments. Finally, as examples in special industrial applications, four novel impedance source converters have been devised by applying this design methodology, which are two novel 3-Z-network DC-DC boost converters specified to solar energy systems by cascading three active impedance networks to realize high output voltage gains, a Z-source half-bridge converter for electrochem- 122 7 Conclusions istry power supplies by coupling a Z-network into a half-bridge converter for input impedance matching, and a dual-output Z-source half-bridge converter for electric vehicle systems by parallelizing two impedance networks for output impedance matching. REFERENCES 123

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Appendix: CURRICULUM VITAE

Affiliation and Official Address: Faculty of Mathematics and Computer Science FernUniversitätin Hagen, 58084 Hagen, Germany Tel.: +49-2331-987-4528, Fax: +49-2331-987-375 Date and Place of Birth: 21 October 1986, Shantou, P.R. China Gender: Male

Languages: Chinese (native language), English, Cantonese

Education: Ph.D. in Electrical Engineering, Faculty of Mathematics and Computer Science, FernUniversit¨atin Hagen, Germany, 2011–2015 Ph.D. in Power Electronics and Power Drives, Continuous Academic Project Involving Master and Doctoral Study, South China University of Technology, 2008–2014 Supervisors: Prof. Bo Zhang B.Sc. in Electrical Engineering and Automation, Xi’an University of Technology, China, 2004–2008 Specialisation: (i) Main Fields: Power converters topologies and their applications; (ii) Other Fields: Suppression of electromagnetic interference in power supplies; (iii) Present :Novel power converters topologies for renewable energy; Dynamics of complex networks in smart grids Involvement in Funded Research:

1. AiF-IGF-Project 17211N, Germany 2011–2013 2. Key Programme of National Natural Science Foundation of China, No. 50937001, 2010– 2013 3. National High Technology Research and Development Programme (863 Programme) of China, No. 2007AA05Z299, 2008.10–2010.11 4. National Key Technology Research and Development Programme in the 11th Five Year Plan of China, No. 2008BAF34B09, 2008.10–2010.10 138 Appendix: List of Publications

5. Guangdong Strategic Emerging Industry Special Fund Project No. 2010A081002004, 2011.1–2013.1 6. Guangdong-Hongkong Breakthrough Bidding Project in Key Areas No. 2009205109, 2009.10–2011.10

Academic Activities: 2nd Ph.D. Summer School on “Mathematical Modeling of Complex Systems”, Pescara, July 2012 Special Section Organizer of Nolta Conference on “Power Electronics Converters for Re- newable Energy Grids”, Hongkong, December 2015

Scientific Awards: 2011.10 Guangdong Science Products Technology Identification 2011.11 Scientific Technical Innovation Award by China Power Supply Society, Second Prize 2012.11 China Patent Honorable Mention Award 2013.02 Guangdong Science and Technology Progress Award, Second Prize 2013.06 Dongguang Science and Technology Progress Award, First Prize Honors and Others:

2012-2014 National Scholarships 2011 Scholarship Award for Excellent Doctoral Student granted by Ministry of Education 2010.8 3rd Chinese college students’ competition in energy conservation and emission reduction in social practice and technology, Third Prize 2010.7 1st Chinese youth science and technology innovation contest, First Prize in Products 2010.6 “South Grid Cup” College students’ energy conservation and emission reduction design contest, Second Prize 2009.12 “3M” Creative Scholarship, Special Prize 2009.5 Cantonese Collegiate Challenge Cup, Second Prize 2008.12 1st Chinese college students’ competition in energy conservation and emission reduction in social practice and technology, Second Prize 2007 Chinese Collegiate Challenge Cup, First Prize 2006 Shanxi Collegiate Challenge Cup, Special Prize 2010.8 SemiKron Scholarship, First Prize Appendix: CV 139

List of Publications:

• 1 PCT Patent, 1 US Patent, 17 China Patents, 10 China Patents Pending, 27 China Utility Patents and 5 China Scientiﬁc Software Copyrights • 5 published papers: 2 papers published in IEEE Transaction on Industrial Electronics, 1 paper published in Physica A: Statistical Mechanics and its Applications, 1 paper published in International Journal of Circuit Theory and Applications and 1 paper published in IET Power Electronics. • 3 papers published in Chinese journals • Author or coauthor of 3 book chapters

A – Journal Publications:

1. G. Zhang, Z. Li, B. Zhang, D. Qiu, W. Xiao and W.A. Halang: A Z-Source Half-Bridge Converter, IEEE Transactions on Industrial Electronics, Vol. 61, No. 3, pp. 1269–1279, 2014

2. G. Zhang, Z. Li, B. Zhang, D. Qiu, L. Yang and W.A. Halang: A 3-Z-network Boost Converter, IEEE Transactions on Industrial Electronics, Vol. 62, No. 1, pp. 278–288, 2015

3. G. Zhang, Z. Li, B. Zhang and W.A. Halang: Understanding the cascading failures in Indian power grids with complex networks theory, Physica A: Statistical Mechanics and its Applications, Vol. 392, No. 15, pp. 3273–3280, 2013

4. G. Zhang, Z. Li, B. Zhang and W.A. Halang: Cascading Failures of Power Grids Caused by Line Breakdown, International of Circuit Theory and Applications, doi: 10.1002/cta.2039

5. L. Yang, D. Qiu, B. Zhang and G. Zhang: High-performance Quasi-Z-source Inverter with Low Capacitor Voltage Stress and Small Inductance, IET Power Electronics, Vol. 8, No. 6, pp. 1061–1067, 2015

6. G. Zhang, B. Zhang, W. Xiao and D. Qiu: Topological index and Vulnerability analysis of Buck Converter, Journal of Power Supply, 6, 2012. (In Chinese)

7. G. Zhang, B. Zhang, W. Xiao and D. Qiu: Eﬃcient Energy Saving High-frequency Switched-mode Power Supply and Intelligent System with Electrochemical Processing, Journal of Power Supply, 1, 2011. (In Chinese)

8. G. Zhang, B. Zhang, W. Xiao and D. Qiu: Investigation of Dissipation Model for High Power Switched-mode Power Supply, Power Electronics, 3, pp. 55–58, 2010. (In Chinese) 140 Appendix: List of Publications

B – Submitted to Journals:

1. G. Zhang, Z. Li, B. Zhang and W.A. Halang: Robustness and Fragility of Power Grids Based on the Complex Network Theory, Safety Science.

C – Book Chapters:

1. G. Zhang, Z. Li, B. Zhang and W.A. Halang: Cascading Failures of Power Grids under Edge-attacks, in Autonomous Systems 2013, H. Unger and W.A. Halang (Eds.), pp. 122– 131, Fortschr.-Ber. VDI Reihe 10 No. 827. D¨usseldorf:VDI-Verlag 2013.

2. Y. Song, Z. Li, J. Niu, G. Zhang, W.A. Halang, and H. Hirsch: Reducing EMI in multiple-output DC converters with chaos control, in Uncertainty Modeling in Knowledge Engineering and Decision Making, C. Kahraman, E.E. Kerre and F.T. Bozbura (Eds.), pp. 1155 – 1160, Singapore: World Scientiﬁc 2012.

3. G. Zhang, Z. Li, B. Zhang, and W.A. Halang: Power electronics converters: An overview, in Autonomous Systems 2014 Proceedings of the 7th GI Workshop, Unger and Halang (Eds.), pp. 117-127, Majorca, Spain, ISSN 0178-9627.

D – Key Granted Patents:

1. B. Zhang, G. Zhang, W. Xiao and D. Qiu: Led centralized dc power supply system and operating methods thereof. PCT patent (PCT/CN2011/072899, 2011.4.16).

2. B. Zhang, G. Zhang, W. Xiao and D. Qiu: Led centralized dc power supply system and operating methods thereof. U.S. patent (US2013/0207562, 2015.3.17).

3. B. Zhang, G. Zhang and W. Xiao: Single-phase Voltage-boosting Push-pull Inverter Circuit. China patent (CN200920050479.4, 2010.12.8).

4. B. Zhang, W. Xiao and G. Zhang: A Z-source Half-bridge Inverter. China patent (CN200910036964.0, 2010.12.29).

5. B. Zhang, W. Xiao and G. Zhang: Low Voltage Stress Single-stage AC-DC Converter Based On LLC Series Resonance. China patent (CN200910036833.2, 2011.3.16).

6. B. Zhang, W. Xiao and G. Zhang: Single Stage Half-bridge AC-DC Converter. China patent (CN200910036831.3, 2011.5.18).

7. B. Zhang, W. Xiao and G. Zhang: Single-stage Single-phase AC-DC Convertor Based On LLC Series Resonance. China patent (CN200910036822.4, 2011.6.15).

8. B. Zhang, W, Hu, W. Xiao and G. Zhang: Z Source Soft Switch Power Factor Correcting Full Bridge Converter. China patent (CN200910036963.6, 2012.8.22). Appendix: CV 141

9. B. Zhang, G. Zhang, W. Xiao and D. Qiu: Electroplating Power Supply Circuit Capable Of Realizing Multiple Output Voltage Waveforms. China patent (CN200910246074.2 2012.5.23).

10. B. Zhang, G. Zhang, W. Xiao, D. Qiu and L. Zhao: 50A-grade Low-voltage High- current Power Source Suitable For Integrated Circuits. China patent (CN200910215971.7, 2012.8.8).

11. B. Zhang, Y. Sui, S. Chao, X. Zhang, G. Zhang, W. Xiao and D. Qiu: An AC current ﬂow equalizing LED. China patent (CN201010528538.1, 2012.8.8).

12. B. Zhang, X. Zhang, Y. Sui, S. Chao, G. Zhang, W. Xiao and D. Qiu: A high PFC control method and its control circuit. China patent (CN201010528529.2, 2013.2.13).

13. B. Zhang, Z. Duan, G. Zhang, W. Xiao, W. He, Y. Dai, S. Lin and D. Qiu: A kind of output ﬁlter for high-current electrochemical industrial power supply. China patent (CN201110082217.8, 2013.5.8).

14. B. Zhang, Y. Dai, W. Xiao, Z. Duan, G. Zhang, W. He, S. Lin and D. Qiu: Method and Device of Reducing the switch loss of the phase shifting full bridge converter. China patent (CN201110078847.8, 2013.4.10).

15. B. Zhang, G. Zhang, W. Xiao, W. He, Z. Duan, S. Lin, Y. Dai and D. Qiu: An electrochemical prediction method of the eﬃciency of the high frequency switch power supply. China patent (CN201110255930.8, 2012.7.24).

16. B. Zhang, G. Zhang, W. Xiao and D. Qiu: A centralized dc power system and its LED operation method. China patent (CN201010528546.6, 2013.11.27).

17. B. Zhang, W. He, W. Xiao, G. Zhang, Z. Duan, S. Lin, Y. Dai and D. Qiu: Electro- chemical High frequency switching power supply rectiﬁer with air cooling heat dissipation. China patent (CN201110245792.5, 2014.5.7).

18. B. Zhang, W. Xiao, G. Zhang, Z. Duan, W. He, Y. Dai, S. Lin and D. Qiu: High-power level low-voltage high-current output ﬁlter circuit for high frequency switch power supply. China patent (CN201110273689.1, 2014.5.7).

19. B. Zhang, W. Xiao, S. Lin, Y. Dai, G. Zhang, Z. Duan, W. He, and D. Qiu: Multiple parallelled power supply modules and its control cooperative control method. China patent (CN201110246890.0, 2014.6.11).

20. B. Zhang, W. Xiao and G. Zhang: Single-stage Single-phase AC-DC Convertor Based On LLC Series Resonance. China utility patent (CN200920050479.4, 2009.12.16). 142 Appendix: List of Publications

21. B. Zhang, W. Xiao and G. Zhang: A Z-source Half-bridge Inverter. China utility patent (CN200920050528.4, 2010.1.27).

22. B. Zhang, W. Xiao and G. Zhang: Single Stage Half-bridge AC-DC Converter. China utility patent (CN200920050527.X, 2009.11.11).

23. B. Zhang, W. Xiao and G. Zhang: Low Voltage Stress Single-stage AC-DC Converter Based On LLC Series Resonance. China utility patent (CN200920050529.9, 2009.11.11).

24. B. Zhang, G. Zhang and W. Xiao: Single-phase Voltage-boosting Push-pull Inverter Circuit. China utility patent (CN200920050721.8, 2009.11.11).

25. B. Zhang, W, Hu, W. Xiao and G. Zhang: Z Source Soft Switch Power Factor Correcting Full Bridge Converter. China utility patent (CN200920050735.X, 2009.11.11).

26. B. Zhang, G. Zhang, W. Xiao and D. Qiu: Electroplating Power Supply Circuit Capable Of Realizing Multiple Output Voltage Waveforms. China utility patent (CN200920272487.3, 2010.9.1).

27. B. Zhang, G. Zhang, W. Xiao, D. Qiu and L. Zhao: 50A-grade Low-voltage High-current Power Source Suitable For Integrated Circuits. China utility patent (CN200920215032.8, 2010.11.10).

28. B. Zhang, S. Chao, X. Zhang, Y. Sui, G. Zhang, W. Xiao and D. Qiu: A kind of AC LED drive and dimmer method. China utility patent (CN201020587664.X, 2011.6.1).

29. B. Zhang, X. Zhang, Y. Sui, S. Chao, G. Zhang, W. Xiao and D. Qiu: A high PFC control circuit. China utility patent (CN201020587741.1, 2011.5.18).

30. B. Zhang, Y. Sui, S. Chao, X. Zhang, G. Zhang, W. Xiao and D. Qiu: An AC current ﬂow equalizing LED. China utility patent (CN201020587758.7, 2011.5.11).

31. B. Zhang, G. Zhang, Y. Sui, S. Chao, X. Zhang, W. Xiao and D. Qiu: A standby type AC LED and lighting. China utility patent (CN201020587758.7, 2011.5.11).

32. B. Zhang, G. Zhang, W. Xiao and D. Qiu: A centralized dc power system and its LED operation method. China utility patent (CN201020587765.7, 2011.6.1).

33. B. Zhang, W. He, W. Xiao, G. Zhang, Z. Duan, S. Lin, Y. Dai and D. Qiu: Electro- chemical High frequency switching power supply rectiﬁer with air cooling heat dissipation. China utility patent (CN201120312123.0, 2012.5.30). Appendix: CV 143

34. B. Zhang, Y. Dai, W. Xiao, Z. Duan, G. Zhang, W. He, S. Lin and D. Qiu: Method and device of reducing the switch loss of the phase shifting full bridge converter. China utility patent (CN201120089512.1, 2011.9.14).

35. B. Zhang, Z. Duan, G. Zhang, W. Xiao, W. He, Y. Dai, S. Lin and D. Qiu: A kind of output ﬁlter for high-current electrochemical industrial power supply. China utility patent (CN201120093879.0, 2011.11.2).

36. B. Zhang, W. Xiao, S. Lin, Y. Dai, G. Zhang, Z. Duan, W. He and D. Qiu: Multiple parallelled power supply modules and its control cooperative control method. China utility patent (CN201120313479.6, 2012.8.8).

37. B. Zhang, W. Xiao, G. Zhang, Z. Duan, W. He, Y. Dai, S. Lin and D. Qiu: High-power level low-voltage high-current output ﬁlter circuit for high frequency switch power supply. China utility patent (CN201120346179.8, 2012.8.18).

38. B. Zhang, G. Zhang, F. Xie, W. Xiao and D. Qiu: Power supply for LED Driver. China utility patent (CN201220708899.9, 2013.7.3).

39. B. Zhang, W. He, W. Xiao, G. Zhang, Z. Duan, S. Lin, Y. Dai and D. Qiu: Electro- chemical High frequency switching power supply rectiﬁer with air cooling heat dissipation. China utility patent (CN201120312123.0, 2012.5.30).

40. B. Zhang, W. Xiao, S. Lin, Y. Dai, G. Zhang, Z. Duan, W. He, and D. Qiu: Multiple parallelled power supply modules and its control cooperative control method. China utility patent (CN201120313479.6, 2012.8.8).

41. D. Qiu, L. Yang, B, Zhang, G. Zhang and Z. Huang: An Improved Z-Source DC-DC Boost Converter. China utility patent (CN2013120756259.X, 2013.11.26).

42. B, Zhang, G. Zhang: A Boost converter with high voltage-gain. China utility patent (CN201320445032.3, 2014.2.12).

43. B. Zhang, G. Zhang, L. Yang, D. Qiu, W. Xiao and Z. Huang: High voltage-gain 3-Z- network Boost Converter. China utility patent (CN201320575155.9, 2014.2.12).

44. Z. Huang, B. Zhang, G. Zhang, X. Li, W. Xiao, and D. Qiu: An LED Centralized Micro-Grid System and its Control Method. China utility patent (CN201320700890.8, 2014.6.4).

45. B. Zhang, G. Zhang, and D. Qiu: A dual-output Z-source converter with three capacitors. China utility patent (CN201420055723.7, 2014.9.10). 144 Appendix: List of Publications

46. B. Zhang, G. Zhang, and D. Qiu: An asymmetric dual-output Z-source converter. China utility patent (CN201420056559.1, 2014.10.8).

47. D. Qiu, L. Yang, B, Zhang, G. Zhang and Z. Huang: A quasi-Z-source DC-DC Boost converter. China utility patent (CN201420078873.X, 2014.7.16).

48. D. Qiu, L. Yang, B, Zhang, G. Zhang and Z. Huang: A continuous current DC-DC Boost converter with high voltage gain. China utility patent (CN201420232395.3, 2014.10.8).

E – National Pending Patent:

1. B. Zhang, S. Chao, X. Zhang, Y. Sui, G. Zhang, W. Xiao and D. Qiu: A kind of AC LED drive and dimmer method. China patent (CN201010528425.1, 2010.11.2).

2. B. Zhang, G. Zhang, Y. Sui, S. Chao, X. Zhang, W. Xiao and D. Qiu: A standby type AC LED and lighting. China patent (CN201010527443.8, 2010.11.2).

3. B. Zhang, G. Zhang, F. Xie, W. Xiao and D. Qiu: Power supply for LED Driver. China patent (CN201210557241.7, 2012.12.19).

4. B. Zhang, G. Zhang, L. Yang, D. Qiu, W. Xiao and Z. Huang: High voltage-gain 3-Z- network Boost Converter. China utility patent (CN201310423140.5, 2013.11.20).

5. Z. Huang, B. Zhang, G. Zhang, X. Li, W. Xiao, and D. Qiu: An LED Centralized Micro- Grid System and its Control Method. China patent (CN201310549039.4, 2013.11.7).

6. D. Qiu, L. Yang, B, Zhang, G. Zhang and Z. Huang: An Improved Z-Source DC-DC Boost Converter. China patent (CN201310611112.6, 2013.11.26).

7. B. Zhang, G. Zhang, and D. Qiu: An asymmetric dual-output Z-source converter. China patent (CN201410042979.9, 2014.4.30).

8. B. Zhang, G. Zhang, and D. Qiu: A dual-output Z-source converter with three capacitors. China patent (CN201410043080.9, 2014.4.30).

9. D. Qiu, L. Yang, B, Zhang, G. Zhang and Z. Huang: A quasi-Z-source DC-DC Boost converter. China patent (CN201410062621.2, 2014.5.28).

10. D. Qiu, L. Yang, B, Zhang, G. Zhang and Z. Huang: A continuous current DC-DC Boost converter with high voltage gain. China patent (CN201410191450.3, 2014.8.27).

F – Scientiﬁc Software Copyrights:

1. B. Zhang, G. Zhang, D. Qiu and W. Xiao: High precision electric power grid real-time detection software V1.0, No. 2011SR023670, 2011.4.27. Appendix: CV 145

2. B. Zhang, G. Zhang, W. Xiao, S. Lin, Y. Dai, Z. Duan, W. He and D. Qiu: Electro- chemical power supply parameters monitoring software Based on serial communication V1.0, No.2011SR018305, 2011.4.7.

3. B. Zhang, G. Zhang, W. Xiao, W. He, S. Lin, Z. Duan, Y. Dai and D. Qiu: Electro- chemical power loss estimation software V1.0, No.2011SR023253, 2011.4.26.

4. B. Zhang, S. Lin, W. Xiao, G. Zhang, Y. Dai, Z. Duan, W. He and D. Qiu: Electro- chemical industry power supply information management system V1.0, No.2011SR023667, 2011.4.27.

5. B. Zhang, G. Zhang, G. Yi and S. Lin: Power electronics converter topology index calculation software V1.0, No.2011SR071563, 2011.10.08.