Lecture 15:

Differential Pairs (Part 2)

Gu-Yeon Wei Division of Engineering and Applied Sciences Harvard University [email protected]

Wei 1 Overview

• Reading – S&S: Chapter 6.6 • Supplemental Reading – S&S: Chapter 6.9 – Razavi, Design of Analog CMOS Integrated Circuits: Chapter 4 • Background – Our treatment of MOS differential pairs has assumed ideal elements. However, real devices suffer a variety of mismatches. This lecture will investigate how mismatches in the load and affect performance of the differential pair. We will then conclude our discussion of differential pair with an active-load differential pair that only uses MOS devices.

Wei ES154 - Lecture 15 2 Another Way to Analyze MOS Differential Pairs

• Let’s investigate another technique for analyzing the RD RD RD RD MOS differential pair V XYV V XYV • For the differential pair circuit out1 out2 out1 out2 on the left (driven by two independent signals), compute V V V the output using superposition in1 in2 in1 I I – Start with Vin1, set Vin2=0 and first solve for X w.r.t.

Vin1 – Reduces to a degenerated common-source amp – neglecting channel-length RD modulation and body- RD RD

effect, RS = 1/gm2 V X V XYV out1 –so… out1 out2

M1 VX − gm1RD − RD M V = = V 2 in1 R V 1+ g R 1 1 in1 S in1 m1 S + RS gm1 gm2

Wei ES154 - Lecture 15 3 • Now, solve for Y w.r.t. Vin1

• Replace circuit within box with a Thevenin equivalent RD RD – M is a source follower with V =V 1 T in1 XY Vout1 Vout2 – RT=1/gm1

• The circuit reduces to a common-gate where… M1 M2

V R Vin1 Y = D V 1 1 in1 + gm1 gm2

• So, overall (assuming gm1 = gm2)

− 2RD VX −VY = Vin1 = −gm RDVin1 due to Vin1 R 1 gm1 +1 gm2 D

Y by symmetry Vout2

VX −VY = gm RDVin2 RT due to Vin 2

VT VX −VY Ad = = −gm RD Vin1 −Vin2

Wei ES154 - Lecture 15 4 Offsets in MOS Differential Pair

• There are 3 main sources of offset that affect the performance of MOS differential pair circuits – Mismatch in load – Mismatch in W/L of differential pair devices

– Mismatch in Vt of differential pair devices • Let’s investigate each individually

Wei ES154 - Lecture 15 5 Resistor Mismatch

• For the differential pair circuit shown, consider the case where RD1 RD2 – Load resistors are mismatched by ∆RD V ∆R O R = R ± D D1,2 D 2 – All other devices parameters are perfectly matched • With both inputs grounded, I = I = I/2, but V is not zero 1 2 O I1 I2 due to differences in the voltages across the load resistors I V = ∆R I O 2 D – It is common to find the input-referred offset which is calculated as VOS = VO Ad

–since Ad = gmRD

I VGS −Vt ∆RD gm = VOS = VGS −Vt 2 RD

Wei ES154 - Lecture 15 6 W/L Mismatch

• Now consider what happens when device sizes W/L are mismatched for the two differential pair MOS devices M1 and M2 W  W 1 W    = ± ∆   L 1,2 L 2  L 

• This mismatch causes mismatch in the currents that flow through M1 and M2

I I ∆(W L) I = ± 1,2 2 2 2()W L

– This mismatch results in VO ∆(W L) V = I R O 2()W L D

– So in the input referred offset is… V −V ∆(W L) V = V A V = GS t OS O d OS 2 ()W L

Wei ES154 - Lecture 15 7 Vt Mismatch

• Lastly, consider mismatches in the threshold voltage ∆V V = V ± t t1,2 t 2 µ • Again, currents I1 and I2 will differ according to the following saturation current equation 2 2 1 W  ∆V  1 W 2  ∆V  I = C V −V − t  = µ C ()V −V 1− t 1 n ox GS t n ox GS t  () 2 L  2  2 L  2 VGS −Vt 

– For small ∆Vt << 2(VGS-Vt) 1 W  ∆V  I ∆I I  ∆V  2  t   t  I1,2 ≅ µnCox ()VGS −Vt 1m  = m ∆I =   2 L  VGS −Vt  2 2 2 VGS −Vt 

– Again, using VOS=VO/Ad (Ad = gmRD and VO =2∆IRD) we get…

2(∆I )(R ) 2IR  ∆V V −V D D  t  GS t VOS = =   = ∆Vt Ad 2 VGS −Vt  IRD

Wei ES154 - Lecture 15 8 Mismatch Summary

• The 3 sources of mismatch can be combined into one equation:

VGS −Vt ∆RD ∆()W L  VOS = ∆Vt +  +  2  RD ()W L 

– arising from Vt, RD, and W/L mismatches

• Notice that offsets due to ∆RD and ∆W/L are functions of the overdrive voltage

Wei ES154 - Lecture 15 9 Differential Pair with MOS Loads

Vb

Vout Vout

Vin Vin

I I

• Consider the above two MOS loads in place of resistors • Left:

– a diode connected pMOS has an effective resistance of 1/gmP

gmN Ad = −gmN ()1 gmP || roN || roP ≅ − gmP • Right:

– pMOS devices in saturation have effective resistance of roP

Ad = −gmN (roN || roP )

Wei ES154 - Lecture 15 10 Active-Loaded CMOS Differential Amplifier

• A commonly used amplifier topology in CMOS technologies • Output is taken single-endedly for a differential input M3 M4 – with a vid/2 at the gate of M1, i1 flows i = g (v 2) 1 m id i1 v i o – i1 is also mirrored through the M3-M4 1 i2 –a –vid/2 at the gate of M2 causes i2 to also flow through M2 M1 M2 i2 = gm (vid 2) vid

• Given that ID=I/2 (nominally) I gm = I VGS −Vt

• The voltage at the output then is given by…

vo = (i1 + i2 )(ro2 || ro4 )= 2i1(ro2 || ro4 ) r A = g ()r || r ≅ g o d m o2 o4 m 2

Wei ES154 - Lecture 15 11 Next Time

• Reading: – S&S: Chapter 6.6 • Supplemental Reading: – S&S: Chapter 6.4 – Razavi: Chapter 5

• Overview – We have seen that transconductance and the effective load resistance set the gain of differential amplifiers. We will next investigate a technique called cascoding that can increase the output resistance of MOS devices in saturation. Utilizing this technique, we can build higher quality current sources and amplifiers (w/ MOS loads) with higher gain. We will also see the trade offs this technique imposes.

Wei ES154 - Lecture 15 12