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Differential Amplifiers Differential Amplifiers EE105 - Spring 2007 General Considerations Microelectronic Devices and MOS Differential Pair Circuits Cascode Differential Amplifiers Common-Mode Rejection Differential Pair with Active Load Lecture 8 Differential Amplifiers 2 Audio Amplifier Example Small-Signal Model for Bipolar Transistor An audio amplifier is constructed above that takes on a Some examples in this chapter are explained in bipolar rectified AC voltage as its supply and amplifies an audio transistor circuits signal from a microphone. The small-signal model of a bipolar transistor is very similar to that of the MOSFET, except bipolar transistor has low input impedance at base 3 4 “Humming” Noise in Audio Amplifier Example Supply Ripple Rejection vAvvXvinr=+ vvYr= vvAvXY−= vin However, V contains a ripple from rectification that CC Since both node X and Y contain the ripple, their leaks to the output and is perceived as a “humming” difference will be free of ripple. noise by the user. 5 6 Ripple-Free Differential Output Common Inputs to Differential Amplifier vAvvX =+vin r vAvvYvinr=+ vvXY−=0 Signals cannot be applied in phase to the inputs of a Since the signal is taken as a difference between two differential amplifier, since the outputs will also be in nodes, an amplifier that senses differential signals is phase, producing zero differential output. needed. 7 8 Differential Inputs to Differential Amplifier Differential Signals vAvvXvinr=+ vAvvYvinr=− + vvXY−=2 Av vin A pair of differential signals can be generated, among other ways, by a transformer. When the inputs are applied differentially, the outputs Differential signals have the property that they share the are 180° out of phase; enhancing each other when same average value to ground and are equal in sensed differentially. magnitude but opposite in phase. 9 10 Single-ended vs. Differential Signals Differential Pair With the addition of a tail current, the circuits above operate as an elegant, yet robust differential pair. 11 12 MOS Differential Pair’s Common-Mode Response Equilibrium Overdrive Voltage I I ()VV−=SS VVV== − RSS GS TH equil W XYDDD μ C 2 noxL The equilibrium overdrive voltage is defined as the Similar to its bipolar counterpart, MOS differential pair overdrive voltage seen by M and M when both of them produces zero differential output as VCM changes. 1 2 carry a current of ISS/2. 13 14 Minimum Common-mode Output Voltage Differential Response I VR−>−SS VV DDD2 CMTH In order to maintain M1 and M2 in saturation, the common-mode output voltage cannot fall below the value above. This value usually limits voltage gain. 15 16 Virtual Ground Small-Signal Response Δ=V 0 Δ=VP 0 P VV− Δ=ΔIgV A = XY Dm1 v Δ−−ΔVV() Δ=−ΔIgVDm2 −Δ2gVR = mD 2ΔV =−gRmD VP For small changes at inputs, the gm’s are the same, and the respective increase and decrease of ID1 and ID2 are the same, node P must stay constant to accommodate Since the output changes by -2gmΔVRD and input by these changes. Therefore, node P can be viewed as AC 2ΔV, the small signal gain is –gmRD, similar to that of ground. the CS stage. However, to obtain same gain as the CS 17 stage, power dissipation is doubled. 18 MOS Differential Pair’s Large-Signal Response Maximum Differential Input Voltage Vin1 − Vin 2 max = 2()VGS − VTH equil There exists a finite differential input voltage that 1 W 4ISS 2 II−=μ C VV − −() VV − completely steers the tail current from one DD122 noxinL () 1in2 W inin 12 μ C transistor to the other. This value is known as the noxL maximum differential input voltage. 19 20 The effects of Doubling the Tail Current The effects of Doubling W/L Since W/L is doubled and the tail current remains Since ISS is doubled and W/L is unchanged, the equilibrium unchanged, the equilibrium overdrive voltage will be overdrive voltage for each transistor must increase by 2 to lowered by 2 to accommodate this change, thus ΔVin,max accommodate this change, thus ΔVin,max increases by 2 as well. will be lowered by 2 as well. Moreover, the differential Moreover, since ISS is doubled, the differential output swing will output swing will remain unchanged since neither ISS nor RD has changed double. 21 22 Small-Signal Analysis of MOS Differential Pair Virtual Ground and Half Circuit 1 WW4I II−≈μμ C VV −SS = C IVV − Δ=V 0 D12 D n ox() in 12 inW n ox SS() in 12 in P 2 LLμ C AgR=− noxL vmC When the input differential signal is small compared to Since VP is grounded, we can treat the differential pair 4 ISS/μnCox(W/L), the output differential current is as two CS “half circuits”, with the same small-signal linearly proportional to it, and small-signal model can gain be applied. 23 24 MOS Differential Pair Half Circuit Example I MOS Differential Pair Half Circuit Example II λ = 0 λ ≠ 0 gm1 ⎛⎞1 A =− A =−grr|| || v vm131⎜⎟ OO gm3 ⎝⎠gm3 25 26 Extension of Virtual Ground MOS Differential Pair Half Circuit Example III VX = 0 It can be shown that if R1 = R2, and points A and B go up λ = 0 and down by the same amount respectively, V does not R 2 X A =− DD move. v RSS21+ g m 27 28 MOS Cascode Differential Pair MOS Telescopic Cascode AgrgrvmOmO≈− 13 31 AggrrgrrvmmOOmOO≈− 1331557⎣⎦⎡⎤()|| ( ) 29 30 CM to DM Conversion, ACM-DM Differential to Single-ended Conversion ΔV ΔR out = D Δ+VgRCM1/ m 2 SS If finite tail impedance and asymmetry are both present, Many circuits require a differential to single-ended then the differential output signal will contain a portion conversion, however, the above topology is not very of input common-mode signal. good. 31 32 Supply Noise Corruption MOS Differential Pair with Active Load ISS I +ΔI SS +ΔI 2 2 2ΔI I SS −ΔI 2 This circuit topology performs differential to single-ended The most critical drawback of this topology is supply conversion with no loss of gain. noise corruption, since no common-mode cancellation The input differential pair decreases the current drawn from RL mechanism exists. Also, we lose half of the signal. by ΔI and the active load pushes an extra ΔI into RL by current 33 mirror action; these effects enhance each other. 34 Asymmetric Differential Pair Because of the vastly different resistance magnitude at the drains of M1 and M2, the voltage swings at these two nodes are different and therefore node P cannot be viewed as a virtual ground. 35.
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