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Ultrafast Design Methodology Guide for the Vivado Design Suite

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Ultrafast Design Methodology Guide for the Vivado Design Suite See all versions of this document UltraFast Design Methodology Guide for the Vivado Design Suite UG949 (v2020.1) August 14, 2020 Revision History Revision History The following table shows the revision history for this document. Section Revision Summary 08/14/2020 Version 2020.1 Chapter 3: Design Creation with RTL Moved into separate chapter. Apply Attributes at the Module Level Added link to synthesis attribute propagation rules. Using the CLOCK_DEDICATED_ROUTE Constraint Updated SAME_CMT_COLUMN example. Chapter 4: Design Constraints Moved into separate chapter. Synthesis Flows Added new section. Synthesis Optimizations Added new section. Assessing Post-Synthesis Quality of Results Added new section. Analyzing and Resolving Timing Violations Added information on Report QoR Suggestions. Using MMCM Settings to Reduce Clock Uncertainty Updated recommendations and added equations. Using the Timing Report to Determine the Impact of Power Updated Tcl example. Optimization UG949 (v2020.1) August 14, 2020Send Feedback www.xilinx.com UltraFast Design Methodology Guide 2 Table of Contents Revision History...............................................................................................................2 Chapter 1: Introduction............................................................................................. 5 About the UltraFast Design Methodology................................................................................5 Understanding UltraFast Design Methodology Concepts..................................................... 8 Using the Vivado Design Suite.................................................................................................11 Accessing Additional Documentation and Training..............................................................12 Chapter 2: Board and Device Planning............................................................. 13 PCB Layout Recommendations............................................................................................... 13 Device Power Aspects and System Dependencies................................................................18 Clock Resource Planning and Assignment.............................................................................21 I/O Planning Design Flows.......................................................................................................22 Designing with SSI Devices...................................................................................................... 28 Designing with HBM Devices...................................................................................................34 Configuration.............................................................................................................................38 Chapter 3: Design Creation with RTL.................................................................40 Defining a Good Design Hierarchy......................................................................................... 40 Working with Intellectual Property (IP)..................................................................................44 RTL Coding Guidelines..............................................................................................................47 Clocking Guidelines...................................................................................................................90 Clock Domain Crossing...........................................................................................................140 Chapter 4: Design Constraints.............................................................................145 Organizing the Design Constraints ......................................................................................145 Defining Timing Constraints in Four Steps.......................................................................... 149 Defining Clock Constraints.....................................................................................................150 Constraining Input and Output Ports...................................................................................159 Defining Clock Groups and CDC Constraints.......................................................................168 Specifying Timing Exceptions................................................................................................ 176 Adding Multicycle Path Constraints......................................................................................180 Other Advanced Timing Constraints.....................................................................................183 UG949 (v2020.1) August 14, 2020Send Feedback www.xilinx.com UltraFast Design Methodology Guide 3 Defining Physical Constraints................................................................................................ 184 Chapter 5: Implementation.................................................................................. 185 Running Synthesis...................................................................................................................185 Moving Past Synthesis............................................................................................................192 Implementing the Design...................................................................................................... 197 Chapter 6: Design Closure......................................................................................205 Timing Closure.........................................................................................................................205 Power Analysis and Optimization......................................................................................... 288 Configuration and Debug...................................................................................................... 291 Appendix A: Additional Resources and Legal Notices........................... 301 Xilinx Resources.......................................................................................................................301 Solution Centers...................................................................................................................... 301 Documentation Navigator and Design Hubs...................................................................... 301 References................................................................................................................................302 Training Resources..................................................................................................................304 Please Read: Important Legal Notices................................................................................. 305 UG949 (v2020.1) August 14, 2020Send Feedback www.xilinx.com UltraFast Design Methodology Guide 4 Chapter 1: Introduction Chapter 1 Introduction About the UltraFast Design Methodology The Xilinx® UltraFast™ design methodology is a set of best practices intended to help streamline the design process for today's devices. The size and complexity of these designs require specific steps and design tasks to ensure success at each stage of the design. Following these steps and adhering to the best practices will help you achieve your desired design goals as quickly and efficiently as possible. • This guide, which describes the various design tasks, analysis and reporting features, and best practices for design creation and closure. • UltraFast Design Methodology Quick Reference Guide (UG1231), which highlights key design methodology steps in an easy-to-use, double-sided card format. • UltraFast Design Methodology Timing Closure Quick Reference Guide (UG1292), which covers recommendations for closing timing, including running initial design checks, baselining the design, and resolving timing violations. • UltraFast Design Methodology Checklist (XTP301), which is available in the Xilinx Documentation Navigator and as a standalone spreadsheet. You can use this checklist to identify common mistakes and decision points throughout the design process. • UltraFast Design Methodology System-Level Design Flow diagram representing the entire Vivado® Design Suite design flow, which is available in the Xilinx Documentation Navigator. You can click a design step in the diagram to open related documentation, collateral, and FAQs to help get you started. RECOMMENDED: In addition to these resources, Xilinx recommends the UltraFast Embedded Design Methodology Guide (UG1046) when working with embedded designs and the UltraFast Vivado HLS Methodology Guide (UG1197) when developing complex systems using Vivado IP integrator with C-based IP. Xilinx provides the following resources to help you take advantage of the UltraFast design methodology: TIP: Xilinx also provides methodology-related design rule checks (DRCs) for each design stage, which are available using the report_methodology Tcl command in the Vivado Design Suite. UG949 (v2020.1) August 14, 2020Send Feedback www.xilinx.com UltraFast Design Methodology Guide 5 Chapter 1: Introduction Using This Guide This guide provides a set of best practices that maximize productivity for both system integration and design implementation. It includes high-level information, design guidelines, and design decision trade-offs for the following topics: • Board and Device Planning: Covers decisions and design tasks that Xilinx recommends accomplishing prior to design creation. These include I/O and clock planning, PCB layout considerations, device capacity and throughput
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