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The Binary Arithmetic Binary Arithmetic for Finite-Word-Length Linear Controllers : MEMS Applications Abdelkrim Kamel Oudjida To cite this version: Abdelkrim Kamel Oudjida. Binary Arithmetic for Finite-Word-Length Linear Controllers : MEMS Applications. Automatic Control Engineering. Université de Franche-Comté, 2014. English. NNT : 2014BESA2001. tel-01124332 HAL Id: tel-01124332 https://tel.archives-ouvertes.fr/tel-01124332 Submitted on 6 Mar 2015 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. Thèse de Doctorat école doctorale sciences pour l’ingénieur et microtechniques UNIVERSITÉ DE FRANCHE-COMTÉ Binary Arithmetic for Finite-Word-Length Linear Controllers: MEMS Applications nABDELKRIM KAMEL OUDJIDA THÈSE présentée par Abdelkrim Kamel OUDJIDA pour obtenir le Grade de Docteur de L'Université de Franche-Compté Spécialité: Automatique Binary Arithmetic for Finite-Word-Length Linear Controllers: MEMS Applications Unité de Recherche: FEMTO-ST, UMR CNRS 6174 Soutenue le 20 Janvier 2014 devant le jury: Amara AMARA Président Professeur des Universités, ISEP, Paris Adel BELOUCHRANI Rapporteur Professeur, ENP, Alger Maître de Conférences HDR, Chouki AKTOUF Rapporteur INP de Grenoble Maître de Conférences, Thibault HILAIRE Examinateur Université Paris 6 Directeur de Recherche, Brahim BOUZOUIA Examinateur CDTA, Alger Nicolas CHAILLET Directeur de Thèse Professeur des Universités, Université de Besançon Gödel's Incompleteness Theorems Theorem 1 − Blind spot: There is a sentence G such that if the formal system is consistent, G is not a theorem nor is it not a theorem. Theorem 2 − Consistency: No consistent theory, with a certain amount of arithmetic, can prove its own consistency. i Acknowledgments I wish to thank my supervisor, Prof. Nicolas Chaillet, for the support and trust he so generously provided me in the course of the accomplishment of my task. His continuous enthusiasm and encouragement constituted the driving force of this work. I am deeply grateful to Dr. Brahim Bouzouia, Director of CDTA, for his help and support during all the period of the thesis. I am so indebted to Prof. Noureddine Zerhouni, Mr. Karim Henda, and Prof. Yassine Haddab for their precious help. Without their effective contribution, this thesis would not have been concretized. My special thanks go to my two colleagues, Mohamed Lamine Berrandjia and Ahmed Liacha, for their technical help in a warm and joyful atmosphere. I am much thankful to my ex-student, Khaled Tahraoui, for having provided me with a tremendous number of papers that much contributed to enhance the quality of the work. I would like to acknowledge Dr. Joël Agnus, research engineer within AS2M department of Femto- St institute, for his valuable advices. Finally, I would like to thank my wife and sons for their great patience and support during my seemingly never-ending nights preparing the thesis. ii Abstract This thesis addresses the problem of optimal hardware-realization of finite-word-length (FWL) linear controllers dedicated to MEMS applications. The biggest challenge is to ensure satisfactory control performances with a minimal hardware. To come up, two distinct but complementary optimizations can be undertaken: in control theory and in binary arithmetic. Only the latter is involved in this work. Because MEMS applications are targeted, the binary arithmetic must be fast enough to cope with the rapid dynamic of MEMS; power-efficient for an embedded control; highly scalable for an easy adjustment of the control performances; and easily predictable to provide a precise idea on the required logic resources before the implementation. r The exploration of a number of binary arithmetics showed that radix-2 is the best candidate that fits the aforementioned requirements. It has been fully exploited to designing efficient multiplier cores, which are the real engine of the linear systems. r The radix-2 arithmetic was applied to the hardware integration of two FWL structures: a linear time variant PID controller and a linear time invariant LQG controller with a Kalman filter. Both controllers showed a clear superiority over their existing counterparts, or in comparison to their initial forms. iii Glossary Abstraction Simplification of details, approximation of complex problems ADC Analog to Digital Converter AFM Atomic Force Microscopy ALU Arithmetic and Logic Unit ASIC Application Specific Integration Circuit Ath Adder Depth, the maximum number of serial adder-operations from input to output Avg Average number of additions BHM Bull Horrocks modified, an existing heuristic MCM algorithm BIGE Bounded Inverse Graph Enumeration, an optimal SCM algorithm BMA Booth Multiplication Algorithm, an existing algorithm for signed multiplication CAD Computer-aided design, tools for design automation CDE Common Digit Elimination CLB Configurable Logic Bloc CMOS Complementary Metal Oxide Semiconductor COTS Commercial Off-The-Shelf CSD Canonical Signed Digit, the SD form with no adjacent nonzero digits and the minimum number of nonzero digits CSE Common Subexpression Elimination, a framework for solving SCM and MCM DAC Digital to Analog Converter DAG Directed Acyclic Graphs, a framework for solving SCM and MCM DBNS Double Base Number System, an existing number representation system DFS Dynamic Frequency Scaling Digit Clashing The CSE problem of disappearing patterns due to colliding digits DMAC Double Multiply-And-Accumulate DSP Digital-Signal-Processor/Processing FF Flip-Flop FPGA Field Programmable Gate Array FPR Fixed-Point Representation FWL Finite Word Length H(k) Heuristic with k extra nonzero digits, an existing heuristic SCM algorithm H(k)+ODP The H(k) algorithm with ODPs, a proposed heuristic SCM algorithm Hcub Cumulative Benefit Heuristic, an existing MCM algorithm iv HDL Hardware Description Language Heuristic An effective but potentially suboptimal method for solving a problem HIS Host Side Interface HPM High Performance Multiplication, an existing adder reduction technique IOB Input Output Block Logic resources An abstraction of the amount of silicon required to implement a logic function LQG Linear Quadratic Gaussian LTI Linear Time Invariant LTV Linear Time Variant MAC Multiply-And-Accumulate MAG Minimized Adder Graph, an existing optimal SCM algorithm MBMA Modified Booth Multiplication Algorithm, , an existing algorithm for signed multiplication MCM Multiple Constant Multiplication, find a low-cost add-shift-subtract realization of multiplication by each of the given constants MEMS Micro-Electro-Mechanical Structure MM Matrix Multiplication MPC Model Predictive Control MPM Multi-Precision Multiplication MSD Minimal Signed Digit, any SD representation with the minimum number of nonzero digits MV Multiplication by a Variable NEMS Nano-Electro-Mechanical Structure NP-hard Non-deterministic Polynomial-time hard ODMAC Optimized Double Multiply-And-Accumulate ODP Overlapping Digit Pattern, a proposed technique for partially resolving the CSE digit clashing problem OS Operating System Pattern (CSE) A collection of signed digits that define how existing terms are added-operated together PC Personal Computer PID Proportional Integral Derivative, an existing control law PLD Programmable Logic Device PPG Partial Product Generator RAG-n n-dimensional Reduced Adder Graph, an existing heuristic MCM algorithm RMRMA Recursive-Multibit-Recoding Multiplication Algorithm, a new algorithm RNS Residue Number System, an existing number representation system RTL Register Transfer Level RTOS Real Time Operating System SCM Single Constant Multiplication, same as MCM but for a single constant SD Signed Digit, a recoding used in the CSE framework v Search space The set of all solutions that can be found by an algorithm, this is smaller than the solution space for heuristic algorithms SEM Scanning Electron Microscopy SiGe Silicon Germanium SM Sign and Magnitude SOC System On Chip Solution space The set of all feasible solutions SRAM Static Random Access Memory TC True and Complement TSMC Taiwan Semiconductor Manufacturing Company Upb Upper bound, maximum number of additions VHDL Very high speed integrated circuit Hardware Description Language VLIW Very Large Instruction Word vi Contents 1 General Introduction . 1 1.1 Motivation and Problem Statement . 1 1.2 Objective of the Thesis. 1 1.3 Requirements and Specifications. 2 1.4 Contribution of the Thesis. 3 1.5 Organization of the Thesis . 4 2 Problem Background . 6 2.1 Application Context . .6 2.2 Micromanipulation as a MEMS application . .8 2.3 Embedded Control-Electronics for MEMS . 10 2.4 Review of the Basic Digital Solutions for Embedded Control . 12 2.4.1 Commercial Off-The-Shelf (COTS) Electronics Components . 12 2.4.2 Digital Signal Processors (DSPs) . 12 2.4.3 Field Programmable Gate Arrays (FPGA) . .13 2.4.4 Application Specific Integrated Circuits (ASIC) . 14 2.5 Overview of Finite-Word-Length (FWL) Controller Optimizations . 16 2.5.1 Definition of the FWL Effect. 16 2.5.2 Control-Theory Based Optimization. 17 2.5.3 Binary-Arithmetic Based Optimization . 19 2.5.3.1 Multiplication by a Constant . 19 2.5.3.2 Multiplication by a Variable . .21 2.5.3.3 Multi-Precision Multiplication. 22 2.6 Conclusion . 23 3 The Binary Arithmetic. 28 3.1 Introduction to the Binary Arithmetic . 28 3.2 Number Representation Formats. 29 3.2.1 Fixed-Point Format. 30 3.2.1.1 Representation of Nonnegative Integers. 30 3.2.1.2 Representation of Signed Integers . 32 3.2.1.3 Fixed-Point Arithmetic of Two's Complement Numbers . 33 3.2.1.4 Multiplication. 34 3.2.1.5 Addition. 35 3.2.1.6 Overflow Detection . 35 3.2.2 Floating-Point Format. 35 vii 3.2.2.1 Dynamic Range. 36 3.2.2.2 Precision . .36 3.3 Number Representation Systems. 38 3.3.1 Canonical Signed Digit (CSD) . 39 3.3.2 Double Base Number System (DBNS) .
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