The Effect of Coating and Potting on the Reliability of QFN Devices
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FC-PBGA, Flip Chip Plastic Ball Grid Array
TM Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, t he Energy Efficient Solutions logo, mobileGT, PowerQUICC, QorIQ, StarCore and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, Kinetis, MXC, Platform in a Package, Processor Expert, QorIQ Qonverge, Qorivva, QUICC Engine, SMARTMOS, TurboLink, VortiQa and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2011 Freescale Semiconductor, Inc. Table of Contents Slide 1. FC-PBGA Package Configurations 3 2. Printed Circuit Board Design for FC-PBGA 11 3. Surface Mount Assembly 16 4. Component Level Qualification 29 5. Board-Level Reliability 31 6. Thermal Performance 38 Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, the Energy Efficient Solutions logo, mobileGT, PowerQUICC, QorIQ, StarCore and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, Kinetis, MXC, Platform in a TM 2 Package, Processor Expert, QorIQ Qonverge, Qorivva, QUICC Engine, SMARTMOS, TurboLink, VortiQa and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2011 Freescale Semiconductor, Inc. TM FC-PBGA Package Configurations Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, t he Energy Efficient Solutions logo, mobileGT, PowerQUICC, QorIQ, StarCore and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, Kinetis, MXC, Platform in a Package, Processor Expert, QorIQ Qonverge, Qorivva, QUICC Engine, SMARTMOS, TurboLink, VortiQa and Xtrinsic are trademarks of Freescale Semiconductor, Inc. -
Manufacturing and Reliability Challenges with QFN
Manufacturing and Reliability Challenges With QFN Dr. Craig Hillman and Cheryl Tulkoff DfR Solutions SMTA DC Chapter Ashburn, VA February 25, 2009 QFN as a ‘Next Generation’ Technology What is ‘Next Generation’ Technology? Materials or designs currently being used, but not widely adopted (especially among hi-rel manufacturers) Carbon nanotubes are not ‘Next Generation’ Not used in electronic applications Ball grid array is not ‘Next Generation’ Widely adopted © 2004 - 2007 2 Introduction (cont.) Why is knowing about ‘Next Generation’ Technologies important? These are the technologies that you or your supply chain will use to improve your product Cheaper, Faster, Stronger, ‘Environmentally-Friendly’, etc. And sooner then you think! © 2004 - 2007 3 Reliability and Next Gen Technologies One of the most common drivers for failure is inappropriate adoption of new technologies The path from consumer (high volume, short lifetime) to high rel is not always clear Obtaining relevant information can be difficult Information is often segmented Focus on opportunity, not risks Can be especially true for component packaging BGA, flip chip, QFN © 2004 - 2007 4 Component Packaging Most of us have little influence over component packaging Most devices offer only one or two packaging styles Why should you care? Poor understanding of component qualification procedures Who tests what and why? © 2004 - 2007 5 Component Testing Reliability testing performed by component manufacturers is driven by JEDEC JESD22 series (A & B) Focus is -
Land Grid Array (LGA) Package Rework
Freescale Semiconductor Document Number: AN3241 Application Note Rev. 1.0, 10/2009 Land Grid Array (LGA) Package Rework 1 Introduction Contents 1 Introduction . 1 This application note describes rework considerations 2 What is LGA? . 3 for the Land Grid Array (LGA) style package. 3 LGA Rework . 5 4 Package Removal . 6 Freescale has introduced radio frequency (RF) modules 5 LGA Reliability . 14 such as the MC1320x and MC1321x in LGA packages as 6 References . 14 an alternative package to ball grid array (BGA). The LGA packages reduce the amounts of lead in finished products and are Reduction of Hazardous Substances (RoHS) compliant, optimized for improved radio-frequency (RF) performance for wireless applications, and/or reduce the overall height of the package by eliminating the stand-off height associated with BGA balls. For assistance with any questions about the information contained in this note or for more details about the MC1320x and MC1321x devices, visit www.freescale.com/802154. or contact the appropriate product applications team. © Freescale Semiconductor, Inc., 2009. All rights reserved. Introduction 1.1 Acronyms and Abbreviations BGA Ball Grid Array BT Bismaleimide Triazine CBGA Ceramic Ball Grid Array CTE Coefficient of Thermal Expansion EU European Union ESD Electrostatic Discharge HCTE High Coefficient of Thermal Expansion HDI High Density Interconnect LGA Land Grid Array LTCC Low Temperature Co-fired Ceramic MSLn Moisture Sensitivity Level n NSMD Non-Solder Mask Defined OSP Organic Solderability Protectant PCB Printed Circuit Board RF Radio Frequency RoHS Reduction of Hazardous Substances SMD Solder Mask Defined SMT Surface Mount Technology Land Grid Array (LGA) Package Rework Application Note, Rev. -
Recommendations for Board Assembly of Infineon Ball Grid Array Packages
Recommendations for Board Assembly of Infineon Ball Grid Array Packages Additional Information Please read the Important Notice and Warnings at the end of this document Revision 4.0 www.infineon.com page 1 of 18 2020-11-09 Recommendations for Board Assembly of Infineon Ball Grid Array Packages Table of Contents Table of Contents Table of Contents ........................................................................................................................... 2 Acronyms and Abbreveations ........................................................................................................... 3 1 Package Description ............................................................................................................... 4 1.1 BGA Package Type ................................................................................................................................... 4 1.3 Package Features and General Handling Guidelines ............................................................................. 5 2 Printed Circuit Board .............................................................................................................. 7 2.1 Routing .................................................................................................................................................... 7 2.2 Pad Design ............................................................................................................................................... 7 3 PCB Assembly ....................................................................................................................... -
Ceramic Leadless Chip Carrier (LCC)
Ceramic,Leadless,Chip,Carrier,(L Ceramic Leadless Chip Carrier (LCC) Literature Number: SNOA023 Ceramic Leadless Chip Carrier (LCC) August 1999 Ceramic Leadless Chip Carrier (LCC) 20 Lead Ceramic Leadless Chip Carrier, Type C NS Package Number E20A © 2000 National Semiconductor Corporation MS101105 www.national.com 20 Lead Ceramic Leadless Chip Carrier NS Package Number EA20B Ceramic Leadless Chip Carrier (LCC) www.national.com 2 Ceramic Leadless Chip Carrier (LCC) 24 Lead Ceramic Leadless Chip Carrier NS Package Number E24B 28 Lead Ceramic Leadless Chip Carrier, Type C NS Package Number E28A 3 www.national.com 28 Lead Ceramic Leadless Chip Carrier, Dual Cavity NS Package Number EA028C Ceramic Leadless Chip Carrier (LCC) www.national.com 4 Ceramic Leadless Chip Carrier (LCC) 32 Lead Ceramic Leadless Chip Carrier, Type C NS Package Number E32A 32 Lead Ceramic Leadless Chip Carrier, Type C NS Package Number E32B 5 www.national.com 32 Lead Ceramic Leadless Chip Carrier, Type C NS Package Number E32C Ceramic Leadless Chip Carrier (LCC) 32 Lead Ceramic Leadless Chip Carrier, Type E NS Package Number EA32B www.national.com 6 Ceramic Leadless Chip Carrier (LCC) 32 Lead Ceramic Leadless Chip Carrier, DIP NS Package Number EA32C 40 Lead Ceramic Leadless Chip Carrier, Type C NS Package Number E40A 7 www.national.com 44 Lead Ceramic Leadless Chip Carrier, Type C NS Package Number E44A Ceramic Leadless Chip Carrier (LCC) 48 Lead Ceramic Leadless Chip Carrier NS Package Number EA48B www.national.com 8 Ceramic Leadless Chip Carrier (LCC) 68 Lead Ceramic -
PDF Package Information
This version: Apr. 2001 Previous version: Jun. 1997 PACKAGE INFORMATION 1. PACKAGE CLASSIFICATIONS This document is Chapter 1 of the package information document consisting of 8 chapters in total. PACKAGE INFORMATION 1. PACKAGE CLASSIFICATIONS 1. PACKAGE CLASSIFICATIONS 1.1 Packaging Trends In recent years, marked advances have been made in the electronics field. One such advance has been the progression from vacuum tubes to transistors and finally, to ICs. ICs themselves have been more highly integrated into LSIs, VLSIs, and now, ULSIs. With increased functions and pin counts, IC packages have had to change significantly in the last few years in order to keep-up with the advancement in semiconductor development. Functions required for conventional IC packages are as follows: 1) To protect IC chips from the external environment 2) To facilitate the packaging and handling of IC chips 3) To dissipate heat generated by IC chips 4) To protect the electrical characteristics of the IC Standard dual-in-line packages (DIP), which fulfill these basic requirements, have enjoyed wide usage in the electronics industry for a number of years. With increasing integration and higher speed ICs, and with the miniaturization of electronic equipment, newer packages have been requested by the industry which incorporate the functions listed below: 1) Multi-pin I/O 2) Ultra-miniature packages 3) Packages suited to high density ICs 4) Improved heat resistance for use with reflow soldering techniques 5) High throughput speed 6) Improved heat dissipation 7) Lower cost per pin In response to these requests, OKI has developed a diversified family of packages to meet the myriad requirements of today’s burgeoning electronics industry. -
Quad Flat No-Lead (QFN) Evauation Test
National Aeronautics and Space Administration Quad Flat No-Lead (QFN) Evaluation Testing Reza Ghaffarian, Ph.D. Jet Propulsion Laboratory Pasadena, California Jet Propulsion Laboratory California Institute of Technology Pasadena, California 6/17 National Aeronautics and Space Administration Quad Flat No-Lead (QFN) Evaluation Testing NASA Electronic Parts and Packaging (NEPP) Program Office of Safety and Mission Success Reza Ghaffarian, Ph.D. Jet Propulsion Laboratory Pasadena, California NASA WBS: 724297.40.43 JPL Project Number: 104593 Task Number: 40.49.02.35 Jet Propulsion Laboratory 4800 Oak Grove Drive Pasadena, CA 91109 http://nepp.nasa.gov 6/17 This research was carried out at the Jet Propulsion Laboratory, California Institute of Technology, and was sponsored by the National Aeronautics and Space Administration Electronic Parts and Packaging (NEPP) Program. Reference herein to any specific commercial product, process, or service by trade name, trademark, manufacturer, or otherwise, does not constitute or imply its endorsement by the United States Government or the Jet Propulsion Laboratory, California Institute of Technology. Copyright 2017. California Institute of Technology. Government sponsorship acknowledged. Acknowledgments The author would like to acknowledge many people from industry and the Jet Propulsion Laboratory (JPL) who were critical to the progress of this activity including the Rochester Institute of Technology (RIT). The author extends his appreciation to program managers of the National Aeronautics and Space -
Building Your Prototype
Building Your Prototype Prototype Construction Techniques Part Numbers Package Types Specification Sheets Schematic Diagrams Practical Advice T. Grotjohn, [email protected] Prototype Construction Techniques 1) Protoboard Use DIP components Keep your wires neat and color coded Prone to bad connections Maximum operating speed: ~ few MHz 2) Wire Wrap Often done using wire wrap sockets on a vector board Use DIP components Wire used is good for digital signals Be careful with high current lines because the wire is small. Typical wire: 30 gauge 0.34 Ω/m 28 gauge 0.21 Ω/m 3) Soldered Board Single solder points board Tied solder points board (Your mini project #1) PCB: printed circuit board PCB can be made for ECE 480 projects in the ECE Shop: See the shop’s web page. (Also see the next page) . Printed Circuit Board System General Information T-Tech Protyping Machine ECE 482 Student Project Design Department of Electrical and Computer Engineering, 1999 Michigan State University, East Lansing, Michigan, USA Part Numbers Typical Part Number: DM8095N Prefix: Indicates the manufacture of the part. See two pages in Attachment 1. Suffixes: Indicates temperature range: “military”, “industrial”, “commercial” Also the suffixes are used to indicate package types. The ECE shop deals most often with the following electronic part suppliers. Allied Electronics (www.alliedelec.com) Digi Key (www.digikey.com) Newark Electronics (www.newark.com) For other (non-electronic) supplies, suppliers often used are Grainger (www.grainger.com) McMaster Carr (www.mcmaster.com) Package Types DIP: Dual Inline Package Easiest to use. Works in protoboards, solder boards, wire wrapping, easiest to solder components to PCB This is your choice for ECE 480. -
Design for Flip-Chip and Chip-Size Package Technology
As originally published in the IPC APEX EXPO Proceedings. Design for Flip-Chip and Chip-Size Package Technology Vern Solberg Solberg Technology Consulting Madison, Wisconsin Abstract As new generations of electronic products emerge they often surpass the capability of existing packaging and interconnection technology and the infrastructure needed to support newer technologies. This movement is occurring at all levels: at the IC, at the IC package, at the module, at the hybrid, the PC board which ties all the systems together. Interconnection density and methodology becomes the measure of successfully managing performance. The gap between printed boards and semiconductor technology (wafer level integration) is greater than one order of magnitude in interconnection density capability, although the development of fine-pitch substrates and assembly technology has narrowed the gap somewhat. All viable efforts are being used in filling this void utilizing uncased integrated circuits (flip-chip) and incorporating more than one die or more than one part in the assembly process. This paper provides a comparison of different commonly used technologies including flip-chip, chip-size and wafer level array package methodologies detailed in a new publication, IPC-7094. It considers the effect of bare die or die-size components in an uncased or minimally cased format, the impact on current component characteristics and reviews the appropriate PCB design guidelines to ensure efficient assembly processing. The focus of the IPC document is to provide useful and practical information to those who are considering the adoption of bare die or die size array components. Introduction The flip-chip process was originally established for applications requiring aggressive miniaturization. -
Packaging Product Specification
Packaging Product Specification PS007225-0607 Copyright ©2007 by ZiLOG, Inc. All rights reserved. www.zilog.com DO NOT USE IN LIFE SUPPORT Warning: LIFE SUPPORT POLICY ZiLOG'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF ZiLOG CORPORATION. As used herein Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness. Document Disclaimer ©2007 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZiLOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. The information contained within this document has been verified according to the general principles of electrical and mechanical engineering. Z8, Z8 Encore!, Z8 Encore! XP, Z8 Encore! MC, Crimzon, eZ80, and ZNEO are trademarks or registered trademarks of ZiLOG, Inc. -
Case Study | Land Grid Array (LGA) Μmodule
Case Study | Land Grid Array (LGA) μModule 645 Harvey Road Manchester, NH 03103 (603) 669‐9181 About EPE Corp. HIGH RELIABILITY EMS provider EPE Corp. Establishes Expertise in Land Grid Array Assembly and Wins Customer Certification www.epecorp.com EPE is a leading supplier of The land grid array (LGA) is a packaging technology with a square grid of flat contacts high‐reliability Electronic that are meant to interconnect with an opposing grid of contacts on a printed circuit Manufacturing Services. Our board (PCB). Also referred to as a QFN "Quad Flat No Lead" or MLFP "Micro Lead deep manufacturing and Frame Plastic" package, LGA packaging is related to ball grid array (BGA) and pin grid engineering expertise, strong array (PGA) packaging, but unlike pin grid arrays, land grid array packages are financial position, and designed to either fit into a socket or be soldered down using surface mount passionate dedication to technology. PGA packages cannot be soldered down using surface mount technology. quality and integrity are at the Further, land grid array packages in non‐socketed configurations use a flat contact foundation of an established which is soldered directly to the PCB, wheras BGA packages have balls as their structure that supports the contacts in between the IC and the PCBs. electronic manufacturing needs of customers in diverse The assembly of LGA packages using soldered surface mount technology is inherently industries – and a demanding challenging because the interface between the flat contacts and the PCB surface can marketplace trap air pockets, causing voids during processing. Such voids are exceptionally difficult to eliminate and to repair or rework the packages are both time consuming and carry GOAL signifciantly high costs. -
Package Reliability As Affected by Material and Processes
I,, '• Package Reliability as Affected By Materials and Processes The semiconductor industry is faced with the problem of how to increase the level of reliability of semiconductor parts being used in electronic systems which have had their lifetimes extended through new and.better system designs. By David Nixen, cussed, are all commercially availc1ble and presently The Aerospace Corporation, being used in high volume in industry. It is not the El Segundo, California intention of this article to present any new, revolu tionary packaging approach, but rather to compare the advantages and disadvantages of the major types The word "reliability" has been used in the semicon as they relate to reliability. uuctor industry over the years in every imaginable The actual choice of which package to use will not way. It may refer to why the cost is so high, the be presented here since that choice is too highly delivery so late, the documentation so voluminous, dependent upon the unique conditions of each indi or, it may be why the system is successful. When vidual case. discussed in the true sense of the word, perhaps reliability has no greater importance than in aero PACKAGE FAMILIES ,, , space systems. The basic package families are divided into three Until this year, a spacecraft system had a projected groups; these three groups, in turn, can be subdivid life of three to five years. Since an orbiting system ed and they, in turn, can also be subdivided. Only cannot be considered in a "repair/replace" categoryr the major families will be discussed, although some a component was required to have an extremely high of the subdivisions will be acknowledged.