Module 2

Serial Communication Standards and Devices

Introduction

Serial communication is common method of transmitting between a computer and a peripheral device. Serial communication is the process of sending data one bit at a time, sequentially, over a single communication line to a receiver.

Parallel communication is a method of conveying multiple binary digits (bits) simultaneously in data transmission.

Synchronous Transmission: The sender and receiver should have synchronized clocks before data transmission.

Asynchronous Transmission does not require a clock but it adds a to the data before transmission. Simplex, Half-Duplex, and Full-Duplex Communication Links

Communication Protocol: A protocol is a standard adopted, which tells the way in which the bits of a frame must be sent from a device to another device or system.

The can access devices via several serial interfaces. In real time application serial connections are typically used to limit no: of wire/connections required to communicate between the functional modules.

UART: Universal Asynchronous Receiver Transmitter

UART is a serial communication device that performs parallel to serial data conversion at the transmitter and serial to parallel data conversion at the receiver side. UART is being used in many applications GPS Receivers, Bluetooth Modules, GSM and GPRS Modems, Wireless Communication systems and RFID based systems.

Features

 It is a simple half-duplex, asynchronous, serial protocol  Simple communication between two equivalent nodes.  Any node can initiate communication.  Since connection is half-duplex, the two lanes of communication are completely independent.  It is universal since its parameters (format, speed ..) are configurable.  It is ‘asynchronous’ since it doesn’t have a clock. Rate: It is the no: of bits transmitted/received per second

UART packet format

Working of UART: In UART serial communication, the data is transmitted asynchronously. instead of clock signals, UART uses some special bits called start and stop bits. These bits are added to the actual data packet at the beginning and end respectively. These additional bits allow the receiving UART to identify the actual data.

Connections for UART

UART Characteristics

 The speed of communication (measured in ) is predetermined on both ends.  A general rule of thumb is to use 9600 bauds for .  UART implements error-detection in the form of parity bit.

Parity Bit

•Parity bit is HIGH when number of 1’s in the Data is odd.

•Respectively, it is LOW when number of 1’s in the Data is even.

HDLC (HIGH- LEVEL Data Link Control)

 The OSI’s data link protocol

 A bit-oriented protocol that supports both half –duplex and full duplex communication over point to point & multipoint link.

 On transmitting side, HDLC receives data from an application, and delivers it to the receiver on the other side of the link

 On the receiving side, HDLC accepts the data and delivers it to the higher level application layer

 There are two formats Standard HDLC and Extended HDLC for and 28 and 216 destination devices or systems, respectively.

For any HDLC communication session one station is designated primary and the other secondary. A session can use one of the following connection modes:

1. Normal unbalanced: The secondary station responds only to the primary station. 2. Asynchronous: The secondary station can initiate a message 3. Asynchronous balanced : Both stations send and receive over its part of a duplex line.

HDLC Frame Structure

 Flag bits (both opening and closing flags):8 bits( 01111110 or 7E hex)  Address bits : 8 bits in Standard HDLC format and 16 bits in extended format  Control field: The control field distinguishes between the three different types of frames used in HDLC, namely information, control and unnumbered frames. The first one or two bits of the field determine the type of frame.  Information field: The information field does not have a length specified by HDLC. In practice, it normally has a maximum length determined by a particular implementation. Information frames (also known as I-frames) are the only frames that carry information bits which are normally in the form of a fixed-length block of data of several kilobytes in length  Frame check sequence: The FCS field contains error-checking bits, normally 16 bit with a provision for increasing this to 32. If the FCS fails, the frame is discarded.

Types of Frames in HDLC o Information frames: contain user data o Supervisory frames: flow/error control (ACK/ARQ) o Unnumbered frames: variety of control functions

Instruction Frames

 The first bit of control field is always zero, i.e. the presence of zero at this place indicates that it is I-frame.  Bit number 2, 3 & 4 in control field is called N(S) that specifies the sequence number of the frame. Thus it specifies the number of the frame that is currently being sent. Since it is a 3.bit field, only eight sequence numbers are possible 0, 1,2,3,4,5,6, 7 (000 to 111).  Bit number 5 in control field is P/F i.e. Poll/Final and is used for these two purposes. It has, meaning only when it is set i.e. when P/F=1. It can represent the following two cases. (i) It means poll when frame is sent by a primary station to secondary (when address field contains the address of receiver). (ii) It means final when frame is sent by secondary to a primary (when the address field contains the address of the sender).

 Bit number 6, 7, and 8 in control field specifies N(R) i.e. the sequence number of the frame expected in return in two-way communication. Supervisory frames

 S-frame carries control information, primarily flow and error controls.  It does not contain information field.  The first two bits in the control field of S-frame are always 10.  Then there is a bit code field that specifies four types of S-frame with combination 00,01, 10, 11 as shown in table :-

(i) RR, Receive Ready-used to acknowledge frames when no I-frames are availab1e (ii) REJ Reject-used by the receiver to send a NAK when error has occurred. (iii) RNR Receive Not Ready-used for flow control. (iv) SREJ Selective Reject-indicates to the transmitter that it should retransmit the frame. • There is no N(S) field in control field of S-frame as S-frames do not transmit data. • P/F bit is the fifth bit and serves the same purpose as discussed earlier. • Last three bits in control field indicates N(R) i.e. they correspond to the ACK or NAK value. Unnumbered frame

• U-frames are reserved for system management and information carried by them is used for managing the link • Information field in U-frame does not carry user information rather, it carries system management information. • U-frame is identified by the presence of 11 in the first and second bit position in control field. • These frames do not contain N(S) or N(R) in control field. • U-frame contains two code fields, one two hit and other three bit. • These five bits can create upto 32 different U-frames. • .P/F bit in control field has same purpose as discussed earlier.

HDLC Operation

 Initialization: S-frames specify mode and sequence numbers, U-frames acknowledge

 Data Transfer: I-frames exchange user data, S-frames acknowledge and provide flow/error control

 Disconnect: U-frames initiate and acknowledge SCI (Serial Connect )

 SCI is a UART asynchronous mode port  SCI is port with Full-duplex mode  SCI is programmable for transmission and for reception  This interface uses three dedicated pins: transmit dara(TXD), receive data(RXD), and SCI serial clock –SCLK(optional for synchronous communication). It supports industry standard asynchronous bit rates and protocols as well as high speed (upto 5 Mbps for a 40-MHZ clock) synchronous data transmission.  The SCI consists of separate transmit and receive sections whose operations can be asynchronous with respect to each other.  The Serial Communications Interface (SCI) module is a relatively slow, asynchronous communication port that is widely used to communicate with other embedded systems and devices  The SCI configuration allows for a number of options for data transmission and reception. In the simplest configuration, ten bits are involved : a start bit (logical 0), the 8 data bits, and a stop bit (logical 1).  An example transmission waveform, is shown below.

 Serial in and serial out lines baud rate not separately program  The signals used in SCI are listed in the figure below

SPI (Serial Peripheral Interface)

 SPI is a Full‐duplex Synchronous communication protocol.  It is Fast, easy to use, and simple  Common serial interface on many  It Supports Single master and Multiple slaves  Simple 8-bit exchange between two devices. o Master initiates transfer and generates clock signal o Slave device selected by master  One-byte at a time transfer  The signals used in SPI are listed in the figure below

Fig: single master and single slave

 SCLK is the serial clock from master.  MOSI (Master Out Slave In) is the output from master  MISO (Master In Slave Out) is the input to the master.  Data is shifted out of the master's MOSI pin and in it's MISO pin  Data transfer is initiated by simply writing data to the SPI data register.  All data movement is coordinated by SCK.  Slave select may or may not be used depending on interfacing device.  Device selection as master or slave can be done by applying a signal to input SS pin.  When this pin is 0, then the device act as Master.  When this pin is 1, then the device act as slave.

SPI Block Diagram (SPI hardware)

 8-bits transferred in each direction every time  Master generates clock  MOSI: “Master Out Slave In”; MISO: “Master In Slave Out” o Connect MOSI to MOSI and MISO to MISO o Very clean terminology, unlike “TX” and “RX” which are easy to confuse  Slave Select (SS) used to select one of many slaves  Master asserts slave/chip select line  Shift registers shift data in and out  Terminology varies: o Instead of SS, “Chip Select” (CS) o Instead of MOSI and MISO, SIMOD and SOMI

Master and multiple independent slaves

Serial Protocols

I2C(Inter )

 Developed and patented by Philips for connecting low speed peripherals to a motherboard, embedded system or cell phone  Synchronous ,half duplex, byte oriented, serial protocol  Multi-master, two wire bus , up to 100 kbits/sec

 One data line (SDA)‏

 One clock line (SCL)‏

 Master controls clock for slaves  Each connected slave has a unique 7-bit address

 Each device has its own unique address fixed by hardware.

I2C Terminology

 Transmitter – The device sending data to the bus

 Receiver – Device receiving data from the bus

 Master – device initiating a transfer, generates to clock and terminates a transfer

 Slave – Device addressed by the master

 Multi-master – more than one master can attempt to control the bus

 Arbitration – procedure to insure that only one master has control of the bus at any instant

 Synchronization – procedure to synchronize the clocks of two or more devices

Fig: Basic I2C block I2C Master-to-Slave Data Transfer Sequence 1. Send the Start bit(S) 2. Send the slave address(ADDR) 3. Send the Read(R)-1/Write(W)-0 bit 4. Wait for/Send an acknowledge bit(A) 5. Send/Receive the data bytes (8 bits)(DATA) 6. Expect/Send acknowledge bit(A) 7. Send the STOP bit

Fig: I2C data transfer

 Start: SDA goes low while SCL is high

 Master sends address of slave (7-bits) on next 7 clocks

 Master sends read/write request bit o 0-write to slave o 1-read from slave

 Slave ACKs to master

 Data transfers now commence

Data Transfer from master to slave

fi : Instruction sequence data from master to slave

A master device sends the sequence S ADDR W and then waits for an acknowledge bit (A) from the slave which the slave will only generate if its internal address matches the value sent by the master. If this happens then the master sends DATA and waits for acknowledge (A) from the slave. The master completes the byte transfer by generating a stop bit (P) (or repeated start).

Data transfer from slave to master

Fig : Instruction sequence data from slave to master

A similar process happens when a master reads from the slave but in this case, instead of W, R is sent. After the data is transmitted from the slave to the master the master sends the acknowledge (A). If instead the master does not want any more data it must send a not- acknowledge which indicates to the slave that it should release the bus. This lets the master send the STOP or repeated START signal.

START and STOP Signal Definition

START condition (S) SCL = 1, SDA falling edge

STOP condition (P) SCL = 1, SDA rising edge

The following diagram shows the above information graphically - these are the signals you would see on the I2C bus.

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Fig : START (S) and STOP (P) bits

CAN BUS (Controller Area Network Bus)

 CAN (Controller Area Network) is a serial bus system used to communicate between several embedded 8-bit and 16-bit microcontrollers.  It was originally designed for use in the automotive industry but is used today in many other systems (e.g. home appliances and industrial machines).  Highest Baud Rate is 1Mbit.  CAN uses a message oriented transmission protocol.  There are no defined addresses, just defined messages.

CAN Frame CAN devices send data across the CAN Network on packets called frames. A typical CAN frame contains an arbitration ID, a data field, a remote frame, an error frame, and an overload frame.

Fig: Standard CAN frames

Fig: Extended CAN

 SOF – Start of Frame. It indicates start of message  Arbitration ID– Tells the content of message and priorityThe arbitration ID determines the priority of the messages on the bus. If multiple nodes try to transmit a message onto the CAN bus at the same time, the node with the highest priority (lowest arbitration ID) automatically gets bus access. Nodes with a lower priority must wait until the bus becomes available before trying to transmit again. The waiting devices wait until the end of the frame section is detected.

Fig: CAN Arbitration  RTR – Remote Transmission Request. It identifies whether it’s a data frame or a remote frame .RTR is dominant when it is a data frame and recessive when it is a remote frame.

 SRR- Substitute Reverse Request. The SRR bit is always transmitted to ensure that, in the case of arbitration between a Standard Data Frame and an Extended Data Frame, the Standard Data Frame will always have priority if both messages have the same base (11 bit) identifier.

 IDE – Identifier extension (distinguishes between CAN standard, 11 bit identifier, and CAN extended, 29 bit identifier.)  R0 - Reversed bit. Not used currently and kept for future use.  R1- It is another bit not used currently and kept for future use.  DLC – Data Length Code. It is 4 bit data length code that contains the number of bytes being transmitted.  Data – holds up to 8 bytes of data.  CRC – “Cyclic Redundant Check” sum. The 16-bit cyclic redundancy check (CRC) contains the checksum of the preceding application data for error detection.

 ACK – Acknowledge. When the data is received correctly the ACK slot is set EOF – End of Frame  IFS – Intermission Frame Space. Minimum number of bits separating consecutive messages. It provides the intermission between two frames.  Message frame  There are four different frames which can be used on the bus. Data frames- These are most commonly used frame and used when a node transmits information to any or all other nodes in the system. Remote frames - The purpose of the remote frame is to seek permission for the transmission of data from another node. Error frames – If transmitting or receiving node detects an error, it will immediately abort transmission and send error frame Overload frame-It is similar to error frame but used for providing extra delay between the messages

USB( Universal Serial Bus)

 USB is used for serial transmission and reception between host and serial devices  A bus between the host system and interconnected number of peripheral devices  It provides an expandable, fast, bidirectional, low cost, hot pluggable, serial hardware interface.  Implemented to provide a replacement for legacy ports.  USB Host Applications Connecting - flash memory cards, pen-like memory devices, digital camera, printer, mouse-device, PocketPC, video games, Scanner.  Plug and play: The user simply needs to plug the device on the bus. The host will detect this addition, interrogate the newly inserted device and load the appropriate driver, for plugged in device. Once the use is over the user can simply plug the cable out, the host will detect its absence and automatically unload the driver.  It offers 3 different speeds- low speed: 1.5Mbps -Full speed:12 Mbps -High Speed:480 Mbps

 USB 1.0 specification introduced in 1994

 USB 2.0 specification finalized in 2001

 Became popular due to cost/benefit advantage

 Three generations of USB o USB 1.0 o USB 2.0 o USB 3.0 and WUSB(wireless USB) Host and devices

 It is an asynchronous bus  Master is also known as ‘host’ and slaves are known as ‘devices’.  There can be only one host per bus.  Communication takes place between host and device and no communication is possible between devices.  Host controller and multiple devices are connected in a tree like fashion using hub devices.

Fig: USB Topology

 A hub is device that contains one or more connectors to USB devices along with the hardware to enable communicating with the device. Hubs may be cascaded upto 6 levels and upto 127 devices may be connected to a single host controller.  USB protocol: It is entirely host initiated, so there is only a single logical path-between host and one device. When the host transmits, there are many devices in the system, only the device addressed by the host responds USB Data Transfer Four Types of Data Transfer 1. Interrupt Transfer: It is meant for devices that must receive the host attention periodically. Human interface devices (low speed devices) such as mouse, keyboards, and joysticks are expected to be capable of processing input signals fast enough so that the users do not feel a "lag."

2. Bulk Transfer

Image input devices, printing devices, and storage devices such as printers, scanners, digital cameras, memory card reader/writers, FDD, and DVD recorders are expected to transfer large volumes of data with accuracy (i.e. without loss of data). For example, it is not acceptable for printers to output faulty printouts due to corrupted data.

3. Isochronous Transfer

The devices must be able to transfer a certain amount of data on a periodic basis. Eg: Audio and video devices such as speakers, microphones, telephones, and video conferencing

4. Control Transfer

Bidirectional data transfer which is used for initial configuration of a device by host. Control transfers are used to exchange device details, allocate USB addresses, and configure devices, and are hence used by all devices.

Parallel Communication Standards:

ISA(Industry Standard Architecture)  Ii is a parallel communication standard with8 bit bus architecture

 It is originally introduced in the IBM PC (1981) as an 8 bit expansion slot

 It was later expanded to 16 bits.

 The 16-bit version introduced with the IBM PC  Today, all ISA slots are 16 bit

 It is a very slow speed bus which is ideal for certain slow speed or older peripherals such as plug-in modems, sound cards etc.

 An ISA bus connects only to embedded device, which has an 8086,80186 or 80286 processor.

 EISA (Extended ISA): This architecture support 32 bit buses with much higher data transfer rates . It provides backward compatibility to 8 bit and 16 bit ISA cards.  Micro Channel Architecture is introduced by IBM in 1987 as a replacement for the ISA bus  EISA and MCA have not been successful

PCI (Peripheral Component Interconnect)

 The Peripheral Component Interconnect is an interconnect bus developed by Intel in 1992 which runs at 33 MHz and supports plug-and-play  It allows high speed connection between peripherals(video adapters, drive adapters and network adapters to the chipset, processor and memory), and from the peripherals to the processor.  PCI allows the transfer of data amongst peripherals ,independently  Found on many desktops, but not limited to them, the PCI bus is a 32 bit wide bus capable of transferring at data rates up to 132 M Bytes per second  A 66 MHz, 64-bit version is capable of transfer rates of up to 524 Mbytes/second  The most recent motherboards usually provide 4 or 5 PCI slots.  The PCI bus can be either 32 bits or 64 bits wide.  Information is transferred across the bus at 33 MHz

PCI based System

PCI-X  It is an expansion slot advanced to PCI.  PCI-X is faster version of PCI running at twice the speed of PCI.  Standard PCI supports up to 64 bit at 66 MHz.

 Peripheral Component Interconnect (週邊元件互連)

 Designed as a replacement for the ISA standard.  3 main goals:  to get better performance when transferring data between the computer and its peripherals.  to be as platform independent as possible.  To simplify adding and removing peripherals to the system.  To get better performance  uses a higher clock rate (25 or 33 MHz) than ISA.  To be as platform independent  is used extensively on IA-32, Alpha, PowerPC, SPARC64, and IA-64 systems.  To simplify adding and removing peripherals  supports for auto detection of interface boards. PCI Addressing  Each PCI peripheral is identified by a bus number(16-bits), combined by bus (8), device(5), and function(3).  Using the lspci tool, we can get the information of each PCI peripheral.  BB:DD.F as three values (bus, device, and function)  The hardware circuitry of each peripheral board will know memory locations, I/O ports, and configuration registers.  Memory locations and I/O ports are shared by all the devices on a PCI bus. When you access a memory location, all the devices see the bus cycle at the same time.

 Configuration space exploits geographical addressing(槽位定址法). Configuration transactions address only one slot at a time