Module 2 Serial Communication Standards and Devices Introduction

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Module 2 Serial Communication Standards and Devices Introduction Module 2 Serial Communication Standards and Devices Introduction Serial communication is common method of transmitting data between a computer and a peripheral device. Serial communication is the process of sending data one bit at a time, sequentially, over a single communication line to a receiver. Parallel communication is a method of conveying multiple binary digits (bits) simultaneously in data transmission. Synchronous Transmission: The sender and receiver should have synchronized clocks before data transmission. Asynchronous Transmission does not require a clock but it adds a parity bit to the data before transmission. Simplex, Half-Duplex, and Full-Duplex Communication Links Communication Protocol: A protocol is a standard adopted, which tells the way in which the bits of a frame must be sent from a device to another device or system. The microcontroller can access devices via several serial interfaces. In real time application serial connections are typically used to limit no: of wire/connections required to communicate between the functional modules. UART: Universal Asynchronous Receiver Transmitter UART is a serial communication device that performs parallel to serial data conversion at the transmitter and serial to parallel data conversion at the receiver side. UART is being used in many applications GPS Receivers, Bluetooth Modules, GSM and GPRS Modems, Wireless Communication systems and RFID based systems. Features It is a simple half-duplex, asynchronous, serial protocol Simple communication between two equivalent nodes. Any node can initiate communication. Since connection is half-duplex, the two lanes of communication are completely independent. It is universal since its parameters (format, speed ..) are configurable. It is ‘asynchronous’ since it doesn’t have a clock. Baud Rate: It is the no: of bits transmitted/received per second UART packet format Working of UART: In UART serial communication, the data is transmitted asynchronously. instead of clock signals, UART uses some special bits called start and stop bits. These bits are added to the actual data packet at the beginning and end respectively. These additional bits allow the receiving UART to identify the actual data. Connections for UART UART Characteristics The speed of communication (measured in bauds) is predetermined on both ends. A general rule of thumb is to use 9600 bauds for wired communication. UART implements error-detection in the form of parity bit. Parity Bit •Parity bit is HIGH when number of 1’s in the Data is odd. •Respectively, it is LOW when number of 1’s in the Data is even. HDLC (HIGH- LEVEL Data Link Control) The OSI’s data link protocol A bit-oriented protocol that supports both half –duplex and full duplex communication over point to point & multipoint link. On transmitting side, HDLC receives data from an application, and delivers it to the receiver on the other side of the link On the receiving side, HDLC accepts the data and delivers it to the higher level application layer There are two formats Standard HDLC and Extended HDLC for and 28 and 216 destination devices or systems, respectively. For any HDLC communication session one station is designated primary and the other secondary. A session can use one of the following connection modes: 1. Normal unbalanced: The secondary station responds only to the primary station. 2. Asynchronous: The secondary station can initiate a message 3. Asynchronous balanced : Both stations send and receive over its part of a duplex line. HDLC Frame Structure Flag bits (both opening and closing flags):8 bits( 01111110 or 7E hex) Address bits : 8 bits in Standard HDLC format and 16 bits in extended format Control field: The control field distinguishes between the three different types of frames used in HDLC, namely information, control and unnumbered frames. The first one or two bits of the field determine the type of frame. Information field: The information field does not have a length specified by HDLC. In practice, it normally has a maximum length determined by a particular implementation. Information frames (also known as I-frames) are the only frames that carry information bits which are normally in the form of a fixed-length block of data of several kilobytes in length Frame check sequence: The FCS field contains error-checking bits, normally 16 bit with a provision for increasing this to 32. If the FCS fails, the frame is discarded. Types of Frames in HDLC o Information frames: contain user data o Supervisory frames: flow/error control (ACK/ARQ) o Unnumbered frames: variety of control functions Instruction Frames The first bit of control field is always zero, i.e. the presence of zero at this place indicates that it is I-frame. Bit number 2, 3 & 4 in control field is called N(S) that specifies the sequence number of the frame. Thus it specifies the number of the frame that is currently being sent. Since it is a 3.bit field, only eight sequence numbers are possible 0, 1,2,3,4,5,6, 7 (000 to 111). Bit number 5 in control field is P/F i.e. Poll/Final and is used for these two purposes. It has, meaning only when it is set i.e. when P/F=1. It can represent the following two cases. (i) It means poll when frame is sent by a primary station to secondary (when address field contains the address of receiver). (ii) It means final when frame is sent by secondary to a primary (when the address field contains the address of the sender). Bit number 6, 7, and 8 in control field specifies N(R) i.e. the sequence number of the frame expected in return in two-way communication. Supervisory frames S-frame carries control information, primarily data link layer flow and error controls. It does not contain information field. The first two bits in the control field of S-frame are always 10. Then there is a bit code field that specifies four types of S-frame with combination 00,01, 10, 11 as shown in table :- (i) RR, Receive Ready-used to acknowledge frames when no I-frames are availab1e (ii) REJ Reject-used by the receiver to send a NAK when error has occurred. (iii) RNR Receive Not Ready-used for flow control. (iv) SREJ Selective Reject-indicates to the transmitter that it should retransmit the frame. • There is no N(S) field in control field of S-frame as S-frames do not transmit data. • P/F bit is the fifth bit and serves the same purpose as discussed earlier. • Last three bits in control field indicates N(R) i.e. they correspond to the ACK or NAK value. Unnumbered frame • U-frames are reserved for system management and information carried by them is used for managing the link • Information field in U-frame does not carry user information rather, it carries system management information. • U-frame is identified by the presence of 11 in the first and second bit position in control field. • These frames do not contain N(S) or N(R) in control field. • U-frame contains two code fields, one two hit and other three bit. • These five bits can create upto 32 different U-frames. • .P/F bit in control field has same purpose as discussed earlier. HDLC Operation Initialization: S-frames specify mode and sequence numbers, U-frames acknowledge Data Transfer: I-frames exchange user data, S-frames acknowledge and provide flow/error control Disconnect: U-frames initiate and acknowledge SCI (Serial Connect Interface) SCI is a UART asynchronous mode port SCI is port with Full-duplex mode SCI is programmable for transmission and for reception This interface uses three dedicated pins: transmit dara(TXD), receive data(RXD), and SCI serial clock –SCLK(optional for synchronous communication). It supports industry standard asynchronous bit rates and protocols as well as high speed (upto 5 Mbps for a 40-MHZ clock) synchronous data transmission. The SCI consists of separate transmit and receive sections whose operations can be asynchronous with respect to each other. The Serial Communications Interface (SCI) module is a relatively slow, asynchronous communication port that is widely used to communicate with other embedded systems and devices The SCI configuration allows for a number of options for data transmission and reception. In the simplest configuration, ten bits are involved : a start bit (logical 0), the 8 data bits, and a stop bit (logical 1). An example transmission waveform, is shown below. Serial in and serial out lines baud rate not separately program The signals used in SCI are listed in the figure below SPI (Serial Peripheral Interface) SPI is a Full‐duplex Synchronous communication protocol. It is Fast, easy to use, and simple Common serial interface on many microcontrollers It Supports Single master and Multiple slaves Simple 8-bit exchange between two devices. o Master initiates transfer and generates clock signal o Slave device selected by master One-byte at a time transfer The signals used in SPI are listed in the figure below Fig: single master and single slave SCLK is the serial clock from master. MOSI (Master Out Slave In) is the output from master MISO (Master In Slave Out) is the input to the master. Data is shifted out of the master's MOSI pin and in it's MISO pin Data transfer is initiated by simply writing data to the SPI data register. All data movement is coordinated by SCK. Slave select may or may not be used depending on interfacing device. Device selection as master or slave can be done by applying a signal to input SS pin. When this pin is 0, then the device act as Master. When this pin is 1, then the device act as slave.
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