EiTddChllfEmerging Trends and Challenges of High Density Packaging & 3D IC Integration

Ricky Lee, PhD, FIEEE , FASME , FI nstP Center for Advanced Microsystems Packaging Hong Kong University of Science & Technology Clear Water Bay, Kowloon, Hong Kong

4th Annual Conference of IeMRC Loughborough University, UK 2 September, 2009 50 Years of IC Industry Development

3D-IC SoC

WSI VLSI/ULSI

LSI ICs

Vacuum Tubes

2 Infancy of Transistors and ICs

Point-Contact , 1947 Silicon-based Junction Transistor, 1954 Integrated Circuit (IC), 1958 Bell Labs (William Shockley*, Texas Instruments (Gordon Teal) Texas Instruments (Jack Kilby*) & Walter Brattain*, John Bardeen**) Fairchhild Semiconductor ()

Planar Transistor, 1959 Monolithic Risitor-Transistor Logic, 1961 Metal Oxide Semiconductor, 1968 Fairchild Semicondcutor Fairchild Semiconductor (Robert Noyce) Fairchild Semiconductor (Jean Hoerni) Source: SIA 3 ’s Prediction

“The complexity for minimum component costs has increased at a rate of roughly a factor of two per year ... Certainly over the short term this rate can be expected to continue, if not to increase. Over the longer term, the rate of increase is a bit more uncertailhhhiin, although there is no reason to believe it will not remain nearly constant for at least 10 years. That means by 1975, the number of components per integrated circuit for minimum cost will be 65,,g000. I believe that such a large circuit can be built on a single wafer” "Cramming more components onto integrated circuits" Electronics Magazine, 19 April 1965

Source: Museum 4 Moore’s Law for ICs

# of Transistors on an IC will be doubled every 18-24 months

Source: Wikipedia 5 More Moore (MM) and More than Moore (MtM)

Source: ITRS2007 6 Nanotechnology for MM

Source: Intel 7 Syygstem Integration for MtM

¾System-on-Chip ¾Multi-Chip Module (Multi-Chip Package)

¾System-on-Board ¾Package-in-Package

¾System-in-Package ¾Package-on-Package

¾Syystem-on-Package 8 Evolution of Packaging Efficiency

3DP

9 Current Implementations of 3DP

Various Web & Personal Sources 10 Emerging 3DP Trends

¾ Flip chips on silicon chip carrier with TSVs as itinterposer. (C2S) ¾ Stack multiple flip chips with TSVs as vertical itinterconnecti on. (C2C) ¾ Embedded wafer level packaging. (C2W) ¾ Wafer bonding for 3D integration. (W2W)

Various Web & Personal Sources 11 Scoppge of TSV Technologies TSV Formation - Laser Drilling -Deep Reactive Ion Etching (()DRIE) Interfacial Layers - IltiInsulation - Barrier/Adhesion - Seed TSV Plugging - Copper - Tungsten - PolySi

12 TSV byyg Laser Drilling

Punching Trepan Spiral

25 µm 29 µm 61 µm

8µm 52 µm 11 µm

Direct Punching Trepanning Spiraling (0.8W, 200 Pulses) (0.8W, 100 Repetitions) (0.8W, 50 Repetitions)

13 TSV by Deep Reactive Ion Etching

The TSVs are formed by DRIE on a silicon wafer with silicon oxide as the mask .

The DRIE machine uses SF6 to etch the silicon and C4F8 to coat a passivation layer to protect the sidewall of the etched part during the etchinggp process.

14 Cross-Section of DRIE TSVs

65 µm

15 Interfacial Multilayer Structure of TSV

Seed Layer (Cu)

Silicon Adhesion/Barrier Layer (TaN or TiW) Substrate

Insulation Layer (SiO2)

16 SEM Microggpraph of Interfacial Multilayer Structure

Ti Ti

17 TSV Plugging by Copper Plating

Over-plated Cu

TSV Plugged with Cu

Top Side of Wafer after Copper Plating

Cross Section Inspection

Bottom Side of Wafer after Copper Plating 18 Electroplating Basics

™ Subconformal ¾ Subconformal plating leads to the formation of void even in the straight- walled features.

™ Conformal ¾ In conformal plating, a deposit of equal thickness at all points of a feature leads to the creation of seam. Typical of PCB and bump processes.

™ Superconformal ¾ Copper growth starts at the bottom of the via and rapidly progresses upwards with the aid of special plating additives that possesses different adsorption preferences on features. Required for sub-micron feature filling. 19 Functions of Plating Chemicals

Copper Sulphate Basic plating solution Sulphuric acid ¾ Provide the required copper ions and acid for plating.

Chloride ions (Cl-) Suppressor ¾ Hinders the deposition of copper at the corners of the via. Polyethylene glycol (PEG)

Bis(3-sulfopropyl)disulfide (SPS) Accelerator ¾ Accelerate the deposition of copper at low current ditidensity region.

Janus Green B (JGB) Leveler ¾ A weak suppressor which will flatten the copper deposition of copper on top surface of the wafer.

TPPA Wetting agent SYS301 ¾ Provides extra wettability for copper deposition at bottom of the via.

20 Platinggp Solution Optimization

21 Range of Chemicals

22 HKUST 4-Stack Flip Chip Prototype with TSV

23 Other Issues with 3D Flippp Chip Stacking

¾ Re-distribution and Bumppging ¾ Wafer Thinning and Handling ¾ Dici ng/St /Stacki ng or WfWafer BdiBonding ¾ Underfill Encapsulation (?)

ICs TSVs

Substrate

24 Process Flow Options for TSVs

25 3D TSV Interconnect Trends

Source: Yole Development 26 Industrial TSV Module Deployment (II)

The new CSCM micro-camera modules will be the first produced with TCV technology, which reduces wire bonding a substrate area by mounting comppyonents directly on the wafer and runnin g electrodes through the vias on the circuit board, securing them with balls of solders on the substrate. (50 μm dia., 70 μm deep)

Source: Toshiba 27 Industrial TSV Module Deployment (I)

28 Samsung TSV and Stacking Roadmap

Source: Samsung 29 Nokia 3D Packaging Roadmap

Source: Nokia 30 Semiconductor 3D Equipment & Materials Consortium

The mission of the international consortium EMC3D is to rapidly develop a cost-effective and manufacturable TSV for 3D chip stacking and MEMS integration. Technology support for the consortium goals is from associate members Fraunhofer IZM, SAIT (Samsung Advanced Institute of Technology), KAIST (Korea Advanced Institute of Science and Technology), TAMU (Texas A&M University), CEA LETI, and NXP. Material members include Rohm and Haas, Enthone, Brewer Science, and AZ Electronic Materials with wafer service support from WRS Materials. Equipment companies are Datacon, EV Group, Semitool, and XSiL. Source: EMC3D 31 Technical Roadmap of EMC3D

Source: EMC3D 32 ITRS System-in-Packaggpe Roadmap

Source: ITRS2007 33 Importance of Design Tools

Source: R3Logic 34 HKUST Campus at Clear Water Bay, HK

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