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Timing Analysis for Time-Predictable Architectures Amine Naji

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Timing Analysis for Time-Predictable Architectures Amine Naji Timing analysis for time-predictable architectures Amine Naji To cite this version: Amine Naji. Timing analysis for time-predictable architectures. Networking and Internet Architecture [cs.NI]. Sorbonne Université, 2019. English. NNT : 2019SORUS282. tel-03143979 HAL Id: tel-03143979 https://tel.archives-ouvertes.fr/tel-03143979 Submitted on 17 Feb 2021 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. Sorbonne Université Ecole doctorale Informatique, Télécommunication et Électronique de Paris Timing Analysis for Time-Predictable Architectures Par Amine Naji Thèse de doctorat d’Informatique Dirigée par Albert Cohen Présentée et soutenue publiquement le 12 juin 2019 Devant un jury composé de : Rapporteurs Mme. Isabelle Puaut Professor, University of Rennes I M. Jens Knoop Professor, Vienna University of Technology Examinateurs Mme. Karine Heydemann Associate Professor, UPMC (Paris 6) M. Albert Cohen Senior Research Scientist, Google M. Florian Brandner Associate Professor, Télécom ParisTech M. Mathieu Jan Research Engineer, CEA List Contents 1 Introduction 1 1 Toward High-Performance Safety-Critical Systems . .1 2 Real-Time Systems . .4 2.1 Definition and Key Properties . .4 2.2 Embedded Systems . .6 2.3 Real-Time Tasks . .6 2.4 System Failure . .7 3 Deriving Timing Guarantees . .7 3.1 Schedulability Analysis . .8 3.2 Timing Analysis . .8 4 Meaning of Performance . 10 4.1 Performance in Standard Computer Systems . 10 4.2 Worst-Case Performance . 13 5 Issues with Standard Architectures . 14 6 Predictable Architectures as an Alternative . 16 6.1 Notable Efforts and Architectures . 16 6.2 Comparing Architectures . 19 7 Contributions . 22 2 Patmos, a Time-Predictable Processor 26 1 Overview and Design Approach . 26 2 Patmos Computer Architecture . 28 2.1 Pipeline and Register File . 28 2.2 Instruction Set Architecture (ISA) . 29 2.3 Predication . 32 2.4 Memory Hierarchy . 32 2.5 Multi-Core and Bus Arbitration Policy . 37 3 Compiler Support . 38 3.1 Toolchain Overview . 39 3.2 Support for Patmos Features . 39 3 3 Static WCET Analysis Framework 43 1 The Analysis Work Flow . 43 2 Basic Concepts for Program Static Analysis . 46 2.1 Control-Flow Graph . 46 2.2 Loops . 49 2.3 Inter-procedural CFG and Call Graph . 51 3 Data-Flow Analysis Frameworks . 52 3.1 Abstract Domain . 53 3.2 Transfer Functions . 55 3.3 Forming DFA equations . 56 3.4 Solving DFA equations . 58 3.5 Intra-procedural and Inter-procedural DFA . 60 4 Standard Cache Analyses . 61 4.1 Goal and Challenges . 61 4.2 Cache Analysis Based On Access Classification . 63 4.3 Improving Precision in Loops . 66 4.4 Preemption Costs . 67 5 Stack Cache Analyses . 68 5.1 Inter-procedural DFA-based Analysis . 69 5.2 Standard Stack Cache Analysis . 70 6 Method Cache Analysis . 71 7 WCET Analysis with Predication . 73 8 Existing Static WCET Analysis Tools . 73 9 Conclusion . 76 4 Analysis of Predicated Programs in Odyssey – a Fully-Integrated WCET Analysis Tool 78 1 Outline . 78 2 Odyssey: a Fully-Integrated WCET Analysis Tool for Patmos . 79 3 Handling Predication: Motivating Example . 82 4 Control-Flow Unfolding . 83 5 Experiments . 87 6 Conclusion . 88 5 Comparing the Precision of Stack Cache Occupancy Analyses 89 1 Outline . 89 2 Cache Occupancy Analyses . 90 2.1 Standard Stack Cache Analysis . 90 2.2 Inter-procedural Data-flow Analysis . 92 3 Experiments . 95 3.1 Discussion . 96 4 Conclusion . 98 6 Analysis of Preemption Costs for the Stack Cache 99 1 Outline . 99 2 Analysis of Preemption Delays: Motivating Example . 100 3 Context Saving Analysis . 102 4 Context Restoring Analysis . 105 4.1 Local Restore Analyses . 106 4 4.2 Global Ensure Analysis . 109 4.3 Global Reserve Analysis . 111 4.4 Context Restore Costs . 114 5 Computational Complexity . 115 6 Discussion . 117 7 Experiments . 117 7.1 Context Restoring Analysis . 117 7.2 Context Saving Analysis . 119 8 Conclusion . 120 7 Preemption Mechanisms for the Stack Cache 121 1 Outline . 121 2 Preemption Mechanisms . 122 3 Handling Preemption Schemes . 124 3.1 Fixed Preemption Schemes . 124 3.2 Non-Fixed Preemption Schemes . 125 4 Experiments . 127 4.1 Hardware Implementation . 131 5 Conclusion . 132 8 Eager Stack Cache Memory Transfers – A Prefetching-Like Technique for the Stack Cache 133 1 Outline . 133 2 Eager Memory Transfers . 134 2.1 Eager Fill . 136 2.2 Eager Spill . 137 3 Spill/Fill Arbitration . 138 4 Experiments . 138 5 Conclusion . 141 9 Conclusion and Future Work 142 1 Contributions . 142 2 Extension and Future Work . 144 2.1 Virtual Stack Caches . 144 2.2 Unused TDM slots . 145 2.3 Method Cache . 146 5 List of Figures 1.1 Timing characteristics of task τi. Ti is the period of activation, Ci is the computation time, and Di is the deadline relative to the activation date. .6 1.2 Distribution of execution times. The actual WCET has to be upper- bounded by the WCET estimate provided by the timing analysis. The precision of the analysis determines the tightness of to the actual WCET. .9 2.1 Simplified representation of Patmos pipeline. Taken from Patmos Handbook [7]. 29 2.2 Portion of a program in Patmos assembly language and its correspond- ing machine code. Each line in the machine code corresponds to a line in the assembly code. 30 2.3 Example of a program and the stack cache state at particular points. 35 2.4 Patmos multi-core platform. 38 2.5 The compilation toolchain. 39 3.1 General WCET analysis work flow. 44 3.2 Portion of a program in Patmos assembly language and its correspond- ing machine code. Each line in the machine code corresponds to a line in the assembly code. 48 3.3 Example of a program in the Patmos assembly language and its corresponding CFG demonstrating the use of a single loop. 50 3.4 Example of an ICFG of a program and its corresponding CG. 52 3.5 Examples of some domains . 55 3.6 The transfer function transforms the input information. 56 3.7 Direction of the information flow in forward and backward analyses. Dashed arrows represent the flow of information, while the regular arrows represent the flow of execution. 57 3.8 Example of liveness analysis. Taken from [3]. 59 3.9 The evolution of the (actual) cache state depending on memory ac- cesses. Assuming 2-way set-associative cache with LRU replacement policy. The memory blocks ’a’, ’b’ and ’d’ map to the cache set s1, whereas ’c’ and ’e’ map to s2....................... 61 6 3.10 Example.
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