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A Java Processor Architecture for Embedded Real-Time Systems Downloaded from orbit.dtu.dk on: Oct 01, 2021 A Java Processor Architecture for Embedded Real-Time Systems Schoeberl, Martin Published in: Journal of Systems Architecture Link to article, DOI: 10.1016/j.sysarc.2007.06.001 Publication date: 2008 Document Version Early version, also known as pre-print Link back to DTU Orbit Citation (APA): Schoeberl, M. (2008). A Java Processor Architecture for Embedded Real-Time Systems. Journal of Systems Architecture, 54(1-2), 265-286. https://doi.org/10.1016/j.sysarc.2007.06.001 General rights Copyright and moral rights for the publications made accessible in the public portal are retained by the authors and/or other copyright owners and it is a condition of accessing publications that users recognise and abide by the legal requirements associated with these rights. Users may download and print one copy of any publication from the public portal for the purpose of private study or research. You may not further distribute the material or use it for any profit-making activity or commercial gain You may freely distribute the URL identifying the publication in the public portal If you believe that this document breaches copyright please contact us providing details, and we will remove access to the work immediately and investigate your claim. A Java Processor Architecture for Embedded Real-Time Systems Martin Schoeberl Institute of Computer Engineering, Vienna University of Technology, Austria Abstract Architectural advancements in modern processor designs increase average performance with features such as pipelines, caches, branch prediction, and out-of-order execution. However, these features complicate worst-case execution time analysis and lead to very conservative estimates. JOP (Java Optimized Processor) tackles this problem from the architectural perspective – by introducing a processor architecture in which simpler and more accurate WCET analysis is more important than average case performance. This paper presents a Java processor designed for time-predictable execution of real-time tasks. JOP is the implementation of the Java virtual machine in hardware. JOP is intended for applications in embedded real-time systems and the primary implementation technology is in a field programmable gate array. This paper demonstrates that a hardware implementation of the Java virtual machine results in a small design for resource-constrained devices. Key words: Real-time system; Time predictable architecture; Java processor 1. Introduction Due to compilation during runtime, execution times are practically not predictable 1 . Compared to software development for desktop sys- This paper introduces the concept of a Java processor tems, current software design practice for embedded [51] for embedded real-time systems, in particular the real-time systems is still archaic. C/C++ and even as- design of a small processor for resource-constrained de- sembly language are used on top of a small real-time vices with time-predictable execution of Java programs. operating system. Many of the benefits of Java, such as This Java processor is called JOP – which stands for safe object references, the notion of concurrency as a Java Optimized Processor –, based on the assumption first-class language construct, and its portability, have that a full native implementation of all Java bytecode the potential to make embedded systems much safer instructions [30] is not a useful approach. and simpler to program. However, Java technology is Worst-case execution time (WCET) estimates of seldom used in embedded real-time systems, due to the tasks are essential for designing and verifying real-time lack of acceptable real-time performance. systems. Static WCET analysis is necessary for hard Traditional implementations of the Java virtual ma- real-time systems. In order to obtain a low WCET chine (JVM) as interpreter or just-in-time compiler are value, a good processor model is necessary. Tradition- not practical. An interpreting virtual machine is too ally, only simple processors can be analyzed using slow and therefore waste of processor resources. Just-in- practical WCET boundaries. Architectural advance- time compilation has several disadvantages for embed- ded systems, notably that a compiler (with the intrinsic 1 One could add the compilation time of a method to the WCET memory overhead) is necessary on the target system. of that method. However, in that case we need a WCET analyzable compiler and the WCET gets impractical high. Preprint submitted to Elsevier 12 June 2007 ments in modern processor designs tend to abide by Even simple processors can contain an instruc- the rule: ‘Make the average case as fast as possible’. tion prefetch buffer that prohibits exact WCET This is orthogonal to ‘Minimize the worst case’ and values. The design of the method cache and the has the effect of complicating WCET analysis. This translation unit avoids the variable latency of a paper tackles this problem from the architectural per- prefetch buffer. spective – by introducing a processor architecture in (xi) Good average case performance compared to which simpler and more accurate WCET analysis is other non real-time Java processors. more important than average case performance. (xii) Avoidance of hard to analyze architectural fea- JOP is designed from ground up with time predictable tures results in a very small design. Therefore an execution of Java bytecode as major design goal. All available real estate can be used for a chip multi- function units, and especially the interaction between processor solution. them, are carefully designed to avoid any time depen- In this paper, we will present the architecture of the dency between bytecodes. The architectural highlights real-time Java processor and the evaluation results for are: JOP, with respect to WCET, size and performance. We (i) Dynamic translation of the CISC Java byte- will show that the execution time of Java bytecodes can codes to a RISC, stack based instruction set (the be exactly predicted in terms of the number of clock microcode) that can be executed in a 3 stage cycles. We will also evaluate the general performance pipeline. of JOP in relation to other embedded Java systems. Al- (ii) The translation takes exactly one cycle per byte- though JOP is intended as a processor with a low WCET code and is therefore pipelined. Compared to for all operations, its general performance is still impor- other forms of dynamic code translation the tant. We will see that a real-time processor architecture proposed translation does not add any variable does not need to be slow. latency to the execution time and is therefore In the following section, related work on real-time time predictable. Java, Java processors, and issues with the low-level (iii) Interrupts are inserted in the translation stage as WCET analysis for standard processors is presented. In special bytecodes and are transparent to the mi- Section 3 a brief overview of the architecture of JOP crocode pipeline. is given, followed by a more detailed description of the (iv) The short pipeline (4 stages) results in short microcode. In Section 4 it is shown that our objective conditional branch delays and a hard to analyze of providing an easy target for WCET analysis has been branch prediction logic or branch target buffer achieved. Section 5 compares JOP’s resource usage with can be avoided. other soft-core processors. In the Section 6, a number (v) Simple execution stage with the two topmost of different solutions for embedded Java are compared stack elements as discrete registers. No write at the bytecode level and at the application level. back stage or forwarding logic is needed. (vi) Constant execution time (one cycle) for all mi- crocode instructions. No stalls in the microcode 2. Related Work pipeline. Loads and stores of object fields are han- dled explicitly. In this section we present arguments for Java in real- (vii) No time dependencies between bytecodes result time systems, various Java processors from industry and in a simple processor model for the low-level academia, and an overview of issues in the low-level WCET analysis. WCET analysis that can be avoided by the proposed (viii) Time predictable instruction cache that caches processor design. whole methods. Only invoke and return instruc- tion can result in a cache miss. All other instruc- tions are guaranteed cache hits. 2.1. Real-Time Java (ix) Time predictable data cache for local variables and the operand stack. Access to local variables Java is a strongly typed, object oriented language, is a guaranteed hit and no pipeline stall can hap- with safe references, and array bounds checking. Java pen. Stack cache fill and spill is under microcode shares those features with Ada, the main language for control and analyzable. safety critical real-time systems. It is even possible, and (x) No prefetch buffers or store buffers that can intro- has been done [60,8], to compile Ada 95 for the JVM. In duce unbound time dependencies of instructions. contrast to Ada, Java has a large user and open-source 2 code base. In [64] it is argued that Java will become the Table 1 JOP and various Java processors better technology for real-time systems. Target Size Speed The object references replace error-prone C/C++ technology Logic Memory (MHz) style pointers. Type checking is enforced by the com- piler and performed at runtime. Those features greatly JOP Altera, Xilinx FPGA 2050 LCs 3 KB 100 help to avoid program errors. Therefore Java is an at- picoJava [58,59] No realization 128 Kgates 38 KB aJile [1,19] ASIC 0.25µ 25 Kgates 48 KB 100 tractive choice for safety critical and real-time systems Cjip [18,25] ASIC 0.35µ 70 Kgates 55 KB 80 [56,26]. Furthermore, threads and synchronization, Moon [62,63] Altera FPGA 3660 LCs 4 KB common idioms in real-time programming, are part of Lightfoot [9] Xilinx FPGA 3400 LCs 4 KB 40 the language.
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