®MOTOFlOLA MVME120/D2

MVME120, MVME121, MVME122, MVME123 VMEbus Microprocessor Module User's Manual

ICR

QUALITY • PEOPLE • PERFORMANCE (f!jMOTOROLA

MVME120jD2 JUNE 1985

MVMEI20, MVMEI21, MVMEI22, MVME123 VMEbus MICROPROCESSOR MODULE USER'S MANUAL

The information in this document has been carefully checked and is believed to be entirely reliable. However, no responsibility is assumed for inaccuracies. Furthermore, Motorola reserves the right to make changes to any products herein to improve reliability, function, or design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights or the rights of others. VERSAdos is a trademark of Motorola Inc.

WARNING THIS EQUIPMENT GENERATES, USES, AND CAN RADIATE RADIO FREQUENCY ENERGY AND IF NOT INSTALLED AND USED IN ACCORDANCE WITH THE INSTRUCTIONS MANUAL, MAY CAUSE INTERFERENCE TO RADIO COMMUNICATIONS. IT HAS BEEN TESTED AND FOUND TO COMPLY WITH THE LIMITS FOR A CLASS A COMPUTING DEVICE PURSUANT TO SUBPART J OF PART 15 OF FCC RULES, WHICH ARE DESIGNED TO PROVIDE REASONABLE PROTECTION AGAINST SUCH INTERFERENCE WHEN OPERATED IN A COMMERCIAL ENVIRONMENT. OPERATION OF THIS EQUIPMENT IN A RESIDENTIAL AREA IS LIKELY TO CAUSE INTERFERENCE IN WHICH CASE THE USER, AT HIS OWN EXPENSE, WILL BE REQUIRED TO TAKE WHATEVER MEASURES NECESSARY TO CORRECT THE INTERFERENCE.

Second Edition Copyright 1985 by Motorola Inc. First Edition September 1984

MICROSYSTEMS SAFETY SUMMARY SAFETY DEPENDS ON YOU

The following general safety precautions must be observed during all phases of operation, service, and repair of this equipment. Failure to comply with these precautions or with specific warnings elsewhere in this manual violates safety standards of design, manufacture, and intended use of the equipment. Motorola Inc. assumes no liability for the customer's failure to comply with these requirements. The safety precautions listed below represent warnings of certain dangers of which we are aware. You, as the user of the product, should follow these warnings and all other safety precautions necessary for the safe operation of the equipment in your operating environment.

GROUND THE INSTRUMENT. To minimize shock hazard, the equipment chassis and enclosure must be connected to an electrical ground. The equipment is supplied with a three-conductor ac power cable. The power cable must either be plugged into an approved th ree-contact electrical outlet or used with a three-contact to two-contact adapter, with the grounding wire (green) firmly connected to an electrical ground (safety ground) at the power outlet. The power jack and mating plug of the power cable meet International Electrotechnical Commission (IEC) safety standards.

DO NOT OPERATE IN AN EXPLOSIVE ATMOSPHERE. Do not operate the equipment in the presence of flammable gases or fumes. Operation of any electrical equipment in such an environment constitutes a definite safety hazard.

KEEP AWAY FROM LIVE CIRCUITS. Operating personnel must not remove equipment covers. Only Factory Authorized Service Personnel or other qualified maintenance personnel may remove equipment covers for internal subassembly or component replacement or any internal adjustment. Do not replace components with power cable connected. Under certai n conditions, dangerous voltages may exist even with the power cable removed. To avoid injuries, always disconnect power and discharge circuits before touching them.

DO NOT SERVICE OR ADJUST ALONE. Do not attempt internal service or adjustment unless another person, capable of rendering first aid and resuscitation, is present.

USE CAUTION WHEN EXPOSING OR HANDLING THE CRT. Breakage of the Cathode-Ray Tube (CRT) causes a high-velocity scattering of glass fragments (implo­ sion). To prevent CRT implosion, avoid rough handling or jarring of the equipment. Handling of the CRT should be done only by qualified maintenance personnel using approved safety mask and gloves.

DO NOT SUBSTITUTE PARTS OR MODIFY EQUIPMENT. Because of the danger of introducing additional hazards, do not install substitute parts or perform any unauthorized modification of the equipment. Contact Motorola Microsystems Warranty and Repair for service and repair to ensure that safety features are maintained.

DANGEROUS PROCEDURE WARNINGS. Warnings, such as the example below, precede potentially dangerous procedures throughout this manual. Instructions contained in the warnings must be followed. You should also employ all other safety precautions which you deem necessary for the operation of the equipment in your operating environment. WARNING

Dangerous voltages, capable of causing death, are present in this equipment. Use extreme caution when handling, testing, and adjusting. ® MOTOROLA

PREFACE

Unless otherwise specified, all address references are in hexadecimal throughout this manual.

An asterisk (*) following the signal name for signals which are level significant denotes that the signal is true or valid when the signal is low.

An asterisk (*) following the signal name for signals which are edge significant denotes that the actions initiated by that signal occur on a high to low transition.

MICROSYSTEMS

® MOTOROL.A

TABLE OF CONTENTS

CHAPTER 1 GENERAL INFORMATION 1.1 INTRODUCTION ...... 1 1.2 FEATURES ...... 1 1.3 SPECIFICATIONS...... 3 1.4 GENERAL DESCRIPTION .... ,...... 4 1.5 MVME120 FAMILY CONFIGURATIONS ...... 4 1. 6 RELATED DOCUMENTATION ...... 4

CHAPTER 2 HARDWARE PREPARATION AND INSTALLATION INSTRUCTIONS 2.1 INTRODUCTION ...... 5 2.2 UNPACKING INSTRUCTIONS ...... 5 2.3 HARDWARE PREPARATION ...... 5 2.3.1 ACFAIL*/SYSFAIL* Select Header (J2) ...... 7 2.3.2 VMEbus Request Level Select Headers (J3, J4) ...... 8 2.3.3 ABORT Switch Disable Select Header (J5) ...... 9 2.3.4 RESET Switch Disable Select Header (J6) ...... 9 2.3.5 VMEbus Interrupt Connection Select Header (J7) ..... 10 2.3.6 ROM/EPROM Device Configuration Select Header (J8) .. 10 2.3.7 Cache Configuration Select Headers (J9, J17) ...... 14 2.3.8 MSR Bit 1 Source Select Header (J20) ...... 15 2.3.9 MSR Bit 0 Source Select Header (J21) ...... 16 2.3.10 ROM Access Time Select Header (J22) ...... 17 2.3.11 Reset Vector Fetch Mode Select Header (J24) ...... 17 2.3.12 Local Time-out Select Header (J25) ...... 19 2.3.13 RAM Dual Port Address Select PAL (U28) ...... 19 2.3.13.1 .Factory Configured RAM Dual Port Base Address .... 19 2.3.13.2 Changi ng U28 ...... 21 2.4 INSTALLATION ...... 21 2.4.1 Module Installation ...... 21 2.4.2 Terminal Connection ...... 22

CHAPTER 3 OPERATING INSTRUCTIONS 3.1 INTRODUCTION ...... 23 3.2 CONTROLS AND INDICATORS ...... •...... 23 3.2.1 RESET Swi tch ...... 23 3.2.2 ABORT Swi tch ...... " ... " ~ ...... 23 3.2.3 MODE Swi tch ...... 23 3.2.4 FAIL Indicator ...... 23 3.2.5 HALT Indicator ...... 24 3.2.6 RUN Indicator ...... 24 3.3 MPU MODULE MEMORYMAP ...... 25 3.3.1 MPU Module Memory Map as Viewed from the VMEbus .... 28

MICROSYSTEMS ® MOTOROLA

TABLE OF CONTENTS (cont'd)

CHAPTER 4 FUNCTIONAL DESCRIPTION 4.1 INTRODUCTION ...... 29 4.2 GENERAL DESCRIPTION ...... 29 4.3 BLOCK DIAGRAM DESCRIPTION ...... 30 4.3.1 MPU ...... 30 4.3.2 MMU ...... 30 4.3.3 Cache ...... 31 4.3.3.1 Cache Organization...... 31 4.3.3.2 Cache Operat ion ...... 33 4.3.4 RAM ...... •...... ••.••...... •..•...•... 37 4.3.4.1 Refresh ...... 38 4.3.4.2 Local Accesses ...... 38 4.3.4.3 Accesses From The VMEbus ...... 38 4.3.5 Multi-Port Controller ...... 38 4.3.6 Bus Requester ...... 39 4.3.7 Interrupt Handl er ...... 39 4.3.7.1 VMEbus Interrupts .~ ...... 39 4.3.7.2 ABORT Switch Interrupts ...... 39 4.3.7.3 MC68901 Interrupts ...... 40 4.3.7;4 Interrupt Source and Vectors ...... 40 4.3.7.5 Enabling Interrupts ...... 41 4.3.8 VMEbus Interface ...... 41 4.3.9 I/O and Control ...... 42 4.3.9.1 Module Status ...... ~ ...... 43 4.3.9.2 Module Control Register ...... 44 4.3.9.3 Timers ...... 45 4.3.10 ROM ...... 46 4.3.11 Source of Bus Error Except ions ...... 46 4.3.11.1 VMEbus BERR ...... 46 4.3.11.2 Onboard Parity Error ...... 47 4.3.11.3 Dual Port Lock on TAS Error ...... 47 4.3.11.4 MMU Faul t ...... 47 4.3.11.5 Local Bus Time-out ...... •...... 47

CHAPTER 5 SUPPORT INFORMATION 5.1 INTRODUCTION ...... •...... 51 5.2 INTERCONNECT SIGNALS ...... 51 5.2.1 Connector PI Interconnect Signals ...... 51 5.2.2 Terminal Port Connector Jl Interconnect Signals ..... 56 5.3 PARTS LIST ...... 57

APPENDIX A RS-232C INTERCONNECTIONS 95 APPENDIX B PROGRAMMABLE ARRAY LOGIC 101 INDEX ...... 115

i i MICROSYSTEMS @MOTOROLA

TABLE OF CONTENTS (cont'd)

LIST OF ILLUSTRATIONS

FIGURE I-I. Typical MPU Module...... 2 2-I. MPU Module Option Locations ...... 6 4-I. MPU Module Block Diagram ...... 49 5-I. MPU Module Parts Location ...... 63 5-2. MPU Module Schematic Diagram ...... 65

LIST OF TABLES

TABLE I-I. MPU Module Specifications ...... 3 3-I. Interpretation of Front Panel Indicators ...... 24 4-I. Modul e Status ...... 43 5-I. Connector PI Interconnect Signals ...... 51 5-2. Connector Jl Interconnect Signals ...... 56 5-3. MPU Module Parts List ...... 57

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THIS PAGE INTENTIONALLY LEFT BLANK.

iv MICROS YS TEMS GENERAL INFORMATION ([!jMOTOROLA

CHAPTER 1 I GENERAL INFORMATION

1.1 INTRODUCTION This manual provides general information, preparation for use and installation instructions, operating instructions, functional description, and support information for the MVMEI20, MVMEI21, MVMEI22, and MVME123 VMEbus Microprocessor Modules (hereinafter referred to as MPU module). A typical MPU module is shown in Figure 1-1.

1. 2 FEATURES The features of the MPU module include: MC68010 MPU MC68451 MMU (optional) 4Kb logical instruction cache (optional) Two, 28-pin ROM/EPROM sockets Onboard dual-port RAM with byte parity Interrupt handler Status and control registers Programmable timer RS-232C serial debug port Bus requester A24, 016 VMEbus interface Local RESET switch Local software ABORT switch Mode switch FAIL indicator HALT indicator RUN indicator

1 MICROSYSTEMS ®MOTOROLA GENERAL INFORMATION I

r- n:l U

...... I

2 MICROSYSTEMS @MOTOROLA GENERAL INFORMATION

1.3 SPECIFICATIONS I The MPU module specifications are identified in Table 1-1.

TABLE 1-1. MPU Module Specifications ======CHARACTERISTICS SPECIFICATIONS ======Microprocessor MC68010 Clock signal 12.5 MHz (or 10.0 MHz) Memory size RAM 128Kb/512Kb EPROM/ROM Two sockets for user supplied 4K x 8, 8K x 8, 16K x 8, 32K x 8, or 64K x 8 devices Interrupt handler All onboard plus seven VMEbus interrupts User input/output signals RS-232C serial debug port (terminal only) Temperature Operating o degrees C to 50 degrees C (forced air is required)

Storage -40 degrees to 85 degrees C Relative humidity 0% to 90% (noncondensing) Physical characteristics Width x height 7.40 in. (188 mm) x 10.20 in. (261 mm) Thickness o. 83 in. ( 21 mm) Power requirements +5 Vdc typical current maximum current 120 4.2 A 4.65 A 121 4.0 A 4.45 A 122 3.2 A 3.55 A 123 4.3 A 4.65 A -12 Vdc @ 12 rnA (typical), 14 rnA (maximum) +12 Vdc @ 17 rnA (typical), 20 rnA (maximum) ======

3 MICROSYSTEMS GENERAL INFORMATION ®MOTOROLA

I 1.4 GENERAL DESCRIPTION The MPU, module is a high performance, VMEbus, microprocessor module that offers a solution for high speed data processing, management, and control applications. The module contains an MC68010 MPU, MC68451 MMU, logical instruction cache, a serial debug terminal port, programmable tick timer, private ROM, and a large dynamic dual port RAM that may be loaded externally via the VMEbus. The MPU module, when used with a system controller module (such as the MVME050 system controller or the MVMEIIO CPU module), satisfies system requirements ranging from simple, high speed single processor applications to complex multiprocessor system architectures.

1.5 MVME120 FAMILY CONFIGURATIONS Four configurations are available for the MVME120 Family of Microprocessor Modules. The configurations are listed below: MVME120 10 MHz MC68010, 128K dynamic RAM, cache, MMU MVME121 10 MHz MC68010, 512K dynamic RAM, cache, MMU MVMEl22 12.5 MHz MC68010, 128K dynamic RAM, no cache, no MMU MVMEl23 12.5 MHz MC68010, 512K dynamic RAM, cache, no MMU

The MC68451 MMU does not function at 12.5 MHz.

1.6 RELATED DOCUMENTATION The following publications may provide additional helpful information. If not shipped with this product, they may be obtained from Motorola Literature Distribution Center, 616 West 24th Street, Tempe, Arizona 85282; telephone (602) 994-6561.

======MOTOROLA DOCUMENT TITLE PUBLICATION NUMBER ======Data Book MC68901 MVMEbus Specification Manual MVMEBS ======

4 MICROSYSTEMS HARDWARE PREPARATION @MOTOROLA

CHAPTER 2 HARDWARE PREPARATION AND INSTALLATION INSTRUCTIONS

2.1 INTRODUCTION I This chapter provides unpacking instructions, hardware preparation, and installation instructions for the MPU module.

2.2 UNPACKING INSTRUCTIONS

If the shipping carton is damaged upon receipt, request carrier's agent be present during unpacking and inspection of equipment.

Unpack equipment from shipping carton. Refer to packing list and verify that all items are present. Save packing material for storing and reshipping of equipment.

2.3 HARDWARE PREPARATION For reliable operation, forced air cooling should be used. The cooling should be enough to maintain the temperature at the back of the MC68010 case below 80 degrees centigrade. To select the desired configuration and ensure proper operation of the MPU module, certain modifications may be made before installation. These modifications are made through jumper or wire-wrap arrangements on the headers. Figure 2-1 illustrates the location of the headers and connectors on the MPU module. The MPU module has been factory tested and is shipped with factory-installed jumper configurations that are also shown in Figure 2-1. The MPU module is operational with the factory-installed jumpers. It is necessary to make changes in the jumper arrangements for the following cond it ions:

a. ACFAIL*/SYSFAIL* select (J2) b. VMEbus request level select (J3,J4) c. ABORT switch disable select (J5) d. RESET switch disable select (J6)

5 MICROSYSTEMS ..

P1 @ ! J7 0 zO J4 ~ 160015 "~"0-0 0-0~ a Z 0-0 0-0 "0"280 1 0-0 0-0 12 00 11 20-01 ~z 00 ~ 00 00 ~ J3 5 1 2 0-01 88 2 001 Igg z) J25 10-00) J2 6 2 3 1

J20 J21 ~~ 00 8~~7 00 2 001 J22

3 1 J1 J910 0-0) ~3 LQJ1 J17

FIGURE 2-1. MPU Module Option locations @MOTOROLA HARDWARE PREPARATION

e. VMEbus interrupt connection select (J7) f. ROM/EPROM device configuration select (J8) g. Cache configuration select (J9, Jl7) h. SWI source select (J20) I i. SW2 source select (J21) j. ROM access time select (J22) k. Reset vector fetch mode select (J24) 1. Local time-out select (J25)

2.3.1 ACFAIL*/SYSFAIl* Select Header (J2) Bit 7 of the Module Status Register (MSR) can be configured to monitor either the Alternating Current Failure (ACFAIL*) signal on the VMEbus or to monitor the System Failure (SYSFAIL*) signal on the VMEbus. ACFAIL* is monitored when the jumper is positioned between pins 1 and 2 on header J2. SYSFAIL* is monitored when the jumper is positioned between pins 2 and 3.

J2 J2 +------+ +------+ I 0 0---0 I I 0---0 0 I +------+ +------+ 321 3 2 1 ACFAIL* SYSFAIL*

7 MICROSYSTEMS ®MOTOROLA HARDWARE PREPARATION

2.3.2 VMEbus Request Level Select Headers (J3, J4) The MPU module can be configured to request VMEbus mastership on anyone of four levels. The desired level is selected by jumper configuration on headers I J3 and J4 as shown below: J4 J4 J4 J4 +------+ +------+ +------+ +------+ 12 0 o III 12 I 0 o III 12 I 0 o III 12 I 0 o III I I I I I I I I I 10 0 o I 9 10 I 0 o I 9 10 I 0 o I 9 10 I 0 o I 9 I I I I I I I 8 0 o I 7 8 I 0 o I 7 8 I 0 o I 7 8 I 0 o I 7 I I I I I I I I I 6 0 o I 5 6 I 0 o I 5 6 I 0 o I 5 6 I 0 o I 5 I I I I I I I I I I I I I 4 0 o I 3 4 I 0 o I 3 4 I 0 o I 3 4 I 0 o I 3 I I I I I I I I I 2 0 o I 1 2 I 0 o I 1 2 I 0 o I 1 2 I 0 o I 1 +------+ +------+ +------+ +------+

J3 J3 J3 J3 +------+ +------+ +------+ +------+ 12 I 0 o III 12 I 0 o III 12 I 0 o III 12 I 0 o III I I I I I I I I I I 10 I 0 o I 9 10 I 0 o I 9 10 I 0 o I 9 10 I 0 o I 9 I I I I I I I I 8 I 0 o I 7 8 I 0 o I 7 8 I 0 o I 7 8 I 0 o I 7 I I I I I I I I I I 6 I 0 o I 5 6 I 0 o I 5 6 I 0 o I 5 6 I 0 o I 5 I I I I I I I I I I I I I I 4 I 0 o I 3 4 I 0 o I 3 4 I 0 o I 3 4 I 0 o I 3 I I I I I I I I I I 2 I 0 o I 1 2 I 0 o I 1 2 I 0 o I 1 2 I 0 o I 1 +------+ +------+ +------+ +------+ LEVEL 0 LEVEL 1 LEVEL 2 LEVEL 3

8 MICROSYSTEMS HARDWARE PREPARATION ® MOTOROL.A

2.3.3 ABORT Switch Disable Select Header (JS) The front panel software ABORT switch on the MPU module can be disabled. The 2 switch is disabled when the jumper is removed from header J5. The MPU module is shipped with the switch enabled as shown below.

J5 J5 +---+ +---+ 2 I 0 I 2 101 I I I I I 1 I 0 I 1 101 +---+ +---+ ABORT ABORT SWITCH SWITCH ENABLED DISABLED

2.3.4 RESET Switch Disable Select Header (J6) The front panel RESET switch on the MPU module can be disabled. The switch is disabled when the jumper is removed from header J6. As shown below, the MPU module is shipped with the switch enabled.

J6 J6 +---+ +---+ 2 101 2 101 I I I I I 1 101 1 I 0 I +---+ +---+ RESET RESET SWITCH SWITCH ENABLED DISABLED

9 MICROSYSTEMS HARDWARE PREPARATION @MOTOROLA

2.3.5 VMEbus Interrupt Connection Select Header (J7) Each VMEbus Interrupt Request (IRQ*) signal can be connected as an interrupt request to the MPU. Jumpers on header J7 determine which, if any, of the VMEbus IRQ* signal lines are connected. J7 connects the IRQ* lines so that they drive the corresponding interrupt request levels to the MPU (i.e., IRQl* I requests level 1 to the MPU, IRQ2* requests level 2 to the MPU, etc.). J7 J7 +------+ +------+ 14 0---0 I 13 IRQ7* 14 I 0 0 13 IRQ7* I I 12 0---0 I 11 IRQ6* 12 I 0 0 11 IRQ6* I I 10 0---0 I 9 IRQ5* 10 I 0 0 9 IRQ5* I I 8 0---0 I 7 IRQ4* 8 I 0 0 7 IRQ4* I I 6 0---0 I 5 IRQ3* 6 I 0 0 5 IRQ3* I I 4 0---0 I 3 IRQ2* 4 I 0 0 3 IRQ2* I I 2 0---0 I 1 IRQl* 2 I 0 0 1 IRQl* +------+ +------+ CONNECTED DISCONNECTED

2.3.6 ROM/EPROM Device Configuration Select Header (J8) There are several types of ROM/EPROM devices that can be used in sockets XU44 and XU52. Header J8 must be configured to match the devices used. The figures below show configurations of J8 for the most commonly used devices. When inserting devices into XU44 and XU52, the device containing even data must be inserted into XU44 and the device containing odd data must be inserted into XU52. Even though XU44 and XU52 are 28-pin sockets, 24-pin devices may be used as shown below:

28 27 26 25 24 23 22 21 20 19 18 17 16 15 +------+------+ I I I I I I I I I +------+------~------+ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 I I I I PIN ONE OF 24-PIN DEVICE I I PIN ONE OF 28-PIN DEVICE

10 MICROSYSTEMS HARDWARE PREPARATION ® MOTOROLA

Header configuration for 4K x 8 EPROM memory devices (AM2732, INT2732) is shown below:

J8 +------+ 16 I 0 o 115 I I I 14 I 0 o 113 I I 12 I 0---0 III I I 10 I 0---0 I 9 I I 8 I 0 o I 7 I I 6 I 0 o I 5 I I I 4 I 0 o I 3 I I 2 I 0 o I 1 +------+

Header configuration for 8K x 8 EPROM memory devices (MCM68764, MCM68766) is shown below:

J8 +------+ 16 I 0 o 115 I I 14 I 0 o 113 I I I 12 I 0 o III I I I 10 I 0 o I 9 I I 8 I 0 o I 7 I I 6 I 0 o I 5 I I I 4 I 0 o I 3 I I 2 I 0 o I 1 +------+

11 MICROSYSTEMS HARDWARE PREPARATION (f!jMOTOROLA

Header configuration for 8K x 8 EPROM memory devices (AM2764, INT2764) is shown below:

J8 +------+ I 16 I 0 o 115 I I 14 I 0---0 113 I I 12 I 0---0 III I I 10 I 0---0 I 9 I I 8 I 0 o I 7 I I I 6 I 0 o I 5 I I 4 I 0 o I 3 I I 2 I 0---0 I 1 +------+

Header configuration for 16K x 8 EPROM memory devices (AM27128, INT27128) is shown below:

J8 +------+ 16 I 0 o 115 I I 14 I 0---0 113 I I 12 I 0---0 III I I 10 I 0---0 I 9 I I 8 I 0 o I 7 I I I 6 I 0 o I 5 I I 4 I 0 o I 3 I I 2 I 0---0 I 1 +------+

12 MICROSYSTEMS (f!jMOTOROLA HARDWARE PREPARATION

Header configuration for 32K x 8 EPROM memory devices (AM27256) is shown below:

J8 +------+ 16 0 0 15 I 14 0---0 13

12 0---0 11

10 0---0 9

8 0---0 7

6 0 0 5

4 0 0 3

2 0---0 1 +------+

Header configuration for 64K x 8 EPROM memory devices (AM27512) is shown below:

J8 +------+ 16 0---0 115 I 14 0---0 113 I 12 0---0 111 I 10 0---0 I 9 I 8 0---0 I 7 I 6 o-X-o<------THE CIRCUIT TRACK ON THE I BACK OF THE MODULE MUST 4 0 0 I 3' BE CUT I 2 0---0 I 1 +------+

13 MICROSYSTEMS HARDWARE PREPARATION ® MOTOROl-A

2.3.7 Cache Configuration Select Headers (J9, J17) The cache can be configured for one of four modes. The cache has a total of 4Kb. The modes are user only, supervisor only, mixed user and supervisor, and 2Kb supervisor and 2Kb user. Jumper position on headers J9 and J17 determine I what mode is selected, as shown below: J9 J17 +------+ +---+ I 0---0 0 I 3 I 0 I +------+ I I 3 2 1 2 I 0 I I I I 1 I 0 I +---+

ALL 4KB OF CACHE ARE USER ONLY

J9 J17 +------+ +---+ I 0---0 0 I 3 I 0 I +------+ I I I 321 2 I 0 I I I 1 I 0 I +---+

ALL 4KB OF CACHE ARE SUPERVISOR ONLY

J9 J17 +------+ +---+ I 0---0 0 I 3 101 +------+ I I 321 2 101 I I 1 I 0 I +---+

ALL 4KB OF CACHE ARE MIXED USER AND SUPERVISOR

14 MICROSYSTEMS HARDWARE PREPARATION ® MOTOROI.A

J9 J17 +------+ +---+ I 0 0---0 I 3 I 0 I +------+ I I 3 2 1 2 I 0 I I I I 1 101 +---+

2KB OF CACHE ARE USER ONLY 2KB OF CACHE ARE SUPERVISOR ONLY

2.3.8 MSR Bit 1 Source Select Header (J20) Bit 1 of the MSR is always connected to section 1 of switch S3. It is high when section 1 is open and low when closed. The signal line Cache Error (CACHERR*) can also be connected to bit 1 of the MSR and section 1. When CACHERR* is connected through header J20 and section 1 is closed, then cache is disabled. When section 1 is open, the signal line CACHERR* can be monitored but this is not a useful configuration. Header configurations and switch settings are shown below:

J20 J20 +---+ +---+ 2 I 0 I 2 I 0 I I I I I I 1 101 1 101 +---+ +---+

S3 S3 S3 S3 +------+ +------+ +------+ +------+ 111X 101 111 XIOI 111X 101 111 XIOI I FI I F I I F I I F I 121 I FI 121 I F I 121 I FI 121 I FI I II I II I II I II 131 101 131 101 131 101 131 101 I PI I PI I PI I PI 141 I EI 141 lEI 141 lEI 141 lEI I NI I NI I NI I NI +------+ +------+ +------+ +------+

MSR BIT 1=0 MSR BIT 1=1 CACHE THIS DISABLED CONFIGURATION (MSR BIT 1 IS NOT ALWAYS LOW) RECOMMENDED

15 MICROSYSTEMS @MOTOROLA HARDWARE PREPARATION

2.3.9 MSR Bit 0 Source Select Header (J21) Bit 0 of the MSR can be configured to monitor section 2 of switch 53 or to monitor the signal line Cache Hit (CACHEHIT*). If it is connected to section 2, it is high when section 2 is open and low when closed. If bit 0 is connected to the signal CACHEHIT*, it matches the level of CACHEHIT*. Header I and switch configurations are shown below: J21 J21 +---+ +---+ 3 101 3 101 I I I I I 2 I 0 I 2 101 I I I I I 1 I 0 I 1 101 +---+ +---+

SECTION 2 OF S3 CONNECTED [CACHEHIT*] CONNECTED TO BIT 0 OF THE MSR TO BIT 0 OF THE MSR

S3 53 +------+ +------+ III 101 III 101 I FI I FI 121X I FI 121 XIFI I II I II 131 101 131 101 I PI I PI 141 IE I I I lEI I NI I NI +------+ +------+

MSR BIT 0=0 MSR BIT 0=1

16 MICROSYSTEMS @MOTOROLA HARDWARE PREPARATION

2.3.10 ROM Access Time Select Header (J22) Header J22 must be configured to match the access time of the EPROM/ROM devices that are installed in sockets XU44 and XU52 as shown in the figures 2 and tables below. Access time is the longer of the time from valid address to valid data or from chip enable to valid data at the pins of the ROM devices. Note that other header configurations affect the configuration of J22 for any given ROM access time.

J22 J22 J22 J22 +------+ +------+ +------+ +------+ 8 I 0 o I 7 8 I 0 o I 7 8 I 0 o I 7 8 I 0---0 I 7 I I I I I I I I 6 I 0 o I 5 6 I 0 o I 5 6 I 0---0 I 5 6 I 0 o I 5 I I I I I I I I 4 I 0 o I 3 4 I 0---0 I 3 4 I 0 o I 3 4 I 0 o I 3 I I I I I I I I 2 I 0---0 I 1 2 I 0 o I 1 2 I 0 o I 1 2 I 0 o I 1 +------+ +------+ +------+ +------+ ROM ACCESS TIME ROM ACCESS TIME ROM ACCESS TIME ROM ACCESS TIME LESS THAN OR LESS THAN OR LESS THAN OR LESS THAN OR EQUAL TO EQUAL TO EQUAL TO EQUAL TO MVME 120, 121, 123 N/A 250 ns 350 ns 450 ns MVME 122 200 ns 400 ns 450 ns 500 ns

2.3.11 Reset Vector Fetch Mode Select Header (J24) The MPU module can fetch the reset vector from onboard ROM or from the VMEbus. When the MPU module fetches the reset vectors from the VMEbus, address modifier code IE or 16 can be used. The mode used is controlled by the position of the jumper on the header and by section 3 and 4 of switch S3 as shown below:

17 MICROSYSTEMS @MOTOROLA HARDWARE PREPARATION

J24 J24 J24 +---+ +---+ +---+ 3 101 3 101 3 101 II I I I I I 2 101 2 101 2 101 I I I I I I I I 1 I 0 I 1 I 0 I 1 I 0 I +-- -+ +---+ +---+ FETCH RESET SECTION 4 OF S3 NEVER FETCH VECTORS FROM CONTROLS MODE RESET VECTORS VMEbus (SEE BELOW) FROM VMEbus (SWITCH HAS NO EFFECT) (SWITCH HAS NO EFFECT) S3 S3 +------+ +------+ 11 101 III 101 I F I I F I 121 IF I 121 IF I I II I II 131 XIOI 131 XI 0 I I PI I PI 141 X I EI 141 XI EI I NI I NI +------+ +------+ FETCH RESET FETCH RESET VECTORS FROM VECTORS FROM VMEbus ONBOARD ADDRESS MODIFIER=lE S3 S3 +------+ +------+ III 101 III 101 I F I I F I 121 IF I 1211 FI I II I II 131X 101 131X 101 I PI I PI 141 X IE I 141 XI E I I NI I NI +------+ +------+ FETCH RESET FETCH RESET VECTORS FROM VECTORS FROM VMEbus ON BOARD ADDRESS MODIFIER=16

18 MICROSYSTEMS HARDWARE PREPARATION ® MOTOROI.A

2.3.12 Local Time-out Select Header (J25) The local bus time-out of the MPU module can be configured for one of three times using jumper positioning on header J25. The user must ensure that the I system controller module has the global bus time-out set correctly.

J25 J25 J25 +------+ +------+ +------+ 1 I 0---0 I 2 1 I 0 0 I 2 1 I 0 0 I 2 I I I I I I 3 I 0 0 I 4 3 I 0---0 I 4 3 I 0 0 I 4 I I I I I I 5 I 0 0 I 6 5 I 0 0 I 6 5 I 0---0 I 6 +------+ +------+ +------+ LOCAL TIME-OUT LOCAL TIME-OUT LOCAL TIME-OUT = 103-137 =43-77 =13-47 MICROSECONDS MICROSECONDS MICROSECONDS THE VMEbus GLOBAL THE VMEbus GLOBAL THE VMEbus GLOBAL BUS TIME-OUT BUS TIME-OUT BUS TIME -OUT MUST BE LESS MUST BE LESS MUST BE LESS THAN OR EQUAL TO THAN OR EQUAL TO THAN OR EQUAL TO 110 MICROSECONDS 170 MICROSECONDS 200 MICROSECONDS

2.3.13 RAM Dual Port Base Address Select PAL (U28) The onboard RAM of the MPU Module is accessible by the onboard MPU and by ot~er VMEbus masters. The lower address at which the onboard RAM appears for the VMEbus master is called the RAM dual port base address. The RAM dual port base address is controlled by the program in the PAL in socket U28. The PAL can, be programmed to· place the RAM dual port base address on any 128Kb boundary for 128K of onboard RAM or on any 512Kb boundary for 512K of onboard RAM. The PAL in socket U28 is a PAL16L2 with a propagation delay time that is less than or equal to 35 ns.

2.3.13.1 Factory Configured RAM Dual Port Base Address. The factory configuration of U28 places the RAM dual port base address at 000000. The figures below show the source code for the factory configuration of U28 for 128Kb of onboard RAM and for 512Kb of onboard RAM.

19 MICROSYSTEMS @MOTOROLA HARDWARE PREPARATION

PAL16L2 2-17-84 U28-SHEET 8 MVME120, MVME122 CKSM= 0744 PALDP20 REV A A23 A22 A21 A20 A19 A18 A17 /LWORD /IACK GND I AMI AM3 AM2 AM4 15 /DPMATCH AMO AM5 VMEAV VCC DPMATCH = /A23*/A22*/A21*/A20*/AI9*/A18*/A17 ;$OOOOOO-$OIFFFF */IACK*/LWORD*/VMEAV *AM5*AM4*AM3*AM2*AMI*AMO ;STANDARD PRIV PROG

+ /A23*/A22*/A21*/A20*/A19*/A18*/A17 ;$OOOOOO-$OlFFFF */IACK*/LWORD*/VMEAV *AM5*AM4*AM3*AM2*/AMI*AMO ;STANDARD PRIV DATA + /A23*/A22*/A21*/A20*/A19*/AI8*/A17 ;$OOOOOO-$OlFFFF */IACK*/LWORD*/VMEAV *AM5*AM4*AM3*/AM2*AM1*/AMO ;STANDARD NON-PRIV PROG + /A23*/A22*/A21*/A20*/AI9*/AI8*/AI7 ;$OOOOOO-$OlFFFF */IACK*/LWORD*/VMEAV *AM5*AM4*AM3*/AM2*/AM1*AMO ;STANDARD NON-PRIV DATA DESCRIPTION: DUAL PORT MAP DECODER{128KBYTE ONBOARD RAM) SET FOR VMEBUS ADDRESSES 0-lFFFF

PAL16L2 7-23-84 U28-SHEET 8 MVME121 ,MVME123 CKSM= OlCC PALDP21 REV A A23 A22 A21 A20 A19 Al8 A17 /LWORD /IACK GND AMI AM3 AM2 AM4 15 /DPMATCH AMO AM5 VMEAV VCC DPMATCH = /A23*/A22*/A21*/A20*/A19 ;$OOOOOO-$07FFFF */IACK*/LWORD*/VMEAV *AM5*AM4*AM3*AM2*AM1*/AMO ;STANDARD PRIV PROG + /A23*/A22*/A21*/A20*/AI9 ;$OOOOOO-$07FFFF */IACK*/LWORD*/VMEAV *AM5*AM4*AM3*AM2*/AM1*AMO ;STANDARD PRIV DATA + /A23*/A22*/A21*/A20*/A19 ;$OOOOOO-$07FFFF */IACK*/LWORD*/VMEAV *AM5*AM4*AM3*/AM2*AM1*/AMO ;STANDARD NON-PRIV PROG

+ /A23*/A22*/A21*/A20*/A19 ;$OOOOOO-$07FFFF */IACK*/LWORD*/VMEAV *AM5*AM4*AM3*/AM2*/AMI*AMO ;STANDARD NON-PRIV DATA DESCRIPTION: DUAL PORT MAP DECODER(512KBYTE ONBOARD DYNAMIC RAM) SET FOR VMEBUS ADDRESSES O~7FFFF

20 MICROSYSTEMS @MOTOROLA HARDWARE PREPARATION

2.3.13.2 Changing U28. The device used in U28 is a PAL16L2 with a maximum propagation delay time of 35 ns. PAL16L2's are not reprogrammable so the new firmware in U28 requires a new PAL16L2. When changing the source code for U28 2 only the lines that affect the ADDRESS should be changed. The other lines must remain intact for proper operation of the module. Below are sample ADDRESS source lines and the resultant base addresses.

/A23*/A22*/A2l*/A20*/A19*/A18* A17 ;ADDRESS=$20000-$3FFFF /A23*/A22*/A2l*/A20*/A19* A18*/A17 ;ADDRESS=$40000-$5FFFF /A23*/A22*/A2l*/A20*/A19* A18* A17 ;ADDRESS=$60000-$7FFFF SAMPLE ADDRESS LINES FOR l28KBYTES OF ON BOARD RAM

/A23*/A22*/A21*/A20* A19 ;ADDRESS=$80000-$FFFFF /A23*/A22*/A2l* A20*/A19 ;ADDRESS=$lOOOOO-$17FFFF /A23*/A22*/A21* A20* A19 ;ADDRESS=$180000-$lFFFFF SAMPLE ADDRESS LINES FOR 1/2MBYTE OF ON BOARD RAM

2.4 INSTALLATION The following paragraphs discuss installation of the MPU module into a VME chassis and the connection of an RS-232C cable. Before inserting the module into the VMEbus chassis ensure that the desired EPROM/ROM devices are installed and configured and that all other headers, switches, and PAL's are configured for desired operation.

2.4.1 Module Installation Now that the module is ready for installation, proceed as follows: a. Turn all equipment power OFF. CAUTION INSERTING/REMOVING MODULES WHILE POWER IS APPLIED COULD RESULT IN .DAMAGE TO MODULE COMPONENTS. b. The module may be installed into any double wide unused card slot which has a VMEbus backplane on the connector PI side.

21 MICROSYSTEMS @MOTOROLA HARDWARE PREPARATION

c. Ensure that the BG* and IACK* daisy-chains are complete on the PI backplane. Each daisy-chain line must be connected from IN to OUT at each connector on the PI backplane. This must either be a direct (shorted) connection or an indirect (gated) connection. Modules that use a daisy-chain line automatically provide an indirect connection from that line's IN pin to the OUT pin on the connector into which the I module is inserted. If the module does not use a daisy-chain line, then it should automatically provide a direct connection from that line's IN pin to the OUT pin on the connector into which the module is inserted. However, some modules do not provide direct connections. With these modules the daisy-chain signal line in question must be shorted at that connector using the means provided on the PI backplane (generally shorting jumpers on a header). In addition, any slots that do not have a module inserted into the PI connector, require that all the daisy-chain signal lines be shorted using the means provided on the backplane. Daisy-chain signal lines that are indirectly connected by a module should not be shorted on the backplane at that slot. The MPU module connects all the daisy-chain signal lines indirectly (except for the IACKIN*-IACKOUT* signal lines which it connects directly), so that none of the daisy-chain signal lines should be shorted on the backplane at the slot where it resides. d. Carefully slide module into card slot. Be sure module is seated properly into connectors on the PI backplane. Fasten module in chassis with front panel screws provided. e. Make sure that all devices on the VMEbus respond to unique address locations. More than one VMEbus device may not respond to the same address and address modifier combination. For example, if two MPU modules reside on the same PI backplane, the RAM dual port base address must be programmed differently on one module then it is on the other. f. Ensure that only one module responds to anyone IRQ signal line on the VMEbus. g. Ensure that a system controller module is present at the highest priority slot of the PI backplane (the MPU module is not a system controller) . h. Make sure that forced air cooling is in place for the modules in the system. i. Turn equipment power ON.

2.4.2 Terminal Connection The RS-232C serial port on the front panel is configured for terminal operation only. A 25-pin RS-232C cable may be connected to the front panel connector with the other end connected to a compatible terminal. Refer to Table 5-2 for detailed information on signals supported.

22 MICROSYSTEMS OPERATING INSTRUCTIONS (f!jMOTOROL.A

CHAPTER 3 OPERATING INSTRUCTIONS

3.1 INTRODUCTION This chapter provides the necessary information to use the MPU module in a I system configuration.

3.2 CONTROLS AND INDICATORS The MPU module has a RESET switch, an ABORT switch, a mode switch, a FAIL indicator, a HALT indicator, and a RUN indicator. All switches and indicators are located on the front panel of the module.

3.2.1 RESET Switch The reset performed by the RESET switch is a board-level reset only. A system level reset is performed by the system controller module that is needed to operate with the MPU module. The MPU is not immediately reset when the RESET switch is depressed, but instead, waits for the current access of the MPU to be completed before entering the reset state. This sequence prevents short cycling onboard and unintentional VMEbus accesses. The module is immediately reset by SYSRESET*.

3.2.2 ABORT Switch A software ABORT switch is located on the front panel. Programs may be aborted with this switch. Oepressing this switch causes a level 7 interrupt to be input to the MPU. "The ABORT switch does not abort the MPU during the execution of the STOP instruction.

3.2.3 Mode Switch The mode switch (section 4 of S3) provides the ability through hardware for the MPU to fetch the reset stack pointer and Program Counter (PC) from either the onboard ROM/EPROM sockets, or from a VMEbus resource that can respond to Address Modifier (AM) code IE or 16. The MVME050 controller module can perform this task. Section 3 of switch S3 selects either AM code 16 or IE for VMEbus accesses of reset vector and stack pointer. The mode switch may be disabled through header J24. Header J24 can be configured to force either the normal or alternate mode of operation. The result of the header configuration and mode switch position is also readable through the MSR.

23 MICROSYSTEMS OPERATING INSTRUCTIONS ® MOTOROLA

3.2.4 FAIL Indicator The red LED FAIL indicator is lit whenever the MPU enters a halted state (MPU driving the HALT line low usually the result of a double bus fault). The indicator is lit when the MPU is being reset. The indicator is lit when the module fail bit of the MCR is set (whenever the FAIL bit is set, the module also drives the SYSFAIL* line low on the VMEbus). The dual port lock condition lights the indicator momentarily. Refer to Table 3-1 for details. II 3.2.5 HALT Indicator The red LED HALT indicator is lit whenever the MPU enters a halted state (usually the result of a double bus fault). The indicator is lit when the MPU is being reset. The dual port lock condition lights the indicator momentarily. Refer to Table 3-1 for details.

3.2.6 RUN Indicator The green LED RUN indicator is lit whenever the Address Strobe (AS*) pin of the MPU is true and off when it is false. Refer to Table 3-1 for details.

TABLE 3-1. Interpretation of Front Panel Indicators ======FAIL HALT RUN DESCRIPTION ======~======OFF OFF OFF No power applied to the module, or processor running but is not the local bus master. OFF OFF ON Normal operation. ON ON OFF Module is being reset or MPU has halted (usually the result of a double bus fault). ON OFF ON MPU is executing code but BRDFAIL (bit 0) in the MCR is set to 1. Bit may have been set to 1 by software, such as self-test routine, or the bit was not cleared to 0 by software since the last time the module was reset. ON OFF OFF Bit 0 in the MCR is set to 1 either by software or reset and MPU is not local bus master. ON ON ON MPU is running and dual port locks are occurring. Frequency of dual port lock determines intensity of halt and fail. ======NOTE: All other combinations are illegal. If they occur, there is most likely some type of hardware malfunction. ======

24 MICROSYSTEMS OPERATING INSTRUCTIONS ®MOTOROLA

3.3 MPU MODULE MEMORY MAP The MPU module memory map as viewed from the onboard MPU is shown below:

ADDRESS RANGE DI5 D08 D07 DOO +------+------+ 000000 I ON BOARD ROM (IF ONBOARD MODE)/VMEbus I (IF OFFBOARD MODE) FOR FIRST 4 MEMORY I CYCLES AFTER RESET. ONBOARD RAM 000007 I THEREAFTER. ------+------000008 I ONBOARD RAM - 128Kb I 01FFFF (07FFFF) I 512Kb (OPTIONAL) ------+------020000 (080000) I VMEbus EFFFFF I ------+------FOOOOO I ONBOARD ROM FOFFFF I ------+------F10000 I RESERVED FOR ONBOARD ROM EXPANSION F1FFFF I ------+------+------F20000 I RESERVED (1) I MFP GPIP ------+------+------F20002 I RESERVED (1) I MFP AER ------+------+------F20004 I RESERVED (1) I MFP DDR ------+------+------F20006 I RESERVED (1) I MFP IERA ------+------+------F20008 I RESERVED (1) I MFP IERB ------+------+------~------F2000A I RESERVED (1) I MFP IPRA ------+------+------F2000C I RESERVED (1) I MFP IPRB ------+------+------F2000E I RESERVED (1) I MFP ISRA ------+------+------F20010 I RESERVED (1) I MFP ISRB ------+------+------F20012 I RESERVED (1) I MFP IMRA ------+------+------F20014 I RESERVED (1) I MFP IMRB ------+------+------F20016 I RESERVED (1) I MFP VR ------+------+------F20018 I RESERVED (1) I MFP TACR ------+------+------F2001A I RESERVED (1) I MFP TBCR ------+------+------F200 1C I RESERVED (1) I MFP TCDCR +------+------+------+

25 MICROSYSTEMS @MOTOROLA OPERATING INSTRUCTIONS

ADDRESS RANGE DIS D08 D07 DOO +------+------+------+ F2001E 1 RESERVED (1) 1 MFP TADR 1 ------+------+------1 F20020 1 RESERVED (1) 1 MFP TBDR 1 ------+------+------1 F20022 1 RESERVED (1) 1 MFP TCDR 1 ------+------+------1 F20024 1 RESERVED (1) 1 MFP TDDR 1 ------+------+------1 F20026 1 RESERVED (1) 1 MFP SCR 1 I ------+------+------1 F20028 1 RESERVED (1) 1 MFP UCR 1 ------+------+------1 F2002A 1 RESERVED (1) I MFP RSR ------+------+------F2002C 1 RESERVED (1) 1 MFP TSR ------+------+------F2002E 1 RESERVED (1) 1 MFP UDR ------+------+------F20030 1 THE ABOVE MFP REGISTERS OCCUR REPEATEDLY F3FFFF 1 IN THIS SPACE ------+------+------F40000 1 VME120 1 RESERVED I CONTROL REGISTER 1 ------+------+------F40002 1 VME120 1 1 CONTROL REGISTER 1 RESERVED F5FFFF IREPEATS IN THIS SPACE 1 ------+------+------F60000 1 MMU AST 0 (2) 1 RESERVED ------+------+------F60002 1 MMU AST 1 (2) I RESERVED ------+------+------1 F60004 I MMU AST 2 (2) 1 RESERVED 1 ------+------+------1 F60006 1 MMU AST 3 (2) 1 RESERVED ------~------+------+------F60008 1 MMU AST 4 (2) 1 RESERVED ------+------+------F6000A 1 MMU AST 5 (2) 1 RESERVED ------+------+------F6000C 1 MMU AST 6 (2) 1 RESERVED ------+------+------F6000E 1 MMU AST 7 (2) 1 RESERVED ------+------+------F60010 1 MMU AST 8 (2) 1 RESERVED ------+------+------F60012 1 MMU AST 9 (2) 1 RESERVED ------+------+------F60014 1 MMU AST 10 (2)1 RESERVED 1 ------+------+------1 F60016 1 MMU AST 11 (2)1 RESERVED 1 +------+------+------+

26 MICROSYSTEMS (f!jMOTOROLA OPERATING INSTRUCTIONS

ADDRESS RANGE 015 008 007 000 +------+------+------+ 1 F60018 1 MMU AST 12 (2) 1 RESERVED 1 1------+------+------1 1 F6001A 1 MMU AST 13 (2)1 RESERVED 1 1------+------+------1 1 F6001C 1 MMU AST 14 (2) 1 RESERVED 1 1------+------+------1 F6001E 1 MMU AST 15 (2)1 RESERVED ------+------+------F60020 1 MMU ACO (2) 1 MMU ACI (2) ------+------+------I F60022 1 MMU AC2 (2) 1 MMU AC3 (2) ------+------+------F60024 1 MMU AC4 (2) 1 MMU AC5 (2) ------+------+------F60026 1 MMU AC6 (2) 1 MMU AC7 (2) ------+------+------F60028 1 MMU AC8 (2) 1 MMU DP (2) ------+------+------F6002A 1 RESERVED 1 MMU IVR (2) ------+------+------F6002C 1 RESERVED 1 MMU GSR (2) 1 ------+------+------F6002E 1 RESERVED 1 MMU LSR (2) ------+------+------F60030 1 RESERVED 1 MMU SSR (2) ------+------+------1 F60032 1 RESERVED 1 RESERVED ------+------+------F60034 1 RESERVED 1 RESERVED ------+------+------F60036 1 RESERVED 1 RESERVED ------+------+------F60038 1 RESERVED 1 MMU lOP (2) ------+------+------F6003A 1 RESERVED 1 MMU RDP (2) ------+------+------1 F6003C 1 RESERVED 1 MMU DIRECT 1 1 1 TRANSLATION 1 ------+------+------1 F6003E 1 RESERVED LOAD DESCRIPTOR 1 ------+------1 F60040 1 THE ABOVE MMU REGISTERS OCCUR 1 F7FFFF 1 REPEATEDLY IN THIS SPACE 1 ------+------1 F80000 1 RESERVED 1 ------+------1 1 F80002 1 BANK 2 CACHE CLEAR 1 1 1 (READ OR WRITE CYCLE) 1 +------+------+

27 MICROSYSTEMS OPERATING INSTRUCTIONS ® MOTOROLA

ADDRESS RANGE 015 008 007 000 +------+------+ F80004 1 BANK 1 CACHE CLEAR 1 1 (READ OR WRITE CYCLE) 1 ------+------1 F80006 1 BANKS 1 AND 2 CACHE CLEAR 1 1 (READ OR WRITE CYCLE) 1 ------+------1 F80008 1 THE ABOVE CACHE CLEAR AREAS APPEAR 1 F9FFFF 1 REPEATEDLY IN THIS SPACE 1 ------+------1 I FAOOOO 1 VMEbus 1 FEFFFF 1 1 ------+------1 FFOOOO 1 VMEbus 1 FFFFFF 1 (GLOBAL SHORT I/O PAGE) 1 +------+------+ NOTES: Bank 1 is the user half and bank 2 is the supervisory half of the cache when the cache is configured as 1/2 user and 1/2 supervisory. If the whole cache is supervisory or user or mixed then cache should be completely cleared using F80006. (1) Accesses to only the even bytes of these locations causes the MPU module to hang up until reset occurs. (2) Only if the MMU is present (accesses to these locations when no MMU is present causes the MPU module to hang up until reset occurs).

3.3.1 MPU Module Memory Map as Viewed from the VMEbus The onboard RAM appears to the VMEbus at the base address programmed into U28. The factory configuration of U28 causes the base address of onboard RAM as viewed from the VMEbus to be 000000. If U28 is changed (refer to paragraph 2.3.13.2 for instructions to change U28), then the user must be aware that RAM now appears at a different address for the VMEbus. For example, if the MPU executes a routine that tells a Direct Memory Access (DMA) module on the VMEbus to fill the onboard RAM wi th a program, the MPU must gi ve the correct address (which is different from the address at which it executes the program) to the DMA module.

28 MICROS YS TEMS FUNCTIONAL DESCRIPTION @MOTOROLA

CHAPTER 4 FUNCTIONAL DESCRIPTION

4.1 INTRODUCTION This chapter provides the overall block diagram level description for the MPU module. The general description provides a overview of the module, followed by a detailed description of each section of the module. Figure 4-1 shows the block diagram of the MPU module.

4.2 GENERAL DESCRIPTION During normal operation, the MPU fetches and executes instructions that were already loaded in the logical instruction cache memory. If there is a cache miss (instruction not in cache, data r/w, or CPU cycle), the hardware activates the MMU causing it to generate physical addresses, which are decoded to access either onboard memory and I/O, or VMEbus memory and I/O. If the MPU was fetching a cachable instruction when the cache miss occurred, then the cache is updated with the new instruction. The entire cache is flushed by accessing a specific location in the memory map, or by resetting the module. To minimize access time from the onboard memory when a cache miss occurs, the onboard dynamic memory begins its access cycle using the lower nine address lines for its row address. It then waits for the physical addresses from the MMU to become valid, and for a select from the address decoder to complete the column addressing. The lowest nine address lines are always required to be nontranslatable with this mode of operation, and restricts memory segmentation to a minimum size of 1024 bytes. Programs are aborted by depressing the ABORT switch on the front panel of the module. Depressing this switch interrupts the MPU at level 7. The module is reset whenever the entire system is reset (SYSTEM RESET line on the bus goes low), or locally by depressing the RESET switch on the front panel of the module. The RESET switch on the MPU module does not generate a global reset because the MPU module is always used with a system controller module that generates the global reset. The two ROM/EPROM sockets are normally used to hold the user-supplied self­ test/boot load program. Immediately after a module reset, the MPU fetches its stack pointer and PC from the socket pair. However, if the front panel mode select switch on the MPU module is placed in its alternate position before the module reset, the MPU fetches its stack pointer and PC from the VMEbus at locations 0-7 using AM code IE or 16. A serial RS-232C debug terminal port connector is located on the front panel of the MPU module. This connector is configured for terminal use only. The baud rates are software programmable for 300 to 9600 baud. The serial port is normally used for debugging.

29 MICROSYSTEMS FUNCTIONAL DESCRIPTION @MOTOROLA

The onboard RAM is accessible from the VMEbus by multi-porting the onboard local bus. The intention of the VMEbus port to the local RAM is to allow programs to be loaded into the onboard RAM from DMA type disk controller or Local Area Network (LAN) module. The address is set by the Programmable Array Logic (PAL), that must be replaced with a user programmed unit, if another address is required. For multiprocessor systems, only one MPU can use the original address decoder. All others must have new decoder.

4.3 BLOCK DIAGRAM DESCRIPTION The block diagram is shown in Figure 4-1. The MPU module operates through the following functional blocks. MPU MMU Cache I RAM Multi-port controller Bus requester Interrupt handler VMEbus interface I/O and control ROM

4.3.1 MPU The MC68010 MPU in a pin grid array package is the modules engine. The MPU and its associated circuitry are designed to run at 12.5 MHz. The clock is a 25 MHz oscillator divided by a flip-flop. Although the circuitry is designed to run at 10 MHz or 12.5 MHz depending on the version of the module.

4.3.2 MMU The MMU is an MC68451 in a pin grid array package. The MMU is able to translate A8-A23 of the processor. However, to improve access time from the onboard memory, the MMU translates A10-A23 only. This restriction saves one wait cycle when accessing onboard memory, but limits the smallest segment size to 1024 bytes. On versions of the module where the MMU is not present, the MMU is replaced with a printed circuit jumper block. When accesses are made to the MMU address space with no MMU on module (MVME122/123), the MPU hangs up waiting until reset occurs. Do not attempt to access the MMU address space if no MMU is present.

30 MICROSYSTEMS FUNCTIONAL DESCRIPTION @ MOTOROLA

4.3.3 Cache The cache memory is single set-associative with a block size of 1 word. It has a total capacity of 2048 sixteen bit words, and is for instruction storage only. As shown in the block diagram, the cache is located between the MPU and MMU. This placement of cache provides no wait state operation by the MPU on cache hit cycles. The following is an in depth discussion of the cache on the MPU module.

4.3.3.1 Cache Organization. The cache has four jumper controlled configurations: a. 2K words of user program space cache. b. 2K words of supervisory program space cache. c. 2K words of user program space/supervisory program space (mixed) cache. d. 1K word of user space cache and 1K word of supervisory space cache.

Configurations a,b,c each have one bank of 2K entries. Configuration d has two banks of lK entries each. Each entry within cache is addressed by the MPU lower address lines (AI-AID for configuration d or AI-All for configurations a,b,c). These lower address lines are called the index. For every possible index value there is a unique cache entry. Each cache entry contains two information fields - cache data (16 bits), and cache tag (15 bits). Refer to the figure below: CACHE ORGANIZATION FOR CONFIGURATIONS A,B,C CACHE TAG CACHE DATA INDEX 1<------15 BITS------>I 1<--16 BITS-->I +-+--+--+------+ +------+ $000 IFIV11V21 A12-A23 I I 000-015 I 1-+--+--+------1 1------1 $002 IFIV11V21 A12-A23 I I 000-015 I 1-+--+--+------1 1------1 I I I I

I I I I 1-+--+--+------1 1------1 $FFE IV I VII V21 A12-A23 I I 000-015 I +-+--+--+------+ +------+

31 MICROSYSTEMS FUNCTIONAL DESCRIPTION ®MOTOROLA

CACHE ORGANIZATION FOR CONFIGURATION 0 BANK 1 (FC2=0) BANK 2 (FC2=1) CACHE TAG CACHE DATA CACHE TAG CACHE DATA INDEX 1<--15 BITS-->I<-16 BITS->I INDEX 1<--15 BITS-->I<-16 BITS->I +--+--+------+------+ +--+--+------+------+ $000 IV11V21A11-A231 000-015 1 $000 IV11V21A11-A231 000-015 1 1--+--+------+------1 1--+--+------+------1 $002 IV11V21A11-A231 000-015 1 $002 IV11V21A11-A231 000-015 1 1--+--+------+------1 1--+--+------+------1 1 1 1 1

I 1 1 1 1 1--+--+------+------1 1--+--+------+------1 $7FE IV11V21A11-A231 000-015 1 $7FE IV11V21A11-A231 000-015 1 +--+--+------+------+ +--+--+------+------+

Cache data is the data that has been cached from main memory. Cache tag consists of the following: Tag bits All (or A12) through A23 constitute the upper logical address of the data in main memory from where the cache data was copied. Tag bits VI and V2 indicate the validity of cache data. When either of them is 0, the cache data for that entry is not valid. When they are both 1, it is valid. Tag bit F matches the value of FC2 when the cache data was originally copied from main memory (FC2=1 for supervisory address space and 0 for user address space). This organization of cache is called single set-associative. It causes each entry in cache to align itself with specific main memory locations. For example, for configurations a,b,c, cache entry 1 (index = 000) is only capable of caching memory locations 0, 1000, 2000, 3000, etc. Cache entry 4 (index = 006) is only capable of of caching memory locations 0006, 1006, 2006, 3006. This means that at any given time, cache entry 4 can have cached memory location 0006 or 1006 or 2006 or 3006, etc., but never 0000-0004 or 0008-1004 or 1008-2004, etc. Adjacent cache entries always have adjacent indexes but do not necessarily come from the same block of memory. For example, cache entry 8 (index=OOE) may contain data from memory location 200E while cache entry 7 (index=OOC) contains data from memory location 400C and cache entry 6 (index=OOA) contains data from memory location 1000A. See figure below:

32 MICROSYSTEMS FUNCTIONAL DESCRIPTION ® MOTOROL.A

SAMPLE CACHE STATE USING CONFIGURATION C CACHE TAG CACHE DATA CACHED MEMORY INDEX IFIVI1V21 A23-A12 I DOO-DI5 I ADDRESS +-+--+--+------+ +------+ $000 11 11 11 $001 I $4E71 $1000 -+--+--+------$002 11 11 11 $008 $60FO $8002 -+--+--+------$004 XI 01 01 XXXX XXXXX XXXXX -+--+--+------$006 01 11 11 $008 $4E71 $8006 -+--+--+------$008 01 11 11 $008 $60FC $8008 -+--+--+------$OOA 01 11 11 $010 $4E71 $1000A -+--+--+------$OOC 01 11 11 $004 $60FE $400C -+--+--+------$OOE 01 11 11 $002 $60FA $200E 1-+--+--+------I

I I I I 1-+--+--+------1 1------1 $FFE 1111111 $001 I I $4AFB I $1FFE +-+--+--+------+ +------+

4.3.3.2 Cache Operation. The cache performs its operations only during memory access cycles by the MPU. It operates on one entry per memory access cycle (except for cache flush operations). The cache does not perform any function during RAM refresh cycles, or VMEbus to RAM access cycles. At the beginning of each processor memory access cycle (before any devices on the module can be selected) the MPU lower address lines index a specific entry in the cache. The valid bits for that entry are checked and the tag from that entry is compared to the MPU upper address lines and to FC2. Depending on the results of the validity check and the comparison, the rest of the memory access cycle is classified as one of four types: Cache hit cycle Cache validate cycle Cache invalidate cycle Cache ignore cycle

33 MICROSYSTEMS FUNCTIONAL DESCRIPTION ®MOTOROLA

Cache Hit Cycle When the cache has determined that the current cycle is a cache hit cycle, the following occurs: a. All selects to non-cache devices are disabled. b. The cache presents the cache data word to the MPU. c. The cache drives [DTACK*] to the MPU in time for the cycle to complete in a wait states.

Cache Validate Cycle When the cache has determined that the current cycle is a cache validate I cycle, the following occurs: a. The selects to the rest of the module are allowed to happen. b. The selected device presents its data to the MPU. c. The cache latches the data that is being driven onto 000-015 by the selected device, into the cache data word. d. The cache latches the value that is being driven onto All (or AI2) and FC2 by the MPU, into the cache tag. e. The cache sets VI and V2 in the cache tag. f. The MPU finishes the cycle with the number of wait cycles indicated by the selected device.

Cache Invalidate Cycle When the cache has determined that the current cycle is a cache invalidate cycle, the following occurs: a. The selects to the rest of the module are allowed to happen. b. The selected device mayor may not present data to the MPU. c. The cache clears VI or V2 or both. d. The MPU finishes the cycle with the number of wait cycles indicated by the selected device.

34 MICROSYSTEMS ®MOTOROLA FUNCTIONAL DESCRIPTION

Cache Ignore Cycle When the cache has determined that the current cycle is a cache ignore cycle, the following occurs: a. The selects to the rest of the module are allowed to happen. b. The selected device mayor may not present data to the MPU or the MPU drives the data bus. c. The cache does not latch anything. d. The MPU finishes the cycle with the number of wait cycles indicated by the selected device.

Memory Access Cycle Type Determination Several factors affect which of the four types of memory access cycle occur: a. Read to user data space always causes a cache ignore cycle. b. Read to supervisory data space always causes a cache ignore cycle. c. Write to user data space causes a cache invalidate cycle if the cache entry addressed by the index has all of the following: 1. Both VI and V2 are true. 2. The cache tag address matches the current upper logical address from the MPU. 3. The F bit in the tag is o. Otherwise, write 'to user data space causes a cache ignore cycle. d. Write to supervisory data space causes a cache invalidate cycle if the cache entry addressed by the index has all of the following: 1. Both VI and V2 are true. 2. The cache tag address matches the current upper logical address from the MPU. 3. The F bit in the tag is 1. Otherwise, write to supervisory data space causes a cache ignore cycle.

35 MICROS YS TEMS FUNCTIONAL DESCRIPTION ®MOTOROLA

Software Considerations The operation of the cache is transparent to software in most situations. However, there are times when software must be written with the cache in mind in order to avoid stale cache problems. Below is a list of stale cache sources and possible solutions: Problem 1 - Code from main memory is cached in user space, the same main memory is written with new code in supervisory space and then the MPU attempts to execute the new code in user space or vice-versa. Solution - Flush cache before executing from the new address space. Problem 2 - Code from main memory is cached, a device other than the onboard MPU DMA's into that memory space, and then the MPU attempts to execute the new code. Solution - Flush cache before executing the new code. Problem 3 - Code from main memory is cached, the descriptors in the MMU are changed so that the logical address from where the code was cached translates to a different physical address. The MPU attempts to execute the new code at the same logical address. Solution - Flush cache when changing descriptors in the MMU. Problem 4 - The software uses PC relative reads of data (that appears as program space on the function code pins of the MPU). It writes to that data in another address space, and then it uses PC relative reads of those same logical addresses expecting to have updated information. Solution Avoid the use of PC relative instructions for data that is to be altered or flush cache after altering the data. If cache is operating in configuration d, then only one of its banks may need to be flushed in some of the above situations. Flushing the cache degrades the cache hit rate and should only be used where necessary.

4.3.4 RAM The RAM array provides eighteen 64K x 1 or 256K x 1, 150 nanosecond access time dynamic RAMs with either 128 row 2 millisecond or 256 row 4 millisecond refreshing requirements. Odd byte parity is always written to the RAM's. Parity detection is software enabled through the module control register if the hardware parity enable jumper is installed. Parity check is always performed on both the lower byte and upper byte of a word of onboard dynamic RAM whether either byte or both bytes are read.

37 MICROSYSTEMS FUNCTIONAL DESCRIPTION @MOTOROLA

4.3.4.1 Refresh. The RAM is refreshed every 30 microseconds with two RAS­ only refresh cycles. During refresh cycles, all onboard processing stops.

4.3.4.2 Local Accesses. The dynamic RAM is accessed locally starting at physical address O. The row address is strobed into the RAMs from the lower address lines when the address strobe from the MPU goes low. If the translated addresses from the MMU result in selecting the RAM, then the RAM is enabled for reading or writing data. If the RAM is not selected, the RAMs do not receive a column address strobe. This results in a RAS-only refresh cycle that completes when the MPU completes its current access.

4.3.4.3 Accesses From The VMEbus. The RAM is accessed from the VMEbus I start i ng at a base address specifi ed by the user confi gurabl e PAL. The RAM is contiguous starting at that base address.

4.3.5 Multi-Port Controller The Multi-Port Controller (MPC) resolves accessing conflicts between the MPU, VMEbus, and the onboard RAM refresh controller. It also generates the local bus time-out when the onboard MPU cannot attain VMEbus mastership within the prescribed amount of time. When the MPC receives a refresh request from the RAM refresh timer, or a VME access request to the onboard RAM, it issues a request to the onboard MPU for mastership of the on board local bus. When the MPU gives up local bus mastership, the MPC gives bus mastership to either the RAM refresh control logic or the VMEbus. In the event of simultaneous requests, refresh has the highest priority. The MPC also handles MPU/VMEbus lock conditions. The lock occurs when the onboard MPU attempts to access the VMEbus at the same time a VMEbus master attempts an access to the onboard RAM. In this case, the MPC issues a rerun handshake to the MPU. The MPU gives up mastership of the local bus at this time. If the instruction the MPU was executing is a Test and Set (TAS) , it does not rerun the cycle, but executes a bus error exception instead. It is up to the software to recover from this instruction. The software should merely RTE from such a condition. If the MPU attempts to execute a cycle on the VMEbus and the cycle is not completed within 220 microseconds, the RAM is not properly refreshed. The time required to complete a VMEbus cycle consists of the time required to obtain VMEbus mastership plus the time required for a VMEbus slave to respond once VMEbus mastership has been obtained and the MPU module strobes have been driven true on the VMEbus. Therefore, the total time from the requesting of mastership to the activation of DTACK* or BERR* by the VMEbus slave must not exceed 220 microseconds. The MPC issues a bus error to the MPU if the bus

38 MICROSYSTEMS (f!jMOTOROLA FUNCTIONAL DESCRIPTION

mastership is not obtained within the hardware selected local time-out period (Tlto). The VMEbus system controller must activate BERR* on the VMEbus if no VMEbus slave responds to the MPU module within 220 microseconds-Tlto. When there is a local bus timeout or a dual port lock on TAS the software should merely RTE.

If a local bus time-out occurs at the same time that a dual port access occurs, the MPU response may be undefined. The system should be organized such that dual port accesses do not happen at the end of long periods of withholding the VMEbus from the module. (Long period = the selected local bus time-out on the module.)

4.3.6 Bus Requester The bus requester requests VMEbus mastership on anyone of four request levels (user configurable through jumpers), and fully supports the bus grant daisy­ chain. The bus requester operates in the Release on Request (ROR) mode and requests bus mastership only if the MPU attempts a VMEbus transfer and the module does not already have VMEbus mastership.

4.3.7 Interrupt Handler The interrupt handler gives the onboard MPU the ability to sense and respond to all onboard interrupts, all seven VMEbus interrupts, VMEbus ACFAIL*/SYSFAIL*, and the ABORT switch. All the onboard interrupts and ACFAIL*/SYSFAIL*, interrupt the MPU indirectly via the MC68901. The VMEbus interrupts and the ABORT switch interrupt the MPU directly. All interrupt requests to the MPU are disabled by the IE* bit in the MCR.

4.3.7.1 VMEbus Interrupts. The VMEbus interrupts are independently routed through onboard headers to provide a means whereby the onboard MPU can selectively ignore individual VMEbus interrupts. All seven VMEbus interrupts are routed to the MPU at their original request level. For example, IRQl* requests level one interrupt to the MPU. The vector that is passed to the MPU during acknowledgement of VMEbus interrupts is the vector passed by the interrupting VMEbus slave.

4.3.7.2 ABORT Switch Interrupts. The ABORT switch interrupts the MPU on level seven. There is no vector passed during the acknowledgement of an abort. Instead, VPA is driven true, causing the MPU to use the exception table address for autovector level 7 ($7C).

The ABORT switch does not interrupt the MPU during the execution of a STOP instruction.

39 MICROSYSTEMS @MOTOROLA FUNCTIONAL DESCRIPTION

4.3.7.3 MC68901 Interrupts. All the onboard interrupts plus ACFAIL*/SYSFAIL* are routed indirectly to the MPU via the GPIO pins of the MC68901. On board serial I/O and timer interrupts are internal interrupts from the MC68901 and do not come in through the GPIO pins. All the interrupts that come through the MC68901 are funneled into one interrupt request level (level 6). The vector that is passed for each of these interrupts is partially programmable and partially fixed in the MC68901 (refer to the MC68901 Data Sheet for detail s).

4.3.7.4 Interrupt Source and Vectors. The following table summarizes all the interrupt sources on the module:

INTERRUPT SOURCE I PATH I VECTOR PASSED I EXCEPTION ADDRESS I LEVEL ------+------+------+------+------I VMEbus IRQ1* I DIRECT I FROM INTERRUPTING I 4 X VECTOR I 1 I I VMEbus SLAVE I I ------+------+------+------+------VMEbus IRQ2* I DIRECT I SAME AS ABOVE I 4 X VECTOR I 2 ------+------+------+------+------VMEbus IRQ3* I DIRECT I SAME AS ABOVE I 4 X VECTOR I 3 ------+------+------+------+------VMEbus IRQ4* I DIRECT I SAME AS ABOVE I 4 X VECTOR I 4 ------+------+------+------+------VMEbus IRQ5* I DIRECT I SAME AS ABOVE I 4 X VECTOR I 5 ------+------+------+------+------VMEbus IRQ6* I DIRECT I SAME AS ABOVE I 4 X VECTOR I 6 ------+------+------+------+------SECTION 2 (J21 2-3) IMC68901 I REFER TO MC68901 I 4 X VECTOR I 6 (NOT DEBOUNCED) / I GPIOO I DATA SHEET I I CACHEHIT* (J21 1-2) I I I I ------+------+------+------+------SECTION 1 IMC68901 I REFER TO MC68901 I 4 X VECTOR I 6 (NOT DEBOUNCED) I GPID1 I DATA SHEET I I ------+------+------+------+------VMEbus BERR IMC68901 I REFER TO MC68901 I 4 X VECTOR I 6 I GPI02 I DATA SHEET I I ------+------+------~-+------+------PARITY ERROR IMC68901 I REFER TO MC68901 I 4 X VECTOR I 6 I GPI03 I DATA SHEET I I ------+------+------+------+------MC68901 TIMER 0 IMC68901 I REFER TO MC68901 I 4 X VECTOR I 6 I I DATA SHEET I I ------+------+------+----~------+------MC68901 TIMER C IMC68901 I REFER TO MC68901 I 4 X VECTOR I 6 I I DATA SHEET I I ------+------+------+------~--+------MODE (NOT IMC68901 I REFER TO MC68901 I 4 X VECTOR I 6 DEBOUNCED) I GPI04 I DATA SHEET I I ------+------+------+------+------

40 MICROS YS TEMS FUNCTIONAL DESCRIPTION ®MOTOROI.A

------+------+------+------+------MMU IRQ* (MUST BEIMC68901 I REFER TO MC68901 I 4 X VECTOR I 6 ENABLED IN MMU) I GPI05 I DATA SHEET I I ------+------+------+------+------MC68901 TIMER B IMC68901 I REFER TO MC68901 I 4 X VECTOR I 6 I I DATA SHEET I I ------+------+------+------+------TRANSMIT ERROR IMC68901 I REFER TO MC68901 I 4 X VECTOR I 6 (SERIAL) I I DATA SHEET I I ------+------+------+------+------TRANSMIT BUFFER IMC68901 I REFER TO MC68901 I 4 X VECTOR I 6 EMPTY (SERIAL) I I DATA SHEET I I ------+------+------+------+------RECEIVE ERROR IMC68901 I REFER TO MC68901 I 4 X VECTOR I 6 (SERIAL) I I DATA SHEET I I ------+------+------+------+------RECEIVE BUFFER IMC68901 I REFER TO MC68901 I 4 X VECTOR I 6 FULL (SERIAL) I I DATA SHEET I I ------+------+------+------+------MC68901 TIMER A IMC68901 I REFER TO MC68901 I 4 X VECTOR I 6 I I DATA SHEET I I ------+------+------+------+------DTR* IMC68901 I REFER TO MC68901 I 4 X VECTOR I 6 I GPI06 I DATA SHEET I I ------+------+------+------+------ACFAIL* (J2 1-2) / IMC68901 I REFER TO MC68901 I 4 X VECTOR I 6 SYSFAIL* (J2 2-3) I GPI07 I DATA SHEET I I ------+------+------+------+------VMEbus IRQ7* I DIRECT I FROM INTERRUPTING I 4 X VECTOR I 7 I I VMEbus SLAVE I I ------+------+------+------+------ABORT* I DIRECT I NONE I $7C I 7 ------+------+------+------+------

4.3.7.5 Enabling Interrupts. VMEbus interrupts are enabled/disabled using jumpers, ABORT is enabled/disabled using a jumper, and all interrupts that come through the MC68901 are enabled in the MC68901. In addition, most of the interrupt sources must be enabled at the source such as VMEbus interrupts and MMUIRQ*. All interrupts are disabled when the IE* bit in the MCR is 1.

4.3.8 VMEbus Interface The VMEbus interface supports both master and slave modes. In either mode, the address and data paths are A24:D16. In the master mode, the MPU module is capable of initiating the following types of cycles:

41 MICROSYSTEMS FUNCTIONAL DESCRIPTION ® MOTOROLA

AM CODE FUNCTION XX Interrupt Acknowledge 3E Standard supervisory program access 3D Standard supervisory data access 3A Standard non-privileged program access 39 Standard non-privileged data access 1E, 16 These codes are in the user-defined category of the VMEbus specification and are used for fetching an alternate stack pointer and program counter after a module reset occurs with the mode switch in its I alternate position. A second switch determines what AM code is generated. 20 Short supervisory I/O access 29 Short non-privileged I/O access

In the slave mode, the interface is capable of responding to the following types of cycles: AM CODE FUNCTION 3E Standard supervisory program access 3D Standard supervisory data access 3A Standard non-privileged program access 39 Standard non-privileged data access

4.3.9 I/O and Control The serial port, timers, and module status are implemented using an MC68901 multifunction peripheral device and some additional control logic. Details of the MC68901 can be found in the MC68901 data sheet. The device is capable of generating 16 internally prioritized interrupts on one interrupt level, and passing anyone of the 16 unique vectors when the interrupt level is acknowledged. The interrupt level is fixed in hardware to level 6. When the MPU accesses even bytes in the MC68901 address space, the MPU sets no response as either DTACK* or BERR*. Consequently, the MPU hangs up, waiting until reset occurs. Do not access even bytes in the MC68901 address space.

42 MICROS Ys TEMs FUNCTIONAL DESCRIPTION ® MOTOROLA

4.3.9.1 Module Status. The status of the MPU module is available on eight signal lines that are connected to the General Purpose I/O (GPIO) pins of the MC68901. In the general case the GPIO lines are programmable as inputs or outputs. However, on the MPU module, they must always be programmed as inputs to avoid buffer fight. Some of the signal lines that are connected to the GPIO pins are steady state type status lines, while others are pulsed status lines. Table 4-1 lists the signal names.

TABLE 4-1. Module Status ======GPIO SIGNAL BIT NO. NAME DESCRI PTION COMMENTS ======o Bit 0 is high when section 2 of Section 2 is con­ S3 is open and low when it is nected only when J21 closed. 2-3 are connected. o CACHEHIT* CACHEHIT* pulses low momentarily CACHEHIT* is con­ during a cache hit cycle. It is nected only when J21 high at all other times. 1-2 are connected. 1 Bit 1 is high when section 1 of None S3 is open and low when it is closed. 2 VMEBERR VMEBERR pulses high momentarily This only occurs when when the VMEbus BERR* signal line the MPU module is goes true. It is low at all accessing the VMEbus. other times. 3 PARERR PARERR pulses high momentarily None during an onboard RAM read cycle that'results tn a parity error. It is low at all other times. 4 Mode Mode is low when the MPU module Mode is optionally is configured to fetch its reset controlled by section vectors from the VMEbus, and high 4 of S3. (open=high when it is configured to fetch and closed=low) them from onboard ROM. 5 MMUIRQ* MMUIRQ* is directly connected to None the MC68451 IRQ pin. It is low when the MC68451 generates an interrupt request. 6 DTR* DTR* is low when the terminal is DTR* is the inverse ready. DTR* is high when it is of DTR signal line not. at the RS-232C con­ nector.

43 MICROSYSTEMS FUNCTIONAL DESCRIPTION @MOTOROLA

TABLE 4-1. Module Status (cont'd) ======GPIO SIGNAL BIT NO. NAME DESCRIPTION COMMENTS ======

7 ACFAIL: ACFAIL* is the ACFAIL* signal This is only when J2 from the VMEbus. 1-2 are connected. 7 SYSFAIL: SYSFAIL* is the SYSFAIL* signal This is only when J2 from the VMEbus. 2-3 are connected. ======NOTE: Only VMEBERR, PARERR, and MMUBERR status bits are available for software monitoring. But, there are two other sources of bus errors (TAS on dual port lock and local bus time-out). The software should treat the presence of BERR exception and absence of VMEBERR, PARERR, II and MMUBERR as a "soft bus error" and should use the normal hardware recovery RTE that reruns the bus cycle. ======

4.3.9.2 Module Control Register. The MCR provides software control for various functions. The control register bits (outputs) are accessed at location F40000 and are defined as shown below:

+------+------+------+------+------+------+------+------+ I BIT 7 I BIT 6 I BIT 5 I BIT 4 I BIT 3 I BIT 2 I BIT 1 I BIT ° I +------+------+------+------+------+------+------+------+ I Wwp* I ALTCLR*I FREEZE I CACHEN I PAREN* I IE* I CTS* IBRDFAIL I +------+------+------+------+------+------+------+------+ BIT 7 - WWP*, when 0, causes faulty parity to be stored when any good onboard RAM location is written to by the MPU. When the same location is read, a parity error occurs. WWP*, when 1, allows correct parity to be written by the MPU. Correct parity is defined as being odd. BIT 6 - ALTCLR*, when 1, allows bus error to start the alternate interrupt mode. When ALTCLR* is 0, it stops the alternate interrupt mode (if in effect), and disables bus errors from starting the alternate interrupt mode. BIT 5 - When FREEZE is 1, the cache cannot be updated (except writes to cached locations invalidate then if in same FC2 space). When FREEZE is 0, cache can be updated. Note that freezing the cache does not necessarily prevent cache hits from occurring. BIT 4 - When CACHEN is 0, the cache cannot be updated and no cache hits can occur. When CACHEN is 1, cache is enabled with restrictions imposed by the FREEZE bit.

44 MICROSYSTEMS FUNCTIONAL DESCRIPTION ®MOTOROLA

BIT 3 - When PAREN* is 1, bus error exceptions can not occur because of parity errors in the onboard RAM. When it is 0, they can, if parity is enabled in hardware. BIT 2 - When IE* is 1, no interrupt requests reach the processor. When IE* is 0, interrupt requests reach the processor. BIT 1 - When CTS* is 0, the CTS line to the terminal is true. When CTS* is 1, the CTS line is to the terminal is false. BIT 0 - When BRDFAIL is 1, the SYSFAIL* line on the VMEbus is driven low by the MPU module, and the FAIL indicator is lit. When BRDFAIL is 0, the SYSFAIL* is not driven low by the MPU module.

The contents of the control register are readable at the same address. Immediately after reset, all control register bits are set to logic 1 by hardware.

4.3.9.3 Timers. Four timers are provided onboard through the MC68901, and each timer is capable of generating an interrupt. For detailed information refer to the MC68901 Data Sheet. The timers are assigned as follows: Timer C - Baud rate generator for the serial port. Timer A - Software tick timer. Timer B - Tick timer overflow/watchdog time-out. Timer D - Delay mode only - unassigned by hardware.

The watchdog time-out resets the MPU module when timer B output is set.

The XTAL input to the MC68901 is MPU clock divided by four (3.125 MHz for 12.5 MHz module and 2.5 MHz for 10 MHz module). The baud rates supported by the baud rate timer are programmable via timerC as shown below:

45 MICROSYSTEMS FUNCTIONAL DESCRIPTION ® MOTOROLA

I I 12.5 MHz MODULE 10 MHz MODULE I I I XTAL = 3.125 MHz XTAL = 2.5 MHz I IBAUD THEOR. FREQI PRE TIMER C ACT PRE TIMER C ACT I IRATE 16 X CLOCK I SCALE COUNT FREQ ERRORI SCALE COUNT FREQ ERRORI +------+------+------+ 19600 153600 I 10 1 156250 1.7 4 2 156250 1.7 1 1 I 1 14800 76800 1 4 5 78125 1.7 4 4 78125 1.7 1 1 1 1 12400 38400 1 4 10 39063 1.7 4 8 39063 1.7 1 1 1 1 11200 19200 1 4 20 19531 1.7 4 16 19531 1.7 I 1 1 1 1 600 9600 1 4 41 9527.8 4 33 9470 1.4 1 1 1 1 1 300 4800 1 4 81 4823.5 4 65 4807.2 1 I 1 1 1 1 110 1760 1 16 55 1775.9 10 71 1760.6 .031 +------+------+------+

4.3.10 ROM Two 28-pin ROM sockets for user-supplied ROM/EPROM are provided. The sockets support 4K x 8 and 8K x 8 24-pin devices, and 8K x 8, 16K x 8, 32K x 8, and 64K x 8 28-pin parts. Configurations for the devices may be chosen by jumper positions on headers. The ROM/EPROM is normally accessed as shown in the memory map in Chapter 3. However, when the module is reset, if the mode switch is in the normal position (disabled) prior to the reset, the MPU fetches its reset stack pointer and program counter from the first eight bytes of onboard ROM. Writes to ROM do not cause a bus error exception to occur.

4.3.11 Source of Bus Error Exceptions There are several sources of bus errors. Some of the sources are fatal errors while others are not. The MSR can be read to determine what source a bus error came from. All the potentially fatal error sources are status bits in the MSR. The other sources are not. When a bus error has occurred, if there are no bus error status bits set in the MSR, then the error should be treated as benign, and the bus error service routine should execute an RTE to cause a processor rerun.

4.3.11.1 VMEbus BERR. VMEbus BERR is a status bit in the MSR. This bus error exception occurs when the VMEbus BERR* signal line is driven true during a VMEbus access by the MPU module. This can only happen after the MPU module has attained VMEbus mastership.

46 MICROSYSTEMS FUNCTIONAL DESCRIPTION @MOTOROLA

4.3.11.2 On board Parity Error. Onboard parity error is a status bit in the MSR. This bus error exception occurs when a location with bad parity is encountered in the onboard RAM while parity is enabled in the MCR. Bad parity in RAM can be caused by uninitialized RAM after power-up, a write to RAM with the WWP bit true in the MCR, or by a data failure in the RAM.

4.3.11.3 Dual Port Lock on lAS Error. Dual port lock on TAS is not a status bit. This bus error exception occurs when a retry happens during the execution of a TAS instruction. This is not a fatal error and should rerun with a processor rerun.

4.3.11.4 MMU Fault. MMU fault is not a status bit in the MSR, but is available as status in the MMU. This bus error exception occurs whenever the MMU drives its FAULT* pin low.

4.3.11.5 Local Bus Time-out. Local bus time-out is not a status bit. This bus error exception occurs when VMEbus mastership is not attained in the alloted time. Local bus time-out should be rerun with a processor rerun.

If a local bus time-out occurs at the same time that a dual port access occurs, the MPU response may be undefined. The system should be organized such that dual port accesses do not happen at the end of long periods of withholding the VMEbus from the module. (Long period = the selected local bus timeout on the module.)

47 MICROSYSTEMS ([!yMOTOROLA FUNCTIONAL DESCRIPTION

II

THIS PAGE INTENTIONALLY LEFT BLANK.

48 MICROSYSTEMS 7 6 5 4 3

PI LOCAL BUS ARBITRATION BUS r- o REFRESH o HAL T,F ] DUAL PORT REQUEST RUN L.:u'S\~L. MODE SWITCHES CONTROLLER REFRESH TIM~

'------,---

DUAL PORT REQUEST

DUAL PORT RESET SWITCH CACHE MMU MAP DECODER RAM MAP DECODER

L-____-, ______r'--_____~ c L-r------r---.-- c RAM CONTROL

TRANSLATED ADDRESS BUS ADDRESS BUS ADDRESS BUS DATA BUS MPU VME BUS DATA BUS CONTROL BUS INTERFACE ,-_+----_+--~_+----_+--~----~~------~S=E~LE~C~T~B~U~S~~------~_r_r~~._-L------____-r--1~~------~'-~C~O~N~T~RO~L~B~U~S~ I - JI

o ~ SERIAL PORT. ..J INTERRUPT HANDLER, CONTROL ROM/PROM VME BUS « 1--__-1 STATUS REGISTER 1-___------REGISTER IEPROM REOUESTOR it: TIMERS UJ (/)

B B IRO AND STATUS BUS

SOFTWARE ABORT SWITCH READABLE SWITCHES

BLOCK DIAGRAM A 63DW)?Q38 REV 8 SH 2 OF 15 A 7 6 5 t 4 FIGURE 4-1. MPU Module Block Diagram 49/50 SUPPORT INFORMATION @MOTOROLA

CHAPTER 5 SUPPORT INFORMATION

5.1 INTRODUCTION This chapter provides the interconnection signals, parts list with parts location illustration, and schematic diagram for the MPU module.

5.2 INTERCONNECT SIGNALS The MPU module interconnects with the VMEbus through connector Pl.

5.2.1 Connector PI Interconnect Signals Connector PI is a standard DIN 41612 triple row, 96 pin male connector. All Motorola VMEbus specifications are met by the MPU module. Table 5-1 lists each pin connection, signal mnemonic, and signal characteristic for the I connector.

TABLE 5-1. Connector PI Interconnect Signals ======PIN SIGNAL NUMBER MNEMONIC SIGNAL NAME AND DESCRIPTION ======,======

AI-A8 000-007 DATA bus (bits 0-7) - eight of 16 three-state bidirectional data lines that provide the data path between VMEbus master and slave. A9 GND GROUND AID Not used. All GND GROUND A12 DS1* DATA STROBE 1 - signal driven by VMEbus master that indicates a data transfer on data bus lines 008-015. A13 DSO* DATA STROBE 0 - signal driven by VMEbus master that indicates a data transfer on data bus lines 000-007. A14 WRITE* WRITE - signal driven by VMEbus master that specifies the direction of data transfers. A15 GND GROUND

51 MICROSYSTEMS SUPPORT INFORMATION ®MOTOROLA

TABLE 5-1. Connector PI Interconnect Signals (cont'd) ======PIN SIGNAL NUMBER MNEMONIC SIGNAL NAME AND DESCRIPTION ======Al6 DTACK* DATA TRANSFER ACKNOWLEDGE - signal driven by VMEbus slave that indicates that valid data is available on the data bus during a read cycle, or that data has been accepted from the data bus during a write cycle. Al7 GND GROUND Al8 AS* ADDRESS STROBE - the falling edge of this signal,driven by VMEbus master, indicates a valid address is present on the address bus. Al9 GND GROUND A20 IACK* INTERRUPT ACKNOWLEDGE - signal driven by the I VMEbus master that indicates a VME interrupt acknowledge cycle. A VME master has been interrupted on one of seven levels and is now acknowledging the specific interrupt with a service routine. A21 IACKIN* INTERRUPT ACKNOWLEDGE IN - IACKIN* and IACKOUT* form a daisy-chained acknowledge. The IACKIN* signal is connected directly to IACKOUT*. A22 IACKOUT* INTERRUPT ACKNOWLEDGE OUT - IACKIN* and IACKOUT* form a daisy-chained acknowledge. The IACKOUT* signal is connected directly to IACKIN*. A23 AM4 ADDRESS MODIFIER (bit 4) - one of the three-state lines driven by VMEbus master that provide additional information about the address bus, such as size, cycle type, and/or data transfer bus master identification. A24 A07 ADDRESS bus (bit 7) - one of 23 three-state lines driven by VMEbus master that specify an address in the memory map.

A25 A06 ADDRESS bus (bit 6) - same as A07 on pin A24. A26 A05 ADDRESS bus (bit 5) - same as A07 on pin A24. A27 A04 ADDRESS bus (bit 4) - same as A07 on pin A24. A28 A03 ADDRESS bus (bit 3) - same as A07 on pin A24. A29 A02 ADDRESS bus (bit 2) - same as A03 on pin A28.

52 MICROSYSTEMS SUPPORT INFORMATION ® ItIIOTOROLA

TABLE 5-1. Connector PI Interconnect Signals (cont'd) ======PIN SIGNAL NUMBER MNEMONIC SIGNAL NAME AND DESCRIPTION ======A30 AOI ADDRESS bus (bit 1) - same as A03 on pin A28. A31 -12 VDC -12 Vdc Power - used by the logic circuits on the MPU module. A32 +5 VDC +5 Vdc Power - used by the logic circuits on the MPU module. Bl BBSY* BUS BUSY - this signal is driven low when the MPU module is the bus master. B2 Not used. B3 ACFAIL* AC FAILURE - Input signal that indicates a power failure has occurred. I B4 BGOIN* BUS GRANT (bit 0) IN - bus-grant-in and bus-grant-out a daisy-chained bus grant. A grant received at the jumpered level indicates the MPU module may become the bus master. The remaining three bus-grant-in lines are connected directly to their respective bus-grant-out lines. B5 BGOOUT* BUS GRANT (bit 0) OUT - bus-grant-in and bus-grant-out form a daisy-chained bus grant. When a bus-grant-in is received at the jumpered level and the MPU is not awaiting bus mastership, the bus-grant-out signal is true on the respective 1evel . B6 BGlIN* BUS GRANT (bit 1) IN - same as BGOIN* on pin B4. B7 BGlOUT* BUS GRANT (bit 1) OUT - same as BGOOUT* on pin B5. B8 BG2IN* BUS GRANT (bit 2) IN - same as BGOIN* on pin B4. B9 BG20UT* BUS GRANT (bit 2) OUT - same as BGOOUT* on pin B5. BI0 BG3IN* BUS GRANT (bit 3) IN - same as BGOIN* on pin B4. B11 BG30UT* BUS GRANT (bit 3) OUT - same as BGOOUT* on pin B5.

53 MICROSYSTEMS SUPPORT INFORMATION ® MOTOROLA

TABLE 5-1. Connector PI Interconnect Signals (cont'd) ======PIN SIGNAL NUMBER MNEMONIC SIGNAL NAME AND DESCRIPTION ======BI2-BIS BRO*-BR3* BUS REQUEST (0-3) - the bus request at the jumpered level is true when the MPU requires bus mastership. When one or more bus request lines is true in the ROR mode, bus mastership is released. B16-B19 AMO-AM3 ADDRESS MODIFIER (bits 0-3) - same as AM4 on pin A23. B20 GND GROUND B21,B22 Not used. B23 GND GROUND B24-B30 IRQ7*­ INTERRUPT REQUEST (7-1) seven prioritized I IRQl* interrupt request inputs. Jumper enabled, level seven is the highest priority. B31 Not used. B32 +S VDC +S Vdc Power -same as +S VDC on pin A32. CI-C8 D08-DOIS DATA bus (bits 8-1S) - eight of 16 three-state bidirectional data lines that provide the data path between VMEbus master and slave. C9 GND GROUND CI0 SYSFAIL* SYSTEM FAIL - signal driven by the MPU module when fail bit is true in MCR. Also can be monitored in MSR. Cll BERR* BUS ERROR - an active low signal driven by VMEbus slave that indicates an error has occurred during a data transfer cycle. C12 SYSRESET* SYSTEM RESET - the system controller provides this input signal that causes a module level reset on the MPU module.

S4 MICROSYSTEMS SUPPORT INFORMATION ®MOTOROLA

TABLE 5-1. Connector PI Interconnect Signals (cont'd) ======PIN SIGNAL NUMBER MNEMONIC SIGNAL NAME AND DESCRIPTION ======C13 LWORD* LONGWORD - not driven. This terminated signal remains at a high level when the MPU module is bus master. The dual port RAM does not respond to VMEbus accesses when LWORD* is true. C14 AM5 ADDRESS MODIFIER (bit 5) - same as AM4 on pin A23. C15 A23 ADDRESS bus (bit 23) - same as A07 on pin A24. C16 A22 ADDRESS bus (bit 22) - same as A07 on pin A24. C17 A21 ADDRESS bus (bit 21) - same as A07 on pin A24. C18 A20 ADDRESS bus (bit 20) - same as A07 on pin A24. C19 A19 ADDRESS bus (bit 19) - same as A07 on pin A24. I C20 AlB ADDRESS bus (bit 18) - same as A07 on pin A24. C21 A17 ADDRESS bus (bit 17) - same as A07 on pin A24. C22 A16 ADDRESS bus (bit 16) - same as A07 on pin A24. C23 A15 ADDRESS bus (bit 15) - same as A07 on pin A24. C24 A14 ADDRESS bus (bit 14) - same as A07 on pin A24. C25 A13 ADDRESS bus (bit 13) - same as A07 on pin A24. C26 A12 ADDRESS bus (bit 12) - same as A07 on pin A24. C27 All ADDRESS bus (bit 11) - same as A07 on pin A24. C28 AI0 ADDRESS bus (bit 10) - same as A07 on pin A24. C29 A09 ADDRESS bus (bit 9) - same as A07 on pin A24. C30 A08 ADDRESS bus (btt 8) - same as A07 on pin A24. C31 +12 VDC +12 Vdc Power - used by the logic circuits on the MPU module. ======

55 MICROSYSTEMS SUPPORT INFORMATION ®MOTOROLA

5.2.2 Terminal Port Connector Jl Interconnect Signals A standard RS-232C cable mates with connector J1. Refer to Appendix A for detailed information on RS-232C interfacing. Table 5-2 lists each pin connection, signal mnemonic, and signal characteristic for the connector. The VME120 has only a partial RS-232C implementation. No facility is provided to connect it to a modem. As wired, it provides permanently true Data Set Ready (DSR), Data Carrier Detect (DCD) signals, and a programmable CTS signal. This allows the system to tell the terminal when it is ready to transmit data. The VME120 also can detect a Data Terminal Ready (DTR) signal, that can be controlled by software to clear buffers or send a message, if desired. CTS is controlled by bit 1 of the module control register at F40000, and DTR is sensed by bit 6 of the IPRA in the MK68901 peripheral chip. Refer to Mostek data sheet for details.

TABLE 5-2. Connector Jl Interconnect Signals ======PIN SIGNAL NUMBER MNEMONIC SIGNAL NAME AND DESCRIPTION I ======1 Not used. 2 TxD TRANSMIT DATA - data to be transmitted is furnished on this line to the MVME120. 3 RxD RECEIVE DATA - data from the receive line is presented to the terminal. 4 Not used. 5 CTS CLEAR TO SEND - CTS is a function supplied to the terminal by the MVME120, that indicates that it is permissible to begin transmission of a message.

6 DSR DATA SET READY - DSR is a function supplied by the MVME120 to the terminal to indicate that the MVME120 is ready to transmit data. 7 SIG-GND SIGNAL GROUND - common return for all signals. 8 DCD DATA CARRIER DETECT - furnished by the MVME120 to the terminal to enable its receive circuits. 9-19 Not used. 20 DTR DATA TERMINAL READY - a signal from the terminal to the MVME120 indicating that the terminal is ready to send or receive data. 21-25 Not used. ======

56 MICROSYSTEMS SUPPORT INFORMATION ®MOTOROLA

5.3 PARTS LIST Table 5-3 lists the components of the MPU module. The parts locations are illustrated in Figure 5-1. Parts listed are for all versions unless otherwise noted. These parts reflect the latest issue of hardware at the time of printing.

TABLE 5-3. MPU Module Parts List ======REFERENCE MOTOROLA DESIGNATION PART NUMBER DESCRI PTI ON ======84-W8293B01 Printed wiring board CR1 48NW9616A03 Diode, 1N4148/1N914 C1,C6,C26, 23NW9618A71 Capacitor, electrolytic, 47 uF @ 10 Vdc C28,C67,C71 C2,C4,C5, 21NW9632A03 Capacitor, fixed, ceramic, 0.1 uF @ 50 Vdc I C7-C17,C19- C22,C24,C25, C27,C29-C49, C51-C53,C55- C66,C68 C23 23NW9704A99 Capacitor, tantalum, 33 uF @ 15 Vdc DLl 01NW9804C33 Delay module, triple, 40 ns DL2 01NW9804C12 Delay module, triple, 20 ns DL3 01NW9804c34 Delay module, triple, 70 ns DS1,DS2 48NW9612A49 Indicator, LED, red DS3 48NW9612A59 Indicator, LED, green J1 28NW9802F88 Connector, 25-pin J2,J9,J17 , 28NW9802D04 Header, single row post, 3-pin J21,J24 J3,J4 28NW9802C63 Header, double row post, 12-pin J5,J6,J20 28NW9802D01 Header, double row post, 2-pin J7 28NW9802C36 Header, double row post, 14-pin

57 MICROSYSTEMS ®MOTOROLA SUPPORT INFORMATION

TABLE 5-3. MPU Module Parts List (cont'd) ======REFERENCE MOTOROLA DESIGNATION PART NUMBER DESCRIPTION ======J8 28NW9802B34 Header, double row post, I6-pin J22 28NW9802C43 Header, double row post, 8-pin J25 28NW9802B2I Header, double row post, 6-pin PI 28NW9802E5I Connector, 96-pin R1 51NW9626A37 Resistor network, 9/10k ohm R2 06SW-124A18 Resistor, fixed, film, 51 ohm, 5%, 1/4 W R3,R4 06SW-124A23 Resistor, fixed, fi 1m, 82 ohm, 5%, 1/4 W I R5 06SW-124A25 Resistor, fixed, film, 100 ohm, 5%, 1/4 W R6 06SW-124A97 Resistor, fixed, film, lOOk ohm, 5%, 1/4 W R7,R2l,R23, 5lNW9626A49 Resistor network, 7/10k ohm R25 R8,R29 5lNW9626A22 Resistor network, 5/10k ohm R9 51NW9626A4l Resistor network, 9/4.7k ohm RIO 51NW9626B55 Resistor network, 9/4.7k ohm Rll 5INW9626B52 Resistor network, 5/l0k ohm R12 51NW9626A63 Resistor network, 5/2.2k ohm R13 51NW9626B56 Resistor network, 9/l0k ohm R14 5lNW9626B51 Resistor network, 5/lk ohm R15 5lNW9626B49 Resistor network, 9/l5k ohm R16 06SW-124A17 Resistor, fixed, film, 47 ohm, 5%, 1/4 W R17 29NW9805B44 Jumper, 2-pin male R18 5lNW9626B50 Resistor network, 3/47 ohm R19,R20 51NW9626B48 Resistor network, 5/47 ohm R22 06SW-124A73 Resistor, fixed, film, 10k ohm, 5%, 1/4 W R24,R26 06SW-124A4l Resistor, fixed, fi 1m, 470 ohm, 5%, 1/4 W

58 MICROS YS TEMS ([!jMOTOROLA SUPPORT INFORMATION

TABLE 5-3. MPU Module Parts List (cont'd) ======REFERENCE MOTOROLA DESIGNATION PART NUMBER DESCRIPTION ======R27,R28 06SW-124A83 Resistor, fixed, film, 27k ohm, 5%, 1/4 W R30 06SW-124A42 Resistor, fixed, film, 510 ohm, 5%, 1/4 W SI,S2 40NW9801A54 Switch, push, momentary SPOT S3 40NW9801B29 Switch, piano, 4 position, SPST Ul,U45,U46 51NW9615K66 I.C. 74F32PC U2,U5,UI0, 51NW9615G07 I.C. SN74S244N U19 U3,U8 51NW9615Hll I.C. SN74LS645N U4,U9 51NW9615G47 I.C. MC6882L I U6 51NW9615F79 I.C. SN74S240N U7 (NOTE) I.C. programmed Ull, U18 51NW9615F85 I.C. SN74S38N U12 51NW9615N76 I.C. SN74LS652NT U13,U14 51NW9615K98 I.C. 74F280PC U15 51NW9615G38 I.C. SN74LS38N U16 (NOTE) I. C. programmed U17,U22 51NW9615K18 I.C. 74F373PC U20 51NW9615E93 I. C. SN74LS14N U21 (NOTE) I. C. programmed U23 51NW9615C30 I. C. SN74LS193N U24,U29,U32 51NW9615R26 I.C. SN74ALS645-1N U25,U66,UI0l 51NW9615K73 I.C. 74FOOPC U26 51NW9615N04 I.C. MC68451RI0 (used on 120, 121) U26 01-W3288BOI MMU bypass (used on 122, 123) U27 51NW9615N03 I.C. MC68010RI0 (used on 120, 121)

59 MICROSYSTEMS SUPPORT INFORMATION @MOTOROLA

TABLE 5-3. MPU Module Parts List (cont'd) ======REFERENCE MOTOROLA DESIGNATION PART NUMBER DESCRIPTION ======U27 51NW9615Rll I. C. MC68010R12 (used on 122, 123) U28 (NOTE) I.C. programmed U30,U33,U36, SlNW9615J39 I.C. 74F74PC U43,U64,U72, U76,U77,U81, U82,U87,U93, U99, UlOO, U106 U31 (NOTE) I.e. programmed U34 (NOTE) I.e. programmed I U3S SlNW9615N40 I.C. MC68901 U37 51NW9615F30 I.C. DM74S05N U38 SlNW961SD93 I.C. SN74S30N U39 (NOTE) I. C. programmed U40 (NOTE) I. C. programmed U41,U49 SlNW9615H79 I.C. TMM2016P-1 (used on 120, 121, 123) U42,U83,U9S, SlNW9615K70 I.C. 74F08PC U107 U47 SlNW961SL74 I. C. 74Fl63PC U48,U59 SlNW961SN32 I. C. 74F164PC U50,US1,U53 51NW961SN4S I.C. 74F257PC US4 SlNW961SK6S I. C. 74F64PC USS,U70 SlNW961SK71 I. C. 74F04PC US6 (NOTE) I. C. programmed US7 SlNW961SK69 I. C. 74F10PC US8,U88 SlNW961SK72 I. C. 74F92PC

60 MICROS YS TEMS SUPPORT INFORMATION ® MOTOROLA

TABLE 5-3. MPU Module Parts List (cont'd) ======REFERENCE MOTOROLA DESIGNATION PART NUMBER DESCRIPTION ======U60,U67,U73, 51NW9615N43 I.C. TMS2150-5JL (used on 120, 121, 123) U78,U84,U90, U96,U102 U61,U62,U68, 51NW9615M09 I.C. MCM6665AP15 (used on 120, 122) U69,U74,U75, U79,U80,U85, U86,U91,U92, U97,U98,U103, U104,U109, UllO U61,U62,U68, 51NW9615P38 I.C. HM50256-15 (used on 121, 123) U69,U74,U75, U79,U80,U85, U86,U91,U92, I U97,U98,UI03, U104,UI09, UllO U63 51NW9615N47 I.C. MC3488API U65 51NW9615F38 I.C. SN74LS393N U7l 51NW9615K67 I.C. 74F20PC U89 51NW9615K68 I.C. 74F11PC U94 51NW9615D26 I.C. SN74S113N U105 51NW9615B30 I. C. MC1489AP U108 (NOTE) I. C. programmed VI 48AW1068B03 Crystal oscillator, 20.0 MHz (used on 120, 121) VI 48AW1015Bll Crystal oscillator, 25.0 MHz (used on 122, 123) 09NW9811A78 Socket, DIL, 20-pin (use at U7,UI6,U21,U28,U31,U40,U56,UI08) 09NW9811A7l Socket, PGA, 68-pin (use at U26,U27)

61 MICROSYSTEMS SUPPORT INFORMATION @MOTOROLA

TABLE 5-3. MPU Module Parts List (cont'd) ======REFERENCE MOTOROLA DESIGNATION PART NUMBER DESCRIPTION ======09NW9811BOI Socket, OIL, 24-pin (use at U34,U39) 09-W4659B24 Socket, 24-pin (use at U35) 09-W4659BI2 Socket, I2-pi n (use at U4I,U49) 09-W4659BI4 Socket, I4-pin (use at UX44,UX52) 09NW98IIA46 Socket, crystal, 4-1ead (use at YI) I 55NW950IAI2 Handle 64-W4736BOI Panel, front 29NW9805BI7 Jumper, shorting, insul ated (use at J2-J9, JI7,J20,J24,J25) ======NOTE: When ordering, use number labeled on part. ======

62 MICROSYSTEMS SVtl3.LSA SOHOIVtl £9

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"..,OI:lO.LOW NOI1VW~OjNI l~Oddns GiJ @MOTOROLA SUPPORT INFORMATION

5.4 SCHEMATIC DIAGRAMS FIGURE 5-2 illustrates the schematic diagram for the MPU module.

I

64 MICROS YS TEMS 7 6 5 4 3

NOTES: & TABLE I & TABLE I CON'T 1. FOR REFERENCE DRAWINGS REFER TO REF REF BILL

A 63DW3293B RFV E SH OF 15 A 7 6 5 t FIGURE 5-2. MPU Module Schematic Diagram 65/66 7 6 5 4 3

PI LOCAL BUS, ARBITRATION BUS II .. D r--__1.L----_._ D REFRESH DUAL PORT REQUEST HAL T,F'\IL, MODE SWITCHES RUN L:::D'S J CONTROLLER REFRESH TII:'R l

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DUAL PORT REQUEST

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DUAL PORT [ESET SWITCH CACHE MMU MAP DECODER RAM J l MAP DECODE~__ rL--______--' c -[ - c RAM CONTROL

TRANSLATED ADDRESS BUS ADDRESS BUS ADDRESS BUS DATA BUS MPU VME BUS 1-__------_.+-_....;D;;..;A.;..;T:..:.A.:.....::B;..;;U~S_-1 -'. CONTROL BUS INTERF ACE VI ~ ~--+ __--+--+--+----+-""'~'-}o---~SE~L~E~C~T~B..;;::U~S=+"'-_---+_-+---+ __~I- __+- ___ ,_-~ ___~~~~~~ ..·--- ...:---.:--1----+t---ft- .....-\-- ....~~i"----1-L ______-r--.J'------.-, r- .. .~, ) ,--...:C;.;:O;.;.;N:..:.T..;.;R..;;::O.::.L_...=.BU;;.;S~ ID lLJ ~ I'------, > JI + r-

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SOFTWARE ABORT SWITCH READABLE SWITCHES

BLOCK DIAGRAM A 63DW)2~3B REV 8 SH 2 OF 15 A FIGURE 5-2. MPU Module Schematic Diagram 67/68 7 6 5 t 7 6 5 4 3

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NC ".- A 63DW 32938 REV SH 3 OF 15 A FIGURE 5-2. MPU Module Schematic Diagram 69/70 7 6 5 t 7 6 5 4 3

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" 16 [0] BUS 4C3 ~ ~ ~ ~ ! " " 9 ~ ~ ~ ~ e B B " tRLPARl 1187 r.:;--- U62 r::;-- U69 r.:;-- U75 r::;-- UBt' r.:;-- UB6 r.:;-- U92 r:;-- U98 r::;-- UI04 UII0 12 14 MCM6256 12 f4 MCM6256 12 14 MCM6256 12 14 MCM6256 12 ,14 MCM6256 12 14 MCM6256 12 14 MCM6256 12 14 MCM6256 2 14 MCM6256 r-'---'--, ~I 5 01 DO [RA J 5 01 DO [RAIJ 5 01 DO ( tA 5 01 DO ~A';"!"~J_~~ 01 DO :RA 5 01 DO :A01 5 OJ DO [RA! 5 01 DO [ JJ ~ 01 DO 1~~:A~--t-+-'!!!-1A0 :RJ 7 A0 [RA 7 A0 tA 7 A0 ~!~A';---k-rlA0 RA 7 A" 1-*:!:~Af---*--I7 A" [R A 7 A" A" I~~:~~~-+-HAI :R, 6 AI lRA2: 6 AI tA 6 Al !A2: AI :A 6 Al ~:~A.---*-I6AI eRA 6 Al ~~;---k--lA 1 ~~~~~~=~~~1~2~A2 R 12 A2 RA3J 12 A2 tA.; 12 A2 ~"?A~3!---:,~A2 :A 12 A2 ~:~A~) ----,,~2c-1A2 RA 12 A2 ~~~-;,~A2 I' 1 A3 1 A3 tA4 A3 tA A3 ~7l'*"4--'~A3 :A 1 A3 ~:~A~~,~A3 I A3 ~~"--~,~A3 l~r~~~HI~0A4 10 A4 tA5: 10 A4 ~t~A~'1~0A4 ~~.~5:-.~A4 :A 10 A4 w.lR~Af--,H.0rl A4 10 A4 ~r::iff-~IH.-lA 4 1~~~-H~:54A5 Ie 13 A5 tA6:1J. A5 tAl3 A5 t1~~l~B:~=j,~=:A5 tAe 13 A5 ~[~R:"?,A\~€~~3-lA5 13 A5 ~~~""'1f.!3'-~A5 r+!~~~f-19~A6 7 9 A6 tA 7 9 A6 RA 7 9 A6 r. 7 A6 RA 9 A6 H[~R:~JA!--~'-i A6 7 9 A6 ~~7~~9'-iA6 1'!!.~;t--~I-+~A7 IB A7 RA8: I A7 [RA8 A7 ~~l*8:--+1rlA7 :RA I A7 H[~R:~JA~~~A7 lB: I A7 Hr~\*8---'f-,-lA 7 A8 12C3 [RW*] 3 A8 ,...[=RW,*.....fJ--'-1 3 A8 (RW*] 3 ~B [RW*]:5 AB [RW*] j- ~8 tRW*] 3 I [RW*J 3 AB tRW*J 3 ~8 [RW*J 3 AB 9C3 lRAS* 4 L :RAS* 4 L lRAS* 4 fu lRAS* 4 L Hl~R~-¥,AI~:S,*t..-74rlfu :RAS* 4 L w.lR~AI~Si*'--"'14~~ RAS* 4 fu lRAS* 4 L ~ BAS. 9C3 :AS* ~ Ws :AS* 15 ffi :AS* 15 CAS :AS* 15 Ws .CAS* 15 CAS :AS*1J5 CAS :AS* 15 CAS .CAS* 15 CAS .CAS* 15 CAS

A 63DW32938 REV 8 SH 10 OF i~ A 7 6 5 t FIGURE 5-2. MPU Module Schematic Diagram 83/84 7 6 5 4 3

----.-. _------!M..Q.lli IS07

· ..... --~~----'~ ISC7 D --~.\r------· :iT2IO D + v ~(~C~3--· 10K R21C +5V I 5 10K [ ~"ill. --.~ IS07 R23A J24 15 +5V~4 __ ..-lY-Mf:VECT*] I"K 6~ 707 2 ~I U4SA R21E F32 10K UI9 I .r.-,::,,::, + 5V~-- S24't PI-CI~ 2] ~ --- I - S II 9 AMS 1 9831.YECT *1 ______------. 16 AM3 ~J 1583 18 IACK* .U·\c.l<~L ~ - --+ ~ 8B7 17 3 LWORO* TAIS] 3 .-~ 887 ·AI7] RIC 14 AM4 PI-A23 U38 [> ·A 8] 2 I"K [FC2.l I 5.. AM 2' ~._ PI-B18 +5V ----.-J AMI - P -B17 TAl 9] I 4 I - ~"8 [ C!l.... __ 2 AM" PI-BIS . [TA2"] 11 .-- r ~: .- TA2 ~ c----/ E 19 TA22] S E TA23] 5 '§.. ~. """,,----AM. ~ 887 70J lTh1..JEi ~ '\.8 c c " 4B3 w;,1 BUS '\. 3 _. \ 13B3 [VMEAV*]

4C3 .....I3!,JS ~, ,. .... ". ill UI3 ,...----F280 +SV 000] I + ~V D"ll 2 102] 4 [WI.P';Bl ODD ~ -- ~ I 03 10C3 RI2E I 04 RI0C 22"" UISO 105: R21F S 4700 '06] I 10K U2"8 " EVEN ~i +5V 1i-~8 4 07] 12 I 7 3 [WW~*l 3~\ 131 1)11 .. 7B3 --.-- V" '\ 8 [RLPAR] I' UI4 US88 10B3 ~ I U4SC F280 6,£.!2 )"8] 1 .4 9-. Q.2 + ~V HI9: 2 8 ~U~8RJ;;RBj 10] 4 l.ad '\. ~- 907 ODD J I !'- [WHPARl I I 1 H ~ 1"83 RII8 UISC 0 47"0 1 I 2 J13 U37C EVEN 5 3 S 2 I ON - 1fl)9 .8 3 PARITY EN ~S6 ~ [RHPAR] I I"C3 [RAMGC 9B3 -" .. _. U64A B 12C3 [RAMWRTE*l U2S0 14 F74 B ... PR [PARERR*] 2 0 a S ~ 807 U2"0 :OLL LSI4 3 a c6 [PARERRl (P8RJ;;N*] U42A CK 407,IS07 7B3 ~ 9~8 1·- OL2C CLR (RASIS"] F"8 20NS 9C3 ~ (RC] 3 5 8 I r 2 .J 403 ~ ~ (DPC~ONJ;;*l U.!Ul:!8~RR*l 12C3 ~ - ~ 887 U648 U4S8 F74 5~ PRb" PI-CII "- \..6 t2 0 / ~~~RI6!1!*l 4l a 9 U18A 9C3 ~ ----/ (MPUCI.KJ n .8 2~ 403 ~ CK a I BERR* CLR ILl) 3 12C7 r3 A 13C3 CPU A] 63DWj2938 REV 8 SH 11 OF 15 A 7 6 5 t FIGURE 5-2. MPU Module Schematic Diagram 85/86

7 6 5 4 3 IlIi'OUn. rJ-II~ ) r-______~~J!(J~

7 ••'.J I , • "8 I IIGlotlT" PI-In !'l-RA ACl.-tN" o D "' !>1-1I11 IIGlINII I I'~ I IIC?OIlT* PI-II11

I 11 J4fi] I ~ ~ IIC:50UT* PI-1I11 ./ ,PI-AI! IICl?TN. ~ "- > "~2~ PI-BI' BG:]IN. II I I .. tPu Cl ee? UIIH I UIIIIB I I S24_~ ! <,FIt I I ! hi I, I, 5D" I V I , I, +fV [DR*) I IS7 i U71A L' F74 i I '1R13J uasc uno I I U83A I I I. FIe F.4 ! ~I-BI'" 1111_. i 2~5!O Q, ! ua2B I·Ilfl( I c I FIe I I [BIISYl ! I ' , I 807 i ' e nl F74 I • c LJ~ n 3 J '" CI< ob e J rv I . , I",>, c; U' 8B I uaec I i C'~R I ~ ~ ~ s3e I ~o PR o~ £.~\ ...-.; R2JE r ______-'- __...L1 ~I~IOo-CK o~ ~JTi'f-'e,,--_'--:L{J)p:e5l..-r-1+ __..JBUiBLilS~X*!!.__'fEJ!.::..- B;uly),

7C3 rYMEBUSJ I j .. : va3e ~

.. 83 tRESEHtl ... LI

683 [BRAV)

• tYMEAY7'1 1287,687 B B • tYMEAYI eC7,12B? • tYMEAY*1 ItC7.12B7

• [AS!*l7C7

63DW3293B REV E SH 13 OF 15, A A FIGURE 5-2. MPU Module Schematic Diagram 89/90 7 6 5 t 7 6 5 4 I 3

D D

4B3[A1 BUS , Q

703 fT A1 BUS '-- 7 " , 3 , 8 t-- t-- , 1 , 18 [m RUe:: 4C3 (P271 f'. "' , 2 (P261 f'. ~? fTA14J XU52 + V , 2 ~.4t=-=-~~",u.:u_-/] ~ (PIJ 1 SOCKET +5V 6 V 7 ·AI5: r-+------h...... ,=------~2 VPP VCCf-! 7 P 7 " ~[~AI~6:J!__-----_'!!3~ A12 PGM:~[§:-l:------l!l=P~~--+--I ~~A~7~Jf__-----..:;J:4~ A 7 NC~17-5------l;';;A~~-----1 ,[T A 13] ~_"""\:,~~!:--_1-,,-'T.1..j-'i-Pr!'~~ITf-:J-+---" ~A~6J!__-----~A6 A8·~¥4---~"A~f----+-~4-~ :A 15J A5 A9~.,;_--""'!O_:!_:!iP"l-!-~--+--~1 ~~~=uAI6~:J ______4-~r .~6 ____-+ ___ ~~ ~:~AI~4-----~~A4 c ~A*0~3J~-----~A3 "A c ~:~A0'~2J!------'!!--l A2 P? 0' ~A~~ll~------~Al 9 07 """''''"*0-=00.--:-----l:¥-l A0 07 18 )06 r.'(~[D~0~ll..__---____lI~ 00 06 17 )05 '8 02 01 05 16 '041 '" 02 04 " ~~~G~N~0~~0~3r~II~~--~~0~01~3-t-t-t-r-t--t/1

, 3 [P201 [P23J + V r---r--~-~--~-~--~.. --- 1 1 1 1 I 1 1 1 , 2 , " 16 RIH RIF r,10 < RIA RIJ RIG R1E < RIB f'. f'. f'. 10K 10K 10K 10K 10K 10K 10K 10K +5V 9 7 5 2 10 8 6 XU44 SOCKET : ~ ~ ~ :0 CD;:;: [Pll Ci ~ ~ 8 & ~ ~ ~ '---_-'[.... P.... 2L...... J ___-+ ...... =c-- _____~vpP VCC~ 7 [P27J ~ ;:;;:; e;::;:; _ [A '8: A12 PG MH<'7<------J[;-!.P~216Jf--+-+-4--l ~--~----~--~----~--~----~--~~--, ~[~AI~7J~-----~A7 NC~~------l[~AI0~9!--+-~ ~~~.~6J!------~A6 A81~~--~~·A~I~0~-+--~f--J "[""A~5"'J-----~f--< A 5 A91H::.;;------"-;~P~2L¥f-3J --+-+--..../1 ~~(~A~~-----~A4 2 +!V ,"[~A~J-----~~A3 'A , 8 ~~(~A~-----~9~A2 !0 P20 1 1 1 1 1 1 1 1 f' [A0 J 10 Al 19 ('DI5J "[;;;:)~0fJ...------¥.'-1 A0 07 18 [ 14J R15E "RI5G R15H R15F ?R150 )oR15A '>RI5B R15e /,[~0*9f-J------+2:!:-1011 06 013 15K 15K 15K 15K 15K 15K 15K 15K '[0101 13 01 D5 (1112J 1~~L------~~02 04 .u.~ 8 9 7 5 2 14 GNO 03 15 [0111 B & :: ;;:, B ;::C ;::c e , 18 "' 16

7C3 [ROMEN*J

'- A 63DW32938 REV 8 SH 14 OF 1~ A FIGURE 5-2. MPU Module Schematic Diagram 91/92 7 6 5 t

APPENDIX A @MOTOROLA

APPENDIX A RS-232C INTERCONNECTIONS

The RS-232C standard is the most widely used interface between terminals and computers or modems, and yet it is not fully understood. This is because all the lines are not clearly defined, and many users do not see the need to conform for their applications. A system should easily connect to any other. Many times designers think only of their own equipment, but the state-of-the­ art is computer-to-computer or computer-to-modem operation. The RS-232C standard was originally developed by the Bell System to connect terminals via modems. Therefore, several handshaking lines were included. In many applications these are not needed, but since they permit diagnosis of problems, they are included in many applications. Table 1 lists the standard RS-232C interconnections. In order to interpret this information correctly it is necessary to know that RS-232C is intended to connect a terminal to a modem. When computers are connected to computers without modems, one must be configured as a terminal and the other as a modem. Because computers are normally configured to work with terminals, they are said to be configured as a modem. Also, the signal levels must be between +3 and +15 volts for a high level, and between -3 and -15 volts for a low level. Any attempt to connect units in parallel may result in out of range voltages and is not allowed by the RS-232C specification.

TABLE 1. RS-232C Interconnections ======PIN SIGNAL NUMBER MNEMONIC SIGNAL NAME AND DESCRIPTION

======~======:======

1 Not used. 2 TxD TRANSMIT DATA - Data to be transmitted is furnished on this line to the modem from the terminal. 3 RxD RECEIVE DATA - Data that is demodulated from the receive line is presented to the terminal by the modem. 4 RTS REQUEST TO SEND - RTS is supplied by the terminal to the modem when required to transmit a message. With RTS off, the modem carrier remains off. When RTS is turned on, the modem immediately turns on the carrier.

95 MICROSYSTEMS APPENDIX A ®MOTOFlOLA

TABLE 1. RS-232C Interconnections (cont'd) ======I PIN SIGNAL NUMBER MNEMONIC SIGNAL NAME AND DESCRIPTION ======5 CTS CLEAR TO SEND - CTS is a function supplied to the terminal by the modem that indicates that it is permissible to begin transmission of a message. When using a modem, CTS follows the off-to-on transition of RTS after a time delay.

6 DSR DATA SET READY - DSR is a function supplied by the modem to the terminal to indicate that the modem is ready to transmit data. 7 SIG-GND SIGNAL GROUND - Common return line for all signals at the modem interface. 8 DCD DATA CARRIER DETECT - Sent by the modem to the terminal to indicate that a valid carrier is being received. 9-14 Not used. 15 TxC TRANSMIT CLOCK - This line clocks output data to the modem from the terminal. 16 Not used. 17 RxC RECEIVE CLOCK - This line clocks input data from a terminal to a modem. 18,19 Not used. 20 DTR DATA TERMINAL READY - A signal from the terminal to the modem indicating that the terminal is ready to send or receive data. 21 Not used. 22 RI RING INDICATOR RI is sent by the modem to the terminal. This line indicates to the terminal that an incoming call is present. The terminal causes the modem to answer the phone by carrying DTR true while RI. 23 Not used. 24 TxC TRANSMIT CLOCK - Same as TxC on pin 15.

96 MICROS YSTEMS ®MOTOROLA APPENDIX A

TABLE 1. RS-232C Interconnections (cont'd) ======~======I PIN SIGNAL NUMBER MNEMONIC SIGNAL NAME AND DESCRIPTION ======25 BSY BUSY A positive EIA signal applied to this pin causes the modem to go off-hook and make the associated phone busy. ======NOTES: 1. High level = +3 to +15 volts. Low level = -3 to -15 volts. 2. RS-232C is intended to connect a terminal to a modem. When computers are connected to computers without modems, one of the computers must be configured as a modem and the other as a terminal. ======

There are several levels of conformance that are appropriate for typical RS-232C interconnections. The bare minimum requirement is the two data lines and a ground. The full version of RS-232C requires 12 lines and accommpdates automatic dialing, automatic answering, and synchronous transmission. A middle-of-the-road approach is illustrated in Figure 1. One set of handshaking signals frequently implemented are RTS and CTS. CTS is used in many systems to inhibit transmission until the signal is high. In the modem application, RTS is turned around and returned as CTS after 150 microseconds. RTS is programmable in some systems to work with the older type 202 modem (half duplex). CTS is used in some systems to provide flow control to avoid buffer overflow. This is not possible if modems are used. It is usually necessary to make CTS high by connecting it to RTS or to some source of +12 volts such as the resistors shown in Figure 1. It is also frequently jumpered to an MC1488 gate that has its inputs grounded (the gate is provided for this purpose). Another signal used in many systems is DCD. The original purpose of this signal was to tell the system that the carrier tone from the distant modem was being received. This signal is frequently used by the software to display a message like CARRIER NOT PRESENT to help the user to diagnose failure to communicate. Obviously, if the system is designed properly to use this signal, and it is not connected to a modem, the signal must be provided by a pullup resistor or gate as described before (see Figure 1). Many modems expect a DTR high signal and issue a DSR. These signals are used by software to help prompt the operator as to possible causes of trouble. The OTR signal is used sometimes to disconnect the phone circuit in preparation for another automatic call. It is necessary to provide these signals to talk to all possible modems (see Figure 1). As shown, Figure 1 is a good minimum configuration that almost always works. If the CTS and OCD signals are not received from the modem, the jumpers can be moved to provide the needed signal artificially. Figure 2 shows a way that an RS-232C connector can be wired to enable a computer to connect to a basic terminal with only three wires. This is because most terminals have a DTR signal that

97 MICROSYSTEMS APPENDIX A ®MOTOROLA

is ON, and that can be used to pullup the CTS, DCD, and DSR signals. Two of I these connectors wired back-to-back can be used. It must be realized that all the handshaking has been bypassed and possible diagnostic messages do not occur. Also the Tx and Rx lines may have to be crossed since Tx from a terminal is outgoing but the Tx line on a modem is an incoming signal.

RXDr------~------~---__a I I RTS ------, I : .,2V--'Y39"'kl,-I-.....J CTS 1------, I I LS08 I I L-(""--, I ,'2V __-_+_---., RS·232C CONNECTOR DCO~----;' : I ~---, I TO t----L_j I I TERMINAL TXC~---, 47011 47011 47011 (DTE) I CPTIONAL I I RXCf----..... I HARDWARE I I I TRANSPARENT I I CTS I MODE I I I I DSR 6 I LS08 I II '------I--~ L ___ -(""--, I DCD I I----t----...J r----t..--/ I SIG G'.o I I I I I I I I L CHASSIS GND LOGIC GND--+~"'I·-+------r...=.::=:....=:.:=--Tb-, I I I I . SIG G'.o I "2V <7 I I I ~l..-4_70_1l____ ~D=-~ __ ~~~:~~.:~ ~O I I 6850 L ______RS·232C TXDI------l------~ CONNECTO I TO RXDI-----~ MODEM OR RTS r------, 39kll EXORciser . 12V-'V\N---.J OR CTS 1------., EXORmacs (DCE) DCDI-----. +12V ~.. ... ,..---, I - I

I ::~b '----~~l=:!J~--~~--L--.....c<58J-12V~ _~4Z70~1l----+;-_, ~ +12V 39kll ~DULE ______~V ______~

FIGURE 1. Middle-of-the-Road RS-232C Configuration

Another subject that needs to be considered is the use of ground pins. There are two pins labeled GND. Pin 7 is the SIGNAL GROUND and must be connected to the distant device to complete the circuit. Pin 1 is the CHASSIS GROUND, but it must be used with care. The chassis is connected to the power ground through the green wire in the power cord and must be connected to the chassis to be in compliance with the electrical code. The problem is that when units are connected to different electrical outlets, there may be several volts

98 MICROSYSTEMS @MOTOROLA APPENDIX A

difference in ground potential. If pin 1 of the devices are interconnected with a cable, several amperes of current could result. This not only may be I dangerous for the small wires in a typical cable, but could result in electrical noise that could cause errors. That is the reason that Figure 1 shows no connection for pin 1. Normally, pin 7 should only be connected to the CHASSIS GROUND at one point, and if several terminals are used with one computer, the logical place for that point is at the computer. The terminals should not have a connection between the logic ground return and the chassis.

RS-232C CONNECTOR GriD 1 0

TXD 2 0 ... RXD 3 0 ... RTS 40

CTS 5

DSR 6

GNO 7

OeD 8

JTR20 0---.1

FIGURE 2. Minimum RS-232C Connection

99 MICROSYSTEMS APPENDIX A ®MOTOROLA I

THIS PAGE INTENTIONALLY LEFT BLANK.

100 MICROSYSTEMS APPENDIX B ® MOTOROLA

APPENDIX B PROGRAMMABLE ARRAY LOGIC

Programmable Array Logic (PAL) source code for the various devices on the I MVME120 is listed in the following pages. In the upper left corner of each page is the PAL number (PAL16L8B), the device reference designation (U108 E), and the schematic sheet number (SHEET 6). The pages are arranged in sheet number order.

PAL16L8A 5-31-84 U40-SHEET 6 MVME12C,MVI~E121 CKSM= 456e PALCAC20 REV A

A10 /CACHERR PRDG BEOT40 AS2 lAS BAN~SEL IMATCH CACHE GND FREEZE ITAG3wT IwRITE SwX ITAG2WT ITAG1wT ICACHHIT IDATAWT ITAGOWT- VCC IF (YCC) CACHHIT = AS*PROG*MATCH*/CACHERR*CACHE IF (Yec) DATAWT = AS*/SEDT40*PROG*/FREEZE*/MATCH *AS2*CACHE + AS*/3EDT40*PRDG*/FREEZE*CACHERR*AS2*CACHE + AS*/BEDT40*MATCH*AS2*CACHE*WRITE + ISEOT40*DATAWT + ISWX*AS*DATAwT

IF (VCC) TAGOWT = DATA~T*AS*/A10*/8ANKSEL*/SWX + DATA~T*AS*/A10*/BANKSEL*/BEDT40

IF (vCC) TAG1wT = DATAWT*AS*A10*/BANKSEL*/SWX + DATAWT*AS*A1Q*/BANKSEL*/3EDT40 IF (VCC) TAG2WT = DATAWT*AS*/A10*6ANKSEL*/Swx + DATAWT*AS*/A10*BANKSEL*/BEDT4Q

IF (VCC) TAG3wT = DATAWT*AS*A10*BANKSEL*/S~X + OATAWT*AS*A10*8ANKSEL*/S=DT40

DESCRIPTION: CACHE CONT~~LLER PAL

101 MICROSYSTEMS APPENDIX B ®MOTOROLA

PAL16L8B 5-31-84 U40-SHEET 6 MVME123 CKSM= 4566 PALCAC23 REV A A10 ICACHERR PROG 8EDT40 AS2 lAS 8ANKSEL IMATCH CACHE GND II FREEZE ITAG3WT I~RITE SWX ITAG2WT ITAG1WT ICACHHIT IOATAWT ITAGOWT VCC IF (vec) CACHHIT = AS*PRDG*MATCH*ICACHERR*CACHE IF (VCC) DATAWT = AS*/BEDT40*PROG*/FREEZE*/MAT(H *AS2*CA(HE ~ AS*/8EDT40*PRDG*/FREEZE*CACHERP.*AS2*CACHE + AS*/BEDT4J*MATCH*AS2*CAC~E*WRITE + IBEDT40*OATAWT + ISWX*AS*OATAwT IF (vee) TAGOwT = DATAwT*AS*/A10*/BANKSEL*/SwX + DATAWT*AS*/A10*/BANKSEL*/5EDT40

IF (vec) TAG1WT = DATAwT*AS*A10*/SANKSEL*/S~X + DATAWT*AS*A10*/SANKSEL*/3EDT40

IF (VCC) TAGZWT = CATAwT*AS*/A10*BANKSEL*/SwX + DATAwT*AS*/A10*BANKSEL r /BEDT40

IF (VCC) TAG3WT = DATAwT*AS*A10*8ANKSEL*/S~X + DATAWT*AS*A1J*5ANKSEL*/BEDT40

DESCRIPTION: CACHE CDNTROLLER PAL

PAL16L8A 11-0-84 U1 DB-SHEET 6 CK$M= 3823 PALMAr R::V B

MATCH4L MATCH2U MATCHZL IBR MATCH3U MATCH3L COLUMN A1C SANKSEL GND DPGNT BRAV ISETUP VMEAV70 MATCH1U MATCH1L MATCH4U /OPCASDIS /TGGMATCH VCC

IF (VeC) TAGMATCH = IA10*IBANKSEL*MATCH1U*MATCH1L + A10*/BAN~SEL*MATCH2U*MATCH2L + IA10* BANKSEL*MATCH3U*MATCH3L • A10* BANKSEL*MATCH4U*MATCH4L IF (VeC) SE TUP = DPGNT*/COLUMN + SETUP*OPGNT IF (VeC) DPCASDIS = ISETUP*DPCASDIS + ICDLUMN*OPCASDIS + /OPGNT

IF (vee) ISRAV = IBR + IVM'=AV70

DESCRIPTION: CACHE MATCH QUALIFIER(BOARO ~AS CACHE)

102 MICROSYSTEMS ® MOTOROLA APPENDIX B

PAL16LdA 11-16-34 U108-SHEET b MVME122 CKSM= 2907 PALMAT22 REV A

MATCH4L MATCrlZU MATCH2L IBR MATCH3U MATCrl3L COLUMN A10 BANKS~L GND DPGNT BRAV ISETUP VMEAV70 MATCH1U MATCH1L MATCH4~ IDPCASCIS ITAGMATCH VCC II IF (VCC) TAGMATCH = IVCC

IF (VCC) SETUP = DPGNT*/COLUMN + SETUP*JPGNT IF (Vce) DPCASDIS = IScTJP*DPCASDIS + /COLU~N*OPCASJIS + IOPGtH

IF (VCC) IBRAV = /BR + IV~EAV70

DESCRIPTION: OUAL PORT CAS SETUP ANO NO CACHE I~DICATCR(CACHE NOT PPESENT)

PAL16L8A 11-6-/:i4 u108-SHEET 6 MVME1Z3 CKSM= 3823 PALMATZ3 ReV A MATCH4L MATCH2U MATCrl2L tBR MATCH3U MATCH3L COLUMN A10 BANKSEL GND DpGNT BRAV ISETuP VMEAV70 MATCH1U MATCrl1L MATCH4U /OPCASDIS tTAGMATCH VCC IF (VCC) TAGMATCH = IA10*/BANKSEL*MATCH1U*M4TCH1L • A10*/BANKSEL*MATCH2U*MATCrl2L + IA10* aAN~SEL*MATCH3U*MATC~3L + A10* BANKS~L*MATCrl4U*MATCH4l

IF (VCC) SETUP = DPGNT*/CClUMN + SETUP*DPG"'T

IF (VCC) OPCASDIS = IScTUP*DPCASDIS • /COlUMN*DpCASDIS + /DPGNT

IF (VCC) IBRAV = ISR + IVMEAV70

DESCRIPTION: CACHE MATCH QUAL!FIER(80ARO HAS CACHE)

103 MICROS YSTEMS APPENDIX B ® MOTOROLA·

82S153 3-06-84 U21-SHEET 7 MVME120,MVM~121 CKS~= CA17 PAL15320 REV A

ILOS IMMUORMFP IRE SET FCO IUDS READ ICACHCLR ICGNTSEL IDTACK GND 1 L 2L 3L 4 5L 6 7L 8L 9L 10 PROG IROMEN ROMTIME UIACK CDTACK IREADCR ILOADCR ~C1 Fe2 vce I 11 12L 13 14 15 16L 17L 18 19 20 IF ('ICC> LOADCR = IRQMTIME*CONTSEL*/READ*UO~ 17L 13 SL 0 5L OR 1834-1 0+23 0+15 0+11 0+9 ·0+38 [-J (23J (15J [11J [9] [33] RESET 3L OR 40+5 46+38 (51J [84J

IF ('ICC> READeR = READ*C~~TSEL*UDS 16L e H 5L 1835 -1 92+10 92+15 92+9 (-] [1u2J [107J (101J

IF (VCe> CDTACK = ROMEN*RO,'lTIMI: . 15 12L 13 OR 1836 -0 138+21 138+22 135+40 [18.s6] (159J [16uJ [178J + MMUCRMF? 2L QR 184+3 1e4+4C [187J (224J + CCNTSEL*ROMTIM: 8L 13 OR 270+15 270+22 270+40 [2~1J (2~SJ (316J

+ CACHCLR 7L OR 322+13 322+40 (335J (362J + DTACK 9L OR 368+17 368+40 [385J (408J

IF (VCC) PROG = IFCD *FC1 *UDS "'LDS *READ 11 4 18 5L 1L e OR 1840-0 414+7 414+32 414+9 414+1 414+10 414+.:.4 [1840J [421J (446J (423J [415J [424J (458J

IF ( 'ICC) UIACK = FCC* Fe1* FC 2 14 4 18 19 OR 1837-0 460+6 460+32 460+34 460+41 C18 37 J C466J (4Y2J [494J [501J INPUTS ONLY = 9 12 13 18 19 1472-("+35) 1544-("+35) 1580-("+35) 1760-("+35) 1796-("+35> (1472-1507J [1S44-157~J [1580-1615J (1760-1795J (17~6-1831J NOTE: NUMBERS IN BRACKETS INDICATE FUSES TO 3E LEFT INTACT.

104 M/CROSYSTEMS ®MOTOROLA APPENDIX B

82S153A 3-06-84 U21-SHEET 7 MVME122,MVME123 CKSM= CA17 PAL15322 Rc:V A

ILOS IMMUDRMFP IRESET FCO IUDS ~E~D ICACHCLR ICONTSEL IOTACK GNO 1L 2L 3L 4 5L 0 7L 8L 9L 10 PROG IROMEN RJMTI~e UIACK CDTACK /READCR IL~ACCR Fe1 Fe2 vce 11 12L 13 14 15 16L 17L 1~ 1~ 2D I If (VCG) LOADCR = IROMTIME*CDNTSEL*IREAO*UDS 17L 13 ElL 0 5L OR 1834-1 C+23 0 ... 15 01'11 (..1+9 0+38 [-J [23: [1 5 J [11 J [9J [38J + RESi:T 3L 0;:; 40+5 ':'0+33 [51 ] [84J

IF (vCe> READCR = REAC~CJNTSEL*UDS 16L o 8L SL JR 1835-1 92+10 92+15 9Z+9 "'2+3 9 ( -J [102J :1J7] [101J [1 31 ]

IF (vec) CO TACK = RCMEN*ROMTIME 15 12L 13 OR 1830 -0 13~+21 1j8T22 13~+40 l1 8 36 J [159J [160J [17·3)

+ MMUORMF~ 2L :JR 184+3 1 ~ .. +40 [1t17J (224) + CONTSEL*RJMTIME 8L 13 OR 270+15 276+22 270+40 [291J [2~~J C31e]

+ CACHCLR 7L 'JR 322+13 322+40 [335J (302J + DTACK -IL CR 3bb+17 368+40 [385J [405J IF (VCe) PR OG = IFCD *FC1 *U:JS *LDS *READ 1 1 4 H SL 1L Co OR 11:$40-0 4141'7 414+32 4141'9 414"'1 414+10 414+44 [1840 J [421] (440) [423J [415] [424] [458]

IF (VCG) UIACK = FCO* FC1* Fe 2 14 4 18 19 CR 1837- Q 460+6 400+32 400+34 460+41 [1837J [466J [492J [494J [501] INPUTS ONLY = 9 12 13 18 19 1472-("+35) 1544-("+35) 1580-("+35) 1760-("+35) 1796-("+35) [1472-1507] [1544-1579J [1580-1615J [1760-1795) [1796-1831)

NOTE: NUM&ERS IN BRACKETS INDICATE FUSES TO 3E LEFT INTACT.

105 MICROSYSTEMS ® MOTOROLA APPENDIX B

PAL20L8A 7-19-84 U34-SI1EET 7 MVME120,MVME122 CKSM= 5657 PALMAP20 REV A READ IMAS TA17 TA18 TA19 TA20 TA21 TA22 TA23 IVMEVF SX GND IVMEVECT VECT IROMEN INOVMEBUS OS IIAORHIT IMFPSEL IMMUSEL I ICONTSEL ICACHCLR ./NOGO yCC

IF (YCC) 'NOV~EBUS =/TA23*/TA22*/T.121*/TA20*/TA19*/TA18*/TA17 */VMEVECT*/VMEVF + TA23*TA22*TA21*TA20*/TA19*/VMEvF + IADRHIT*/VMEVF + TA23*TA22*TA21*TA20*TA1~*/TA18*/T~17*/VMEVF + NOGO + ISX + IOS*NOVMEBUS IF (VCC) MF PS EL = MAS*TA23*TA22*TA21*TA20*/TA19*/TA18*TA17 */IAORHIT*SX*/NOGO*DS

IF (VCC) CONTSEL = MAS*TA23*TA22*TA21*TA20*/TA19*TA1~*/TA17 */IAORHIT*SX*/NOGO*DS IF ( VCe> MMuSE:L = MAS*TA23*TA22*TA21*TA?O*/TA19*TA18*TA17 */IADRHIT*SX*/NGGO*DS IF (VCG) ROME N = MAS*TA23*TA22*TA21*TA20*/TA19*/TA18*/TA17 */IADKHIT*SX*/NOGO + MAS*/IAORHIT*SX*VECT*/VMEVECT IF (VCC) CACHCLR = MAS*TA23*TA22*TA21*TA20*TA19*/TA18*/TA17 */IAORHIT*SX*/NOGO*DS

DESCRIPTION: BOARD MAP DECODER(128K3YTE ONSOARD DYNA~IC RAM)

106 MICROSYSTEMS ® MOTOROI.A APPENDIX B

PAL20LBA 7-23-84 U34-SHEET 7 MVME121,MVME123 CKSM= 5679 PALMAP?1 REV A

READ IMAS TA17 TA18 TA1~ TA20 TA21 TA22 TA23 IVMEVF SX GNO IVMEVECT vEeT IROMEN INOVMEdUS OS IIAORHIT IMFPSEL IMMUSEL ICONTSEL leACHCLR INOGO VCC

IF (vec) NOVM~8uS = ITA23*/TA22*/TA21*/TA20*/TA19 */VMEVtCT*/VMEVF + TA23*TA22*TA21*TA20*/TA19*/VMEVf + IAORHIT*/V~,EVF + TA23*TA22*TA21*TA20*TA19*/TA18*/TA17*/VMEVF + NCC,O + ISX .. + IDS*NCVMEBUS IF (VCC) MfPSEL = MAS*TA23*TA22*TA21*TAZO*/TA19*/TA18*TA17 */IAORrlIT*SX*/NOGO*OS IF (VCO CONTSEL = MAS*TA23*TA22*TA21*TA20*/TA19*TA18*/TA17 */IAORHIT*Sx*/NOGC*DS IF (VCO MMUS EL = MAS*TA23*TA22*TA21*TA20*/TA19*TA18*TA17 */IAORHIT*SX*/NOGO*DS IF (VCO ROMEN = MAS*TA23*TA22*TA21*TA20*/TA19*/TA18*/TA17 */IAOR~IT*SX*/NOGO + MASw/IAGRHIT*SX*VECT*/VMEVECT

IF (Vce) CACHCLR = MAS*TA23*TA22*TA21*TA20*iA19*/TA18*/TA17 */IAORMIT*SX*/NOGO*OS

DESCRIPTIDN: BOARJ ~AP DECODER(S12KBYTc ON3DARD DYNAMIC RAM)

107 MICROSYSTEMS APPENDIX B ® MOTOROLA

PAL16L8A 3-C6-84 U16-SHE:ET 8 MVME12Q,MVME121,MVME122,MVME123 CKSM= 5780 PALMIS20 REV A RESET AS VDS 16USBERR IBUSDTCK DPGNT ICACHCLR A02 A01 GND I VAS ICLR1 INOvECT 114 115 ISLAVECYC 17 IDpeyDN ICLRO vec IF (VCC) 14 = IVAS*SLAVECYC + 14*SLAVECYC IF (VCC) SLAVECYC = VOS*DPGNT + VDS*SLAVECYC + SLAVECYC*/14 IF (VCC) OPCYON = RESET + ::lUSUTCK + BUSE:lERR IF (VCC) CLRO = CACHCLR*A01 + RESET IF (VCC) CLR1 = CACHCLR*A02 + RESET IF (VCC) 15 = A01*A02*AS + IRESET*15

IF (Vce) NOVECT = 15*/~S*/RESET + IRESET*NGvECT

DESCRIPTION: MISCELLANEO~S FUNCTIONS

108 M/CROSYSTEMS APPENDIX B ®MOTOROLA

PAL16L2 2-17-84 U28-SHEET 8 MVME120,MVME122 CKSM= 0744 PALDP20 REV A

A23 A22 A21 A20 A19 A18 A17 ILwORD IIACK GND AM1 AM3 AM2 AM4 15 IDPMATCH AMO AM5 VMEAV VCC DPMATCH = IA23*iA2t*/A21*/A20*/A1i*/A18*/A17 ;SUPER PRGG */IACK*/LWCRJ*/VMEAV *AM5*A~4*AM3*AM2*AM1*/AM0

+ IA23*/A22*/A21*/A2Q*/A1Y*/A1S*/~17 ;SUPER DATA */IACK*/LWORD*/VMEAY *AMS*AM4*AM3*AM2*/AM1*AMO

+ IA23*/A22*/A21*/A20*/A1i*/A18*/A17 ;USER PROG */IACK*/LWGRD*/YMEAV *AMS*AM4*AM3*/AM2*AM1*/AMO • IA23*/A22*iA21*/A20*/A1i*/A18*/A17 ;USER LJATA */IACK*/LWORD*/VMEAV *AMS*AM4*AM3*/AM2*/AM1*AMO DESCRIPTIDN: DUAL PORT MAP DECODER(128KBYTE ONSDARD RAM) SET FOR VMESUS ADDRESSES Q-1FFFF

7-23-84 PAL16L2 Ct<. SM= 07CC U28-$HEET 8 MVME121,VME123 PALDP21 REY A A23 A22 A21 A20 A19 A18 A17 /LWORD IIACK GND AM1 AM3 AM2 AM4 15 IDPMATCH AMO AM5 VMEAV yce DPMATCH = IA23*/A22*/A21*/A20*/A19 ;SUPER PROG */IACK*/LWORD*/VMEAV *AM5*AM4*AM3*AM2*AM1*/AMO + IA23*/A22*/A21*/A20*/A19 iSUP!:R DATA */IACK*/LWORD*/YMEAV *AM5*AM4*AM3*AM2*/AM1*AMO

+ IA23*/A22*/A21*/A2C*/A19 ;\.JSER PROG */IACK*/LWDRD*/VMEAV *AM5*AM4*AM3*/AM2*AM1*/AMO

+ IA23*/A22*/A21*/A20*/A19 ;USER DATA */IACK*/LwORD*/YM~AV *AM5*AM4*AM3*/AM2*/AM1*AMO DESCRIPTION: DUAL PORT MAP DECODER(512KBYTE ON80ARD DYNAMIC RAM) StT FOR VME8US ADDRESSES 0-7fFFF

109 MICROSYSTEMS APPENDIX B ® MOTOROLA

PAL16L8A 5-31-84 U31-SHEET 9 MVME120,MVME122 CKSM= 4242 PALCAS20 REV A

ILOS IUDS TA1? TA18 TA19 TA20 TA21 TA22 TA23 GND I IRAMWRT IRAMGD 10K lUCAS ICASTIME ILCAS IVLCASEN VUCASEN 19 vce IF (Vce) LCAS = ITA23*/TA22*/JA21*/T420*/TA19*/TA18*/TA17 *OK*LDS*CASTH1E + ITA23*/TA22*/TA21*/TA20*/TA19*/TA18*/TA17 *OK*UOS*CASTIME*/RAMWRT + LCAS*CASTH1E + VLCASEN*CASTIME + nCASEN*LCAS + VUCASEN*CASTIME*/RAM~RT + VUCASEN*LCAS*/RAMwRT

IF (VCC) UCAS = ITA23*/TA22*/TA21*/TA20*/TA1~*/TA13*/TA1? *CK*UDS*CASTIME + ITA23*/TA22*/TA21*/TA20*/TA19*iTA18*/TA1? *OK*LDS*CASTIME*/RAMWRT + UCAS*CASTH1E + VUCASEN*CASTIME + VUCASEN*UC.AS ~ VLCASEN*CASTIME*/RAMWRT + VLCASEN*UCAS*/RAMWRT

IF (VCC) RAMGO = ITAZ3*/TA22*/TAZ1*/TA20*/TA19*/TA1~*/TA17 *UOS*OK*CASTH~E + ITA23*/T~22*/TAZ1*/TA20*/TA19*/TA18*/TA17 *lOS*OK*c:.STIME

DESCRIPTION: RAM CAS'S(128KBYTE ONB8ARJ DY~AMIC RAM) USE THIS PAL WHEN AN MMU IS P~~SENT OR WHEN J13 1-2 ARE CUNNECTED

110 MICROSYSTEMS ®MOTOROI..A APPENDIX B

PAL16L8A 7-23-84 U31- SHEET 'i MVME121,MVME123 CKSM= 430E pALCAS21 REV A ILOS IUDS TA17 TA18 TA19 TA20 TA21 TA22 TA23 GNC IRAMWRT IRAMGO leK lUCAS ICASTIME ILCAS IVLCASEN VUCASEN 1Y VCC IF (VCC) LCAS = ITA23*/TA22*/TA21*/TA20*/TA19 *OK*LCS*CASTIM: ~ ITA23*/TA22*/TA21*/TA20*/TA19 *OK*UCS*CASTIME*JRAMwRT + LCAS*CASTIME ~ VLCASEN*CASTIMc ~ VLCASEN*LCAS + VUCASEN*C~STIME*/RAMwRT + VUCASEN*LCAS*/RAMWRT IF (VCC) UCAS = ITA23*/TA22*/TA21*/TA20*/TA19 * CK * UC S * CAS T H~ i:: + ITA23*/TA22*/TA21*/TA20*/TA19 *O~*LCS*CASTI~E*/RAMwRT + LCAS*CASTIME + VUCASEN*CASTIME + VUCASEN*UCAS + VLCASEN*CASTIME*/RAMwRT + VLCASEN*UCAS*/RAMWRT

IF (VCC) RAMGC = ITA23*/T~22*/TA21*/TA20*/TA19 *UDS*OK*U STUe: ~ ITA23*/TA22*/TA21*/TA20*/TA1'i *LOS*CK*C~STI~E

DESCRIPTION: RA~ CAS'S(S12K8VTE ONBOARD rVNAMIC RAM)

III MICROSYSTEMS APPENDIX B @MOTOROLA

PAl16R8 7-20-84 US6-SHEET 10 MVME120,MVME121,MVME122,MVME123 CKSM= 7C40 PAlCNT20 REV A

elK 2 3 4 S 6 7 8 9 GNO I IDE IA? IA6 lAS IA4 IA3 IA2 I A1 lAO vec AO : = lAO

Ai : = AO*/A1 + IAO*A1

A2 := AO*A1*/A2 + IAO*A2 + IA1*A2

A3 : = AO*A1*A2*/A3 + I;.\O*A3 + IA1*A3 + IA2*A3

A4 := AO*A1*A2*A3*/A4 + IAO*A4 + IA1*A4 + IA2*A4 + IA3*A4

AS := AO*A1*A2*A3*A4*/A5 + IAO*AS + /A1*A5 + IA2*AS + IA3*AS + IA4*A5

A6 := AO*A1*A2*A3*A4*AS*/A6 + IAO*A6 + IA1*A6 + IA2*A6 + IAS*A6 + IA4*A6 + IA5*A6

A7 := AO*A1*A2*A3*A4*A5*A6*/A7 + IAO*A7 + IA1*A7 + IA2*A7 +" IA3*A7 + IA4*A7 + /AS*A7 + IA6*A7

DESCRIPTION: RA~ REFRESrl COUNTER

112 MICROSYSTEMS APPENDIX B ® MOTOROL.A

PAL16L8A 3-06-84 U7-SHEET 12 MVME120,MVME121,MVME122,MVME123 CKSM= 6680 PALVMEZO REV A

VWRITE VDTACK V~ERR IVMEAV ISLAVECYC IEN40 IUDS IOVAS READ GND ILOS INOBBERR Is244EN I~N /SUDS IRAMWRT ISLDS vOs INOSJTACK vce I IF (vee) EN = IVBERR*/VDTACK*VMEAV*UDS*/REAQ + IVBERR*/VDTACK*VMEAV*LDS*/READ T SLAVEC~C*/VWRITE*VDS + EN*UOS + EN*LDS IF (VCC) S244EN = UDS*RcAO*OVAS + VWRITE*SLAVECYC*VDS*/VOTACK + LCS*REtlD*OVAS + S244E~*BUDS + SZ44EN*BLDS

IF (vec) BUOS = OV~S*UDS*/vaERR*lvDTACK*VMEAV*READ + OVAS*UDS*/VBERR*/VDTACK*VMEAV*/READ*EN40 + BUDS*UDS

IF (vee) oLDS = OVAS*LDS*/V5ERR*/VOTACK*V~EAV*READ + OVAS*LDS*/VBERR*/VDTACK*VMEAV*/READ*E~4J + BLOS*LOS IF (vec) NoeBERR = IV6ERR + 18UOS*/3LDS

IF (vce) N06DTACK = IVDTAC~ T IBuDS"-lOlDS

IF (veo RAMWRT = IREAC + vwRITE*SLAVtCYC

OEStRI?TION: VMEBUS STRC9ES ETC.

113 MICROSYSTEMS APPENDIX B ®MOTOROLA

PAL20L8A 4-15-85 U39-SHEET 15 MVME120, MVME121,MVME122,MVME123 CKSM=98D5 PALINT20-51AW4697B27 REV B

IIACK A02 A01 IIRQ1 IIRQ2 IIRQ3 IIRQ4 IIRQ5 IIRQ6 IIRQ7 IIEO GND IABORT I IMFPIRG IIPLO IVPA IVMEVF A03 ALTINT IMFPIACK IIPL2 IIPL1 lIE VCC IF (VCC) IPLO = IE*IRG1*/IRQ2*/IRG4*/IRG6*/MFPIRG + IE*IRG3*/IRG4*/IRG6*/MFPIRQ + IE*IRG5*/IRQ6*/MFPIRG + IE*IRQ7 + IE*ABORT IF (VCC) IPLl = IE*IRQ2*/IRQ4*/IRG5 + IE*IRQ3*/IRG4*/IRQ5 + IE*IRG6 + IE*MFPIRQ + IE*IRG7 + IE*ABORT

IF (vec) IPL2 ~ IE*IRG4 + IE*IRG5 + IE*IRG6 + IE*MFPIRG + IE*IRG7 + IE*ABORT IF (VCC) MFPIACK = A03*A02*/A01*IACK*/ALTINT + MFPIACK*IACK

IF (VCC) VPA = IA01*/A02*/A03*IACK + A01*A02*A03*IACK*ABORT + ALTINT*IACK*/VMEVF

IF (VCC) VMEVF = A03*A02*A01*/ABORT*IACK*/ALTINT + A03*A02*/A01*IACK*IEO*/ALTINT + A03*/A02*IACK*/ALTINT + IA03*A02*IACK*/ALTINT + IA03*/A02*A01*IACK*/ALTINT + VMEVF*IACK

DESCRIPTION: INTERRUPT HANDLER

114 MICROSYSTEMS INDEX @MOTOROLA

INDEX

ABORT 41 ABORT switch 5,9,23,29,39 access time 7,17,29,30,37 ACFAIL 5,7,39,40,41,44,53 addresses) 17-33,35-42,45,52,54,55 address bus 52,53,55 array 30, 37, 101 backplane 21, 22 baud 29,45,46 baud rate 45 bidirectional 51,54 block diagram 29,30,31,49 boundary 19 buffer 41,43,97 bus 19,29,30,36,38,39,44,46,47,53,54 bus cycle 44 bus master 24,52,53,55 bus requester 30, 39 bytes 28,29,30,37,42,46 cache 4,7,14-16,27-37,43,44 cache flushing 36 cache hit cycle 33,34,36,43 cache ignore cycle 33, 35 cache invalidate cycle 33-36 cache memory 29,31 cache validate cycle 33,34,36 CACHEHIT 16,40,43 card 21,22 chain 39 chip enable 17 clock 3,30,45,46,96 control register 26,37,44,45,56 controller .23,30,38 CPU 4,29 computer 4,29 cycle 29,30,33-36,38,43,52,54 data bus 35,51,52,54 data path 51,54 data terminal 56,96 debug 3,4,29 decoder 20,29,30 diagnostic 98 disk controller 30 DMA 28,30,37 direct memory access 28,30,37 double bus fault 24 DTACK 34,38,42,52 data transfer acknowledge 34,38,42,52 DTR 41,43,56,96,97

115 MICROSYSTEMS INDEX @MOTOROLA

data terminal ready 41,43,56,96,97 dynamic memory 29 dynamic RAM 4,37,38 EPROM 11-13 FAIL indicator 23,24,45 fault 47 fetch 7,17,18,23,43 flip-flop 30 gate 97 general description 4,29 HALT indicator 23,24 handshaking 94,97,98 header 7,9-13,15-17,19,22,23,57,58 I/O and control 30 input signal 53,54 instructions 5, 23, 28, 29, 37 internal interrupts 40 interrupt handler 3,30,39 IRQ 10,22,41,43 interrupt request 10,22,41,43 logic circuits 53,55 main memory 32, 37 map 20 master 19,38,41,51,52,54 memory access cycle 33,35,36 memory map 25,28,29,36,46,52 MMU 4,26-31,37,38,41,47,59 memory mangement unit 4,26-31,37,38,41,47,59 MMUIRQ 41,43 mode switch 23,42,46 monitor 7,16 MPU 2-6,8-10, 17, 19,21-25,28-31,33-47,49,51,53-55,57-64,94 multi-port controller 30, 38 network 30,58 noise 99 OR 17, 19,27,28 overflow 97 PAL 19,21, 30, 38, 101 programmable array logic 19,21,30,38,101 PARERR 43,44 parity error 43,44 parity check 37 PC 23,29,37 program counter 23,29,37,42,46 port 3,4,19,20,22,24,29,30,39,42,44,45,47,55,56 RAM 3,4,19,20,21,22,25,28,30,33,37,38,43,44,47,55 read cycle 36,43,52 request to send 95 reset 7,9,17,18,23-25,28-30,36,42,43,45,46,54 RESET switch 5,9,23,29 ROM 4,7,17,25,30,43,46 RS-232C 3,21,22,29,43,56,94,96-99

116 MICROSYSTEMS INDEX @MOTOROLA

RUN indicator 23, 24 SCR 26 segment 30 service routine 46,52 slave 38-42, 51, 52, 54 software considerations 37 source code 19,21,101 stack pointer 23,29,42,46 status bit 46,47 status register 7 strobe 24,38,51,52 supervisor 14, 15 SYSFAIL 5,7,24,39-41,44,45,54 system failure 5,7,24,39-41,44,45,54 SYSRESET 23,54 system reset 23,54 system controller 4,19,22,23,29,39,54 terminal 3,4,22,29,43,45,56,94-98 terminal port connector 29,56 track 13 transition 96 vector(s) 7, 17, 18,23,39-43 VMEBERR 43,44 VMEbus error 43,44 VMEbus interface 30,41 wait state 31 WRITE 27,28,51 write cycle 27,28,36,52

117 MICROSYSTEMS ® MOTOROLA INDEX

118 MICROSYSTEMS FUNCTIONAL DESCRIPTION ® MOTOROI.A

e. Read to user program data space causes one of two cycle types to occur: 1. Cache hit cycle if in the indexed cache entry; VI=l, V2=I, F=O, and the cache tag address matches the current logical address from the MPU. 2. Cache validate cycle if in the indexed cache entry; Vl=O, V2=O, F=l, or the cache tag address does not match the current logical address from the MPU. f. Read to supervisory program space causes one of two cycle types to occur: 1. Cache hit cycle if in the indexed cache entry; VI=I, V2=I, F=I, and the cache tag address matches the current logical address I from the MPU. 2. Cache validate cycle if in the indexed cache entry; VI=O, V2=O, F=O, or the cache tag address does not match the current logical address from the MPU. g. Write to user program space should never be used by the software if cache is enabled. h. Write to supervisory program space should never be used by the software if cache is enabled. i. Any memory access cycle that would normally be a cache validate cycle, becomes a cache invalidate cycle if an address error or a bus error occurs. j. The cache can be enabled/disabled by software using the CACHEN bit in the MCR. When the cache is disabled, all cycles are cache ignore cycles. k. The cache can be frozen/unfrozen by software using the FREEZE bit in the MCR. The only effect of freezing the cache is that all cache validate cycles become cache ignore cycles. Cache invalidate cycles are not affected.

Cache Flushing The cache can be flushed by the software accessing a particular location in the memory map. The access can be either a read cycle or a write cycle. When using configurations a,b,c, the cache is flushed by accessing location F80006. When using configuration d, all the cache is flushed by accessing location F80006 or the user program space is flushed by accessing location F80004, or the supervisory program space is flushed by accessing location F80002. Locations F80002 or F80004 should not be accessed when using configurations a,b,c. When cache is flushed, its VI and V2 bits are cleared to 0 making all cache entries become invalid. Reset also causes cache to be cleared. The cache clear function happens whether or not the cache is enabled or frozen in the MCR.

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