Heterogeneous Three-Dimensional Electronics by Use of Printed Semiconductor Nanomaterials Jong-Hyun Ahn, et al. Science 314, 1754 (2006); DOI: 10.1126/science.1132394

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9. M. Schwarzschild, R. Härm, Astrophys. J. 150, 961 (1967). 21. F. M. Jiménez-Esteban, P. García-Lario, D. Engels, in 9499 (A.M. and P.G.L.) and a MEC JdC grant (J.M.T.R.). 10. R. H. Sanders, Astrophys. J. 150, 971 (1967). Planetary Nebulae as Astronomical Tools, R. Szczerba, This work is based on observations obtained at the 11. M. Busso, R. Gallino, G. J. Wasserburg, Annu. Rev. Astron. G. Stasinska, S. K. Gorny, Eds. (AIP Conference Proceedings, 4.2-m William Herschel Telescope, operated on the Astrophys. 37, 239 (1999). vol. 804, American Institute of Physics, Melville, NY, 2005), island of La Palma by the Isaac Newton Group in the 12. O. Straniero et al., Astrophys. J. 440, L85 (1995). pp. 141–144. Observatorio del Roque de Los Muchachos of the 13.J.W.Truran,I.IbenJr.,Astrophys. J. 216, 797 22. P. Ventura et al., Astrophys. J. 550, L65 (2001). Instituto de Astrofisica de Canarias, and on observations (1977). 23. C. M. O’D. Alexander, Philos. Trans. R. Soc. London Ser. A obtained with the 3.6-m telescope at ESO–La Silla 14. H. Beer, R. L. Macklin, Astrophys. J. 339, 962 (1989). 359, 1973 (2001). Observatory (Chile). 15. C. Abia et al., Astrophys. J. 559, 1117 (2001). 24. E. Zinner et al., Geochim. Cosmochim. Acta 69, 4149 16. D. L. Lambert et al., Astrophys. J. 450, 302 (1995). (2005). 17. J. Tomkin, D. L. Lambert, Astrophys. J. 523, 234 (1999). 25. K. D. McKeegan, A. M. Davis, in Meteorites, Planets, and Supporting Online Material www.sciencemag.org/cgi/content/full/1133706/DC1 18. A. Banerjee, D. Das, V. Natarajan, Europhys. Lett. 65, Comets, A. Davis, Ed., vol. 1 of Treatise on Geochemistry Fig. S1 172 (2004). (Elsevier-Pergamon, Oxford, 2003), pp. 431–460. 19.N.Grevesse,A.J.Sauval,Space Sci. Rev. 85, 161 26. F. A. Podosek et al., Geochim. Cosmochim. Acta 55, 10 August 2006; accepted 19 October 2006 (1998). 1083 (1991). Published online 9 November 2006; 20. P. S. Chen, R. Szczerba, S. Kwok, K. Volk, Astron. 27. Supported by the Spanish Ministerio de Educación y 10.1126/science.1133706 Astrophys. 368, 1006 (2001). Ciencia (MEC) grants AYA 2004-3136 and AYA 2003- Include this information when citing this paper.

this method avoids some of the aforementioned problems, the requirements for epitaxy place Heterogeneous Three-Dimensional severe restrictions on the quality and type of materials that can be grown, even when buffer Electronics by Use of Printed layers and other advanced techniques are used (1, 13). Semiconductor Nanomaterials By contrast, nanoscale wires, ribbons, mem- branes, or particles of inorganic materials, or Jong-Hyun Ahn,1,2,3 Hoon-Sik Kim,5 Keon Jae Lee,1,3 Seokwoo Jeon,1,2,3 Seong Jun Kang,1,2,3 carbon-based systems such as single-walled Yugang Sun,1,2,3 Ralph G. Nuzzo,1,2,3,4 John A. Rogers1,2,3,4,5* carbon nanotubes (SWNTs) or graphene sheets (14–17), can be grown and then suspended in We developed a simple approach to combine broad classes of dissimilar materials into solvents or transferred onto substrates in a on December 14, 2006 heterogeneously integrated electronic systems with two- or three-dimensional layouts. The process manner that bypasses the need for epitaxial begins with the synthesis of different semiconductor nanomaterials, such as single-walled carbon growth or wafer bonding. Recent work has nanotubes and single-crystal micro- and nanoscale wires and ribbons of gallium nitride, silicon, shown the integration of isolated crossed nano- and gallium arsenide on separate substrates. Repeated application of an additive, transfer printing wire diodes in 2D layouts formed by solution process that uses soft stamps with these substrates as donors, followed by device and interconnect casting (18). Our results show how dissimilar formation, yields high-performance heterogeneously integrated electronics that incorporate any single-crystal inorganic semiconductors (such combination of semiconductor nanomaterials on rigid or flexible device substrates. This versatile as micro- and nanoscale wires and ribbons of methodology can produce a wide range of unusual electronic systems that would be impossible to GaN, Si, and GaAs) can be combined with one achieve with other techniques. another and also with other classes of nano- www.sciencemag.org materials (such as SWNTs) with the use of a any existing and emerging electronic chip-scale bonding (1, 2, 6, 8–10) and epitaxial scalable and deterministic printing method to devices benefit from the heteroge- growth (3, 11, 12) represent the two most widely yield complex, heterogeneously integrated Mneous integration of dissimilar classes used methods for achieving these types of electronic systems in 2D or 3D layouts. The of semiconductors into single systems, in either integrated systems. capabilities of this process are demonstrated by two-dimensional (2D) or 3D layouts (1, 2). Ex- The bonding processes use fusion processes ultrathin multilayer stacks of high-performance amples include multifunctional radio-frequency (8, 9) or layers of adhesives (6, 10) to combine metal oxide semiconductor field-effect transis- communication devices, infrared imaging cam- integrated circuits, photodiodes, or sensors tors (MOSFETs), high electron mobility tran- Downloaded from eras, addressable sensor arrays, and hybrid sili- formed separately on different semiconductor sistors (HEMTs), thin-film transistors (TFTs), con complementary metal oxide semiconductor wafers. This approach works well in many photodiodes, and other components that are (CMOS) circuits and nanowire devices (3–7). cases, but it has important drawbacks (1, 9), integrated into device arrays, logic gates, and In some representative systems, compound semi- including (i) limited ability to scale to large actively addressable photodetectors on rigid conductors or other materials provide high-speed areas (i.e., larger than the wafers) or to more inorganic and flexible plastic substrates. operation, efficient photodetection, or sensing than a few layers in the third (i.e., stacking) Figure 1 illustrates representative steps for capabilities; the silicon CMOS provides digital dimension; (ii) incompatibility with unusual producing these types of systems. The process readout and signal processing in circuits that of- materials (such as nanostructured materials) begins with the synthesis of the semiconductor ten involve stacked 3D configurations. Wafer- or and/or low-temperature materials and substrates; nanomaterials, each on their own source sub- (iii) challenging fabrication and alignment for strate. The devices shown in Fig. 1 allow micro- 1Department of Materials Science and Engineering, Uni- the through-wafer electrical interconnects; (iv) and nanoscale wires and ribbons of single- versity of Illinois, Urbana-Champaign, IL 61801, USA. demanding requirements for planar bonding crystalline GaN, GaAs, and Si that were formed 2Beckman Institute for Advanced Science and Technology, University of Illinois, Urbana-Champaign, IL 61801, USA. surfaces; and (v) bowing and cracking that can with the use of wafer-based source materials 3Frederick Seitz Materials Research Laboratory, University occur from mechanical strains generated by and lithographic etching procedures (19–23)to of Illinois, Urbana-Champaign, IL 61801, USA. 4Department differential thermal expansion and contraction be integrated with each other or with networks of Chemistry, University of Illinois, Urbana-Champaign, IL of disparate materials. Epitaxial growth provides of SWNTs that were grown by chemical vapor 61801, USA. 5Department of Electrical and Computer En- gineering, University of Illinois, Urbana-Champaign, IL 61801, a different approach, which uses molecular deposition (16, 23). Scanning electron micro- USA. beam epitaxy or other means to form thin layers graphs at the top of Fig. 1 show these *To whom correspondence should be addressed. E-mail: of semiconductor materials directly on the semiconductor nanomaterials after their removal [email protected] surfaces of wafers of other materials. Although from the source substrates. For circuit fabrica-

1754 15 DECEMBER 2006 VOL 314 SCIENCE www.sciencemag.org REPORTS tion, these elements remain in the configurations Second, the method is applicable to broad optical micrograph of an edge of the system; the defined on the wafers during the fabrication or classes of semiconductor nanomaterials, includ- layout of the system was designed to reveal growth stage: aligned arrays in the case of the GaN, ing emerging materials such as SWNTs. Third, separately the parts of the substrate that sup- GaAs, and Si materials, and submonolayer random the soft stamps enable nondestructive contacts port one, two, and three layers of MOSFETs. networks for the SWNTs. High-temperature dop- with underlying device layers; these stamps, A 90° rotation of the device geometry for the ing and annealing procedures for ohmic contacts together with the ultrathin semiconductor ma- second layer, relative to the first and third, to the GaN, GaAs, and Si can be performed on terials, can also tolerate surfaces that have some helps to clarify the layout of the system. Sche- the source substrates. topography. Fourth, the ultrathin device geom- matic cross-sectional and angled views of the The next step involves transferring these etries and interlayers allow easy formation of stacked structure are shown in Fig. 2B. The processed elements, with the use of an elasto- layer-to-layer electrical interconnects by direct sample can be viewed in 3D using confocal meric stamp–based printing technique (19), metallization over the device structure. These optical microscopy. Figure 2C shows top and from the source substrates to a device substrate, features overcome many of the disadvantages angled views of such images. (The image qual- such as a sheet of polyimide (PI) (Fig. 1). In of conventional approaches. ity degrades somewhat with depth because of particular, laminating a stamp of polydimethyl- Figure 2 presents three-layer, 3D stacks of scattering and absorption from the upper layers). siloxane against the source substrate establishes arrays of Si MOSFETs fabricated by the general Figure 2D presents electrical measurements of soft, van der Waals adhesion contacts to the process flow shown in Fig. 1. We used single- representative devices in each layer. Devices on semiconductor nanomaterial elements. We con- crystalline silicon nanoribbons with doped tacted the “inked” stamp to a device substrate contacts (formed on the source wafer), SiO2 (such as a PI sheet) with a thin, spin-cast layer dielectrics formed by plasma-enhanced chemi- of a liquid prepolymer (such as polyamic acid) cal vapor deposition, and Cr/Au metallization on its surface and then cured the polymer, for the source, drain, and gate electrodes (25). which left these semiconductor materials Each device uses three aligned nanoribbons, embedded on and well adhered to this layer each with length L =250mm, width W =87mm, (19–22) when the stamp was removed. Similar and thickness = 290 nm. Figure 2A shows an procedures work well with a range of substrates (i.e., rigid or flexible and organic or inorganic) and semiconductor nanomaterials. We used a slightly modified version of this process for the on December 14, 2006 SWNT devices (23). The thickness of the inter- layer (PI in this case) can be as small as 500 nm and was typically 1 to 1.5 mm for the systems we describe. After some additional processing—including deposition and patterning of gate dielectrics, electrodes, and interconnects—the transfer printing and device fabrication steps can be re- peated, beginning with spin-coating a new pre- www.sciencemag.org polymer interlayer on top of the previously completed circuit level. Automated stages spe- cially designed for transfer printing or conven- Fig. 2. (A) Optical micrograph view of the top tional mask aligners enable overlay registration of a 3D multilayer stack of arrays of single-crystal accuracy of ~2 mm over several square centi- silicon MOSFETs that use printed silicon nano- meters (fig. S1). The spatial distortions asso- ribbons for the semiconductor. The bottom (1st), ciated with the printing had a mean value of middle (2nd), and top (3rd) parts of this image ~0.5 mm (fig. S2). The yields for printing of Si, correspond to regions with one, two, and three Downloaded from SWNT, GaAs, and GaN were >99%, >99%, layers of devices, respectively. (B) Schematic cross- >95%, and >85%, respectively. Defects in these sectional (top) and angled (bottom) views. S, D, last two cases were associated with fracture and and G refer to source, drain, and gate electrodes impartial transfer for the relatively wide GaAs (all shown in gold), respectively. The light and dark ribbons and relatively thick GaN bars, respec- blue regions correspond to doped and undoped tively (fig. S3). Layer-to-layer interconnects regions of the silicon ribbons; the purple layer is (24) were formed simply by evaporating metal the SiO2 gate dielectric. (C) 3D images (left, top lines over and into openings in the interlayers view; right, angled view) collected by confocal microscopy on a device substrate similar to that defined by photopatterning and/or dry etching. shown in (A) and (B). The layers are colorized (gold, This fabrication approach has several im- top layer; red, middle layer; blue, bottom layer; portant features. First, all of the processing on Fig. 1. Schematic illustration of a printed semi- silicon, gray) for ease of viewing. (D) Current- the device substrate occurs at low temperatures, conductor nanomaterials–based approach to voltage characteristics of Si MOSFETs in each of the thereby avoiding differential thermal expansion heterogeneous 3D electronics. The process in- layers, showing excellent performance (mobilities and shrinkage effects that can result in un- volves the repetitive transfer printing of col- of 470 ± 30 cm2/Vs) and good uniformity in the wanted deformations in multilayer stacked sys- lections of nanotubes, nanowires, nanoribbons, properties. The channel lengths and widths are 19 tems. This operation also enables the use of or other active nanomaterials, separately formed and 200 mm, respectively. The overlap lengths, as low-temperature plastic substrates and inter- on source substrates, to a common device sub- defined by distance that the gate electrode ex- layer materials, and it helps to ensure that strate to generate interconnected electronics tends over the doped source and drain regions, underlying circuit layers are not thermally de- in ultrathin, multilayer stack geometries. HGI, are 5.5 mm. IDS, drain current; VGS,biasvoltage; graded by the processing of overlying devices. heterogeneous integration. VDS, drain voltage.

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each of the three layers, which are formed on bend radii down to 3.7 mm. To explore the S12 to S15 present information on variation in a PI substrate, show excellent properties with response of devices to operation under various device properties. linear mobilities of 470 ± 30 cm2/Vs (where the conditions, such as repeated bending and elec- Electrical interconnections formed between error is SD), on/off ratios greater than 104,and trical testing, we carried out two sets of exper- different levels in these devices can create threshold voltages of –0.1 ± 0.2 V; there are no iments. Repeated bending (up to 2000 cycles) systematic differences between devices in dif- resulted in no substantial change in the prop- ferent layers. Additional layers can be added erties of the devices (fig. S8). Repeated elec- to this system by repeating the same proce- trical testing showed stable responses (~10% dures. To investigate issues related to mis- changes in properties, or less) (fig. S11). Figures matches in coefficients of thermal expansion in these systems, we evaluated the behavior of the devices under thermal cycling (60 times) between room temperature and 90°C. Small changes were observed for the first few cycles followed by stable behavior (fig. S9). In addition to 3D circuits with a single semi- conductor, Fig. 3 illustrates that the capability to combine various semiconductors can be used in multiple layers. We fabricated arrays of HEMTs, MOSFETs, and TFTs—with the use of GaN bars, Si nanoribbons, and SWNT films, respectively, on PI substrates. Figure 3, A and B, shows high-magnification optical and con- focal images, respectively, of the resulting devices. The GaN HEMTs on the first layer use ohmic contacts (Ti/Al/Mo/Au, annealed on the source wafer) for the source and drain, and Schottky (Ni/Au) contacts for the gates. Each on December 14, 2006 device uses GaN ribbons (composed of multi- layer stacks of AlGaN/GaN/AlN) intercon- nected electrically by processing on the device substrate. The SWNT TFTs on the second layer use SiO2 and epoxy for the gate dielectric and Cr/Au for the source, drain, and gate. The Si MOSFETs use the same design as those shown in Fig. 2. Various other devices can be con- structed with different combinations of Si, www.sciencemag.org SWNT, and GaN (figs. S4 and S5). Figure 3C presents the current-voltage characteristics of typical devices in the systems of Fig. 3, A and B. In all cases, the properties are similar to those fabricated on the source wafers: The GaN Fig. 4. (A) Image of a printed array of 3D silicon HEMTs have threshold voltages (Vth)of–2.4 ± Fig. 3. (A) Optical micrograph of 3D heteroge- n-channel metal oxide semiconductor inverters on 0.2 V, on/off ratios greater than 106,andtrans- neously integrated electronic devices, including a PI substrate. The inverters consist of MOSFETs conductances of 0.6 ± 0.5 mS; the SWNT TFTs GaN nanoribbon HEMTs, Si nanoribbon MOSFETs, (channel lengths of 4 mm, load-to-driver width Downloaded from m have Vth = –5.3 ± 1.5 V,on/off ratios greater than and SWNT network TFTs, in a three-layer stack. (B) ratio of 6.7, and a driver width of 200 m) on two 105, and linear mobilities of 5.9 ± 2.0 cm2/Vs; 3D image collected by confocal microscopy. The different levels, interconnected by electrical via and the Si MOSFETs have Vth = 0.2 ± 0.3 V, layers are colorized (gold: top layer, Si MOSFETs; structures. The image on the top right provides a on/off ratios greater than 104, and linear mobil- red: middle layer, SWNT TFTs; pink: bottom layer) magnified view of the region indicated by the red ities of 500 ± 30 cm2/Vs. for ease of viewing. (C) Electrical characteristics of box in the left frame. The graph on the bottom Another interesting aspect of these devices, GaN devices on the first layer (channel lengths, right shows transfer characteristics of a typical m which follows from the use of thin PI substrates widths and gate widths of 20, 170, and 5 m, inverter. (B) Transfer characteristics of a printed (25 mm), devices (<1.7 mm), and PI interlayers respectively, and ribbon thicknesses, widths, and complementary inverter that uses a p-channel lengths of 1.2, 10, and 150 mm, respectively), SWNT TFT (channel length and width of 30 and (1.5 mm), is their mechanical bendability. This SWNT devices on the second layer (channel lengths 200 mm, respectively) and an n-channel Si MOSFET characteristic is important for applications in and widths of 50 and 200 mm, respectively, and (channel length and width of 75 and 50 mm, flexible electronics, for which these systems average tube diameters and lengths of ~1.5 nm respectively). The insets provide an optical micro- might provide attractive alternatives because and ~10 mm, respectively), and Si devices on the graph of an inverter (left) and a circuit schematic of their enhanced capabilities compared with third layer (channel lengths and widths of 19 and (right). (C) Current-voltage response of a GaAs those of conventional organic-based devices. 200 mm, respectively). (D) (Left) Normalized trans- MSM (channel length and width of 10 and 100 mm, We evaluated the effective transconductance conductances (gm/g0m) of devices in each layer respectively) integrated with a Si MOSFET (channel (geff) for the Si, SWNT, and GaN devices in the (black squares, Si MOSFETs; red circles, SWNT TFTs; length and width of 9 and 200 mm, respectively) at system of Fig. 3A as a function of bend radius. green triangles, GaN HEMTs) as a function of bend- different levels of illumination from dark to 11 mW Figure 3D, which shows these data normalized ing radius of the plastic substrate. T,tension;C, with an infrared light source at 850 nm. The insets to the transconductance in the unbent state compression. (Right) Image of the bent system and show an optical image (left) and a circuit diagram (g0eff), demonstrates the stable performance for probing apparatus. (right). gnd, ground.

1756 15 DECEMBER 2006 VOL 314 SCIENCE www.sciencemag.org REPORTS interesting circuit capabilities. The thin polymer sistent with circuit simulation (fig. S7). A re- 10. P. Garrou, Semicond. Int. 28, SP10 (February, 2005). interlayers allow robust interconnects to be sponsivity of about 0.30 A/W at the 850-nm 11. H. Amano, N. Sawaki, I. Akasaki, Y. Toyoda, Appl. Phys. Lett. 48, 353 (1986). formed easily by evaporating metal lines over wavelength is observed from 1 to 5 V. (This value 12. T. Kuykendall et al., Nat. Mater. 3, 524 (2004). lithographically defined openings. Thermal underestimates the true responsivity because it 13. J. C. Bean, Proc. IEEE 80, 571 (1992). cycling tests showed no changes in their ignores optical reflection). The bendability of this 14. A. M. Morales, C. M. Lieber, Science 279, 208 (1998). properties (fig. S10). Figure 4A shows a 3D system, which is comparable to that of the devices 15. M. Law et al., Science 305, 1269 (2004). 16. J. Kong, H. T. Soh, A. M. Cassell, C. F. Quate, H. Dai, n-channel metal oxide semiconductor inverter in Fig. 3, could be useful for advanced systems Nature 395, 878 (1998). (logic gate) in which the drive (L =4mm, W = such as curved focal plane arrays for wide-angle 17. K. S. Novoselov et al., Science 306, 666 (2004). 200 mm) and load (L =4mm, W =30mm) Si infrared night vision imagers. 18. Y. Huang, X. Duan, C. M. Lieber, Small 1, 142 (2005). MOSFETs are on different levels. With a sup- Printed semiconductor nanomaterials provide 19. M. A. Meitl et al., Nat. Mater. 5, 33 (2006). ply voltage of 5 V, this double-layer inverter new approaches to 3D heterogeneously integrated 20.E.Menard,K.J.Lee,D.Y.Khang,R.G.Nuzzo,J.A.Rogers, Appl. Phys. Lett. 84, 5398 (2004). exhibits well-defined transfer characteristics systems that could be important in various fields 21. Y. Sun, S. Kim, I. Adesida, J. A. Rogers, Appl. Phys. Lett. with gains of ~2, comparable to the perform- of application, including not only those suggested 87, 083501 (2005). ance of conventional planar inverters that use by the systems reported here but also others such 22. S.-H. Hur, D.-Y. Khang, C. Kocabas, J. A. Rogers, similar transistors. Figure 4B shows an inverter as microfluidic devices with integrated electron- Appl. Phys. Lett. 85, 5730 (2004). 23. Materials and methods are available as supporting with a complementary design (CMOS) with the ics, chemical and biological sensor systems that material on Science Online. use of integrated n-channel Si MOSFETs and incorporate unusual materials with conventional 24. S. Linder, H. Baltes, F. Gnaedinger, E. Doering, in p-channel SWNT TFTs, designed to equalize silicon-based electronics, and photonic and Proceedings of the 7th IEEE International Workshop on the current-driving capability in both pull-up optoelectronic systems that combine light emit- Micro Electro Mechanical Systems, Oiso, Japan, 25 to 28 January 1994 (IEEE, Piscataway, NJ, 1994), pp. 349–354. and pull-down directions. Transfer curves col- ters and detectors of compound semiconductor 25. J.-H. Ahn et al., IEEE Electron Devices Lett 27, 460 (2006). lected with a supply voltage (VDD)of5Vand with silicon drive electronics or microelectro- 26. J. B. D. Soole, H. Schumacher, IEEE J. Quantum Electron. gate voltage (input) swept from 0 to 5 V ap- mechanical structures. Furthermore, the compat- 27, 737 (1991). pear in Fig. 4B. The curve shapes and gains ibility of this approach with thin, lightweight 27. The research was supported by the U.S. Department of Energy, Division of Materials Sciences under award no. (as high as ~7) are qualitatively consistent plastic substrates may create additional oppor- DEFG02-91ER45439, through the Frederick Seitz Materials with numerical circuit simulations (fig. S6). tunities for devices that have unusual form Research Laboratory (FS-MRL). We thank T. Banks and As a third example, we built GaAs metal- factors or mechanical flexibility as key features. K. Colravy for help with cleanroom and other facilities at the semiconductor-metal (MSM) infrared detectors Frederick Seitz Materials Research Laboratory and H. C. Ko,

Q. Cao, P. Ferreira, J. Dong, and E. Menard for help with on December 14, 2006 (26), integrated with Si MOSFETs on flexible PI printing and distortion measurements using facilities and substrates, to demonstrate a capability for fab- References and Notes 1. K. Banerjee, S. J. Souri, P. Kapur, K. C. Saraswat, manufacturing approaches developed at the Center for ricating unit cells that could be used in active Proc. IEEE 89, 602 (2001). Nanoscale Chemical Electrical Mechanical Manufacturing infrared imagers. In this case, printed nano- 2. S. F. Al-Sarawi, D. Abbott, P. D. Franzon, IEEE Trans. Systems at the University of Illinois (funded by the NSF under ribbons of GaAs (L = 400 mm, W = 100 mm, and Components Packaging Manufacturing Technol. Part B grant DMI-0328162). All imaging and surface analysis was performed at the FS-MRL Center for Microanalysis of thickness = 270 nm) transferred onto a substrate 21, 2 (1998). 3. A. S. Brown et al., Mater. Sci. Eng. B 87, 317 (2001). Materials at the University of Illinois at Urbana-Champaign, with a printed array of Si nanoribbon MOSFETs 4. Y.-C. Tseng et al., Nano Lett. 4, 123 (2004). supported by award no. DEFG02-91ER45439. form the basis of the MSMs. Electrodes (Ti/Au) 5. C. Joachim, J. K. Gimzewski, A. Aviram, Nature 408, 541 Supporting Online Material deposited on the ends of these GaAs nanoribbons (2000). www.sciencemag.org/cgi/content/full/314/5806/1754/DC1 6. G. Roelkens et al., Opt. Express 13, 10102 (2005). www.sciencemag.org form back-to-back Schottky diodes with sepa- Materials and Methods m 7. D. B. Strukov, K. K. Likharev, Nanotechnology 16, 888 (2005). rations of 10 m. The resulting detector cells 8. Q. Y. Tong, U. Gosele, Semiconductor Wafer Bonding: Figs. S1 to S15 exhibit current enhancement as the intensity of Science and Technology (John Wiley, New York, 1999). 12 July 2006; accepted 31 October 2006 infrared illumination increases (Fig. 4C), con- 9. M. A. Schmidt, Proc. IEEE 86, 1575 (1998). 10.1126/science.1132394

Hall effect can in principle exist in band in- sulators, where the spin current can flow without Quantum Spin Hall Effect and dissipation. Motivated by this suggestion, re- Downloaded from searchers have proposed the quantum spin Hall Topological Phase Transition in (QSH) effect for graphene (7)aswellasfor semiconductors (8, 9), where the spin current is HgTe Quantum Wells carried entirely by the helical edge states in two- dimensional samples. B. Andrei Bernevig,1,2 Taylor L. Hughes,1 Shou-Cheng Zhang1* Time-reversal symmetry plays an important role in the dynamics of the helical edge states We show that the quantum spin Hall (QSH) effect, a state of matter with topological properties (10–12). When there is an even number of pairs distinct from those of conventional insulators, can be realized in mercury telluride–cadmium of helical states at each edge, impurity scattering telluride semiconductor quantum wells. When the thickness of the quantum well is varied, the or many-body interactions can open a gap at the electronic state changes from a normal to an “inverted” type at a critical thickness dc. We show that edge and render the system topologically trivial. this transition is a topological quantum phase transition between a conventional insulating phase However, when there is an odd number of pairs and a phase exhibiting the QSH effect with a single pair of helical edge states. We also discuss of helical states at each edge, these effects can- methods for experimental detection of the QSH effect. not open a gap unless time-reversal symmetry is

he spin Hall effect (1–5) has recently at- tronics. In particular, the intrinsic spin Hall effect 1Department of Physics, Stanford University, Stanford, CA tracted great attention in condensed mat- promises the possibility of designing the intrinsic 94305, USA. 2Kavli Institute for Theoretical Physics, University Tter physics, not only for its fundamental electronic properties of materials so that the effect of California, Santa Barbara, CA 93106, USA. scientific importance but also because of its can be maximized. On the basis of this line of *To whom correspondence should be addressed. E-mail: potential application in semiconductor spin- reasoning, it was shown (6) that the intrinsic spin [email protected]

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