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Eindhoven University of Technology MASTER Transputer Design and Simulation in Idass Van Hassel, M.C.J.M

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Eindhoven University of Technology MASTER Transputer Design and Simulation in Idass Van Hassel, M.C.J.M Eindhoven University of Technology MASTER Transputer design and simulation in IDaSS van Hassel, M.C.J.M. Award date: 1994 Link to publication Disclaimer This document contains a student thesis (bachelor's or master's), as authored by a student at Eindhoven University of Technology. Student theses are made available in the TU/e repository upon obtaining the required degree. The grade received is not published on the document as presented in the repository. The required complexity or quality of research of student theses may vary by program, and the required minimum study period may vary in duration. General rights Copyright and moral rights for the publications made accessible in the public portal are retained by the authors and/or other copyright owners and it is a condition of accessing publications that users recognise and abide by the legal requirements associated with these rights. • Users may download and print one copy of any publication from the public portal for the purpose of private study or research. • You may not further distribute the material or use it for any profit-making activity or commercial gain Technische Universiteit tU) Eindhoven Faculty of Electrical Engineering Digital Information Systems Group Master's thesis: TRANSPUTER DESIGN AND SIMULATION IN IDASS lng. M. C.J.M. van Hassel Coach : Dr. ir. A.C. Verschueren Supervisor : Prof. ir. M.PJ. Stevens Period : September 1993 - August 1994 The Faculty of Electrical Engineering of Eindhoven University of Technology does not accept any responsibility regarding the contents of Master's theses. ABSTRACT This master thesis is the conclusion of my graduation period at Eindhoven University of Technology. This report describes the design and implementation in lDaSS of a transputer, based on the IMS T800 from INMOS. Transputers are microprocessors that can be connected directly with each other via on-chip link interfaces. In this way a network of transputers can easily be build. This enables parallel computing. A transputer also contains an internal process scheduler. This enables parallel processing. IDaSS is an interactive design and simulation environment for digital circuits. It is developed by my coach Dr. Ir. A.C. Verschueren. In lDaSS a transputer is implemented with four link interfaces, two timers. an event channel and a process scheduler. The floating-point unit and the dynamic RAM interface are not implemented because of time constraints. But these blocks already exist in the IDaSS design library. The goal was to implement a transputer core, based on the INMOS T800. Most typical transputer features are implemented. So the goal has been reached to a large extent. Furthermore during this graduation period I have written an AWK tool for stripping lDaSS documentation files from not useful text. Because my coach and other IDaSS users were very interested. I adjusted this tool to the recommendations of my coach and spread it. The usage and working of this tool is briefly described in this report. This tool can only strip documentation files from IDaSS version VO.08m. The next IDaSS version will make this tool superfluous. iii PREFACE This report is the master thesis for my graduation at the Eindhoven University of Technology. It concludes the three years I have spent at this university to acquire the title 'Ir' in the field of Information Technology in continuation of the highschool of technology in Breda. In order to reduce the size of appendices, I used my AWK tool to shrink the loads of documentation generated by lDaSS. If anyone would like to obtain the original lDaSS design files and/or the AWK tool, then contact Dr. Ir. A.C. Verschueren at the Digital Systems Group (EBI. He can also be reached via email at:[email protected]. Here I would like to take the opportunity to thank some people who made my graduation possible and joyful: • Ad Verschueren for the very good coaching. • All students and co-workers at the Digital Systems Group for helping me anyhow and for making my graduation period enjoyable. • Mark Venbrux for sharing his house with me for two very joyful years. • The Walhalla and the AOR for cheap beer. • My parents and my girlfriend Lianda de Jong for pushing me to carryon and for giving me the opportunity to study. • Minister Ritzen for waiting to restrict the study freedom and for waiting to economize on the scholarship and free travelling after I finished studying. • Everybody else who contributed in any way to the success of my study. Thanks! Marco van Hassel v TABLE OF CONTENTS 1. INTRODUCTION............................................. i 1.1 History ............................................ .. 1 1.2 Multiprocessor systems ........................ .. 2 1.3 Applications. ....................................... .. 4 1.4 Comparison with other multiprocessor systems 5 1.4.1 TMS320C40....................................... 5 1.4.2 iWarp............................................ 6 1.4.3 POOL and DOOM. ................................. .. 6 2. OCCAM 7 3. IMS T800 9 3.1 System services 10 3.2 External memory interface 11 3.3 Internal RAM 11 3.4 CPU ............................................. .. 12 3.4.1 Registers 12 3.4.2 Instructions....................................... 13 3.4.3 ..Scheduler ........................... .. 13 3.4.4 Communication through channels 15 3.5 Floating point unit ................................... .. 17 3.6 Links " , 17 3.7 Events " 19 3.8 Timers. .......................................... .. 19 4. IDASS................................................... 23 4.1 Converting an IDaSS design to silicon 24 5. IMPLEMENTATION OF THE TRANSPUTER " 25 5.1 Interfacing with the outside world ........................ .. 26 5.2 Internal memory interfacing 27 5.3 The Z-bus protocol 28 5.4 Timing of the links and timers ........................... .. 29 6. TEST SYSTEM ........................................... .. 31 7. IMPLEMENTATION OF RAM AND ROM " 33 7.1 Internal and external RAM 33 7.2 RO M 34 8. IMPLEMENTATION OF THE BUS MULTIPLEXER .................... .. 35 8.1 Selection. ........................................ .. 36 8.2 Arbitration " 37 8.3 Multiplex unit 38 9. IMPLEMENTATION OF SYSTEM SERVICES •...................... " 41 vii TRANSPUTER DESIGN AND SIMULA TION IN IDASS 10. IMPLEMENTATION OF THE EXTERNAL MEMORY INTERFACE. ......... .. 45 11. IMPLEMENTATION OF THE TIMERS ••••••.•.. ..••.....•.••.••.• .. 47 11 .1 Timer 0 ...........••...........•.............•..... 47 11 .2 Timer 1 ..•...•.•...•.........•..................... 48 12. IMPLEMENTATION OF THE LINKS •.....•••.......••....•..•••... 51 12.1 The bus multiplexer •.••.•.............•.............. .. 52 12.2 Link control .•....•.....•........•...........•....... 53 12.3 Link interface ..•.........•.•.....•................... 53 12.3.1 The bus multiplexer .....•......•........•........... 54 12.3.2 Link output ....•.....•.............•.............. 56 12.3.3 Link input •.....•••...................•........... 59 13. IMPLEMENTATION OF THE EVENT CHANNEL .•...•••............... 63 14. IMPLEMENTATION OF THE CPU ••••••........•..••............• 65 14.1 The fetcher. .............•......................... .. 65 14.2 The decoder ..............•........................ .. 67 14.3 The load/store unit 68 14.4 The workspace cache 70 14.5 The Z-bus arbiter. .•................................. .. 71 14.6 The scheduler ...................................... .. 71 14.6.1 Arbitration of the requests 73 14.6.2 State control , 74 14.6.3 Scheduling a process ....................... .. 76 14.6.4 Extracting a process " 77 14.7 The executer 78 14.7.1 State number and instruction control 81 14.7.2 Stack manipulations ............................... .. 82 14.7.3 Loading and storing ...•............................. 84 14.7.4 Z-bus communications ...............•............... 84 15. EXECUTION OF INSTRUCTIONS. •.•.•...•.......••.•..•..•..•. .. 87 16. PERFORMANCE ......•.••..•.•••.•....•.•••••.••.•....•.... 97 17. STRIPPING IDASS DOCUMENT FILES .••............•.•........ .. 105 17.1 Usage of the stripper •..•........... ........•........ .. 105 17.2 Explanation of the AWK program 106 18. CONCLUSIONS ......•.•••.•••.•••.••.•...•...•.......•..• 107 19. RECOMMENDATIONS .••••••••••••••••..•.•.•..•.•.•..•... .. 109 REFERENCES •••••..••....•.•.•.••.•••••••..••.••....•...•••. 111 INDEX .••.•..•....•....•..••••.••••.......••.•.•.......•.. 11 5 available as separate documentation: APPENDICES : Design documentation viii 1.INTRODUCTION 1.1 History The first idea for the transputer stems from 1975, when Ian Barron had the idea that it should be possible to build a processor on a single chip which could be used as a building block for larger parallel computers, or even supercomputers. Along with this processor a high level language had to be provided to use all of its possibilities. In 1984 the technology had advanced far enough for the first transputer to built. It became possible to place a processor with memory (not much) and communication facilities on a single chip. The first transputer was built by the firm INMOS and was for testing purposes only. In September 1985 the first commercial transputer was made by the same firm. This was the T414a. The T414a became successful when INMOS produced an adapter for the IBM's Personal Computer and released the language OCCAM 1, to program the transputer. Unfortunately, there were a number of flaws to the T414a and OCCAM 1. The T414a did not have a floating point unit and OCCAM 1 provided no alternative. OCCAM 1 did not support functions, nor the
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