Transputer Architecture
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Inmos T800 Transputer)
PARALLEL ALGORITHM DEVELOPMENT FOR A SPECIFIC MACHINE (INMOS T800 TRANSPUTER) BY WILLIAM STAUB 1 This paper will desribe from start to finish the parallel algorithm program development for a specific transputer (Inmos T800) network. It is essential to understand how the hardware manages parallel tasks and how information is exchanged between the transputers before writing a parallel program. A transputer (figure1, page3) is a circuit containing a processor, some memory to store programs and data, and several ports for exchanging, or transferring information with other transputers or with the outside world. By designing these circuits so that they could be connected together with the same simplicity with which transistors can be in a computer, the transputer was born. One of the most important factor was the introduction of a high-level language, occam [MAY83], whose features were directly supported by this transputer’s hardware and that made the transputer a building block for parallel computers. However a Locical System C compiler was developed for wider know usage. A prominent factor to utilizing this circuitry was the ease with which transputers could be connected to each other with as little as a few electrical wires. The four bi- directional input/output (I/O) ports of the transputer are designed to interface directly with the ports of other transputers, his feature allows for several transputers to fit on a small footprint, with very little extra logic circuits, making it possible to easily fit four transputers with some memory on a PC daughter board (ISA bus). 2 Figure 1: Transputer block-diagram and examples of interconnection networks. -
A Low Cost, Transputer Based Visual Display Processor G.J. Porter, B
Transactions on Information and Communications Technologies vol 3, © 1993 WIT Press, www.witpress.com, ISSN 1743-3517 A low cost, transputer based visual display processor G.J. Porter, B. Singh, S.K. Barton Department of Electronic and Electrical Engineering, University of Bradford, Richmond Road, Bradford, West Yorkshire, UK ABSTRACT As major computer systems and in particular parallel computing resources become more accessible to the engineer, it is becoming necessary to increase the performance of the attached video display devices at least pro-rata with those of the computational elements. To this end a number of device manufacturers have developed or are in the process of developing new display controllers, dedicated to the task of improving the display environments of the super computers in use today by engineers. There is however a price to be paid for this development, in terms of monetary cost and in the design effort involved in integrating the new technology into existing systems. This paper will present a solution to this problems. Firstly, by showing how to utilise available transputer technology to upgrade the display capability of existing systems by transferring some of the available processing power from the computational elements of the system to the display controller. Secondly, by utilising a low cost off-the-shelf Transputer Module based video display unit. The new video display processor utilises a three transputer pipeline formed from as Scan Converter Unit, a Span Encoder Unit and a Span Filler Unit, and can be further expanded by increasing the functionality and/or parallelism of each stage if required. 1. -
A Distributed Transputer-Based Architecture Using a Reconfigurable Synchronous Communication Protocol
A DISTRIBUTED TRANSPUTER-BASED ARCHITECTURE USING A RECONFIGURABLE SYNCHRONOUS COMMUNICATION PROTOCOL Marie Josette Brigitte Vachon B.A.Sc. Royal Military College, Kingston, 1984 A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF MASTER OF APPLIED SCIENCE in THE FACULTY OF GRADUATE STUDIES DEPARTMENT OF ELECTRICAL ENGINEERING We accept this thesis as conforming to the required standard THE UNIVERSITY OF BRITISH COLUMBIA August 1989 © Marie Josette Brigitte Vachon s 1989 In presenting this thesis in partial fulfilment of the requirements for an advanced degree at the University of British Columbia, I agree that the Library shall make it freely available for reference and study. I further agree that permission for extensive copying of this thesis for scholarly purposes may be granted by the head of my department or by his or her representatives. It is understood that copying or publication of this thesis for financial gain shall not be allowed without my written permission. Department of E^(Lm\OAL. k)ZF.P\*iU The University of British Columbia Vancouver, Canada Date IC AVC I J8 7 DE-6 (2/88) Abstract A reliable, reconfigurable, and expandable distributed architecture supporting both bus and point- to-point communication for robotic applications is proposed. The new architecture is based on Inmos T800 microprocessors interconnected through crossbar switches, where communication between nodes takes place via point-to-point bidirectional links. Software development is done on a host computer, Sun 3/280, and the executable code is downloaded to the distributed architecture via the bus. Based on this architecture, an operating system has been designed to provide communication and input/output support. -
Design of a Neural Network Simulator on a Transputer Array
DESIGN OF A NEURAL NETWORK SIMULATOR ON A TRANSPUTER ARRAY Gary Mclntire James Villarreal, Paul Baffes, and Advanced Systems Engineering Dept. Ford Monica Rua Artificial Intelligence Section, Aerospace, Houston, TX. NASNJohnson Space Center, Houston, TX. Abstract they will be commercially available. Even if they were available today, they would be A high-performance simulator is being built generally unsuitable for our work because to support research with neural networks. All they are very difficult (usually impossible) to of our previous simulators have been special reconfigure programmably. A non-hardwired purpose and would only work with one or two VLSl neural network chip does not exist today types of neural networks. The primary design but probably will exist within a year or two. If goal of this simulator is versatility; it should done correctly, this would be ideal for our be able to simulate all known types of neural simulations. But the state of the art in networks. Secondary goals, in order of reconfigurable simulators are supercomputers importance, are high speed, large capacity, and and parallel processors. We have a very fast ease of use. A brief summary of neural simulator running on the SX-2 supercomputer networks is presented herein which (200 times faster than our VAX 11/780 concentrates on the design constraints simulator), but supercomputer CPU time is imposed. Major design issues are discussed yfzy costly. together with analysis methods and the chosen For the purposes of our research, solutions. several parallel processors were investigated Although the system will be capable of including the Connection Machine, the BBN running on most transputer architectures, it Butterfly, and the Ncube and Intel Hypercubes. -
The Helios Operating System
The Helios Operating System PERIHELION SOFTWARE LTD May 1991 COPYRIGHT This document Copyright c 1991, Perihelion Software Limited. All rights reserved. This document may not, in whole or in part be copied, photocopied, reproduced, translated, or reduced to any electronic medium or machine readable form without prior consent in writing from Perihelion Software Limited, The Maltings, Charlton Road, Shepton Mallet, Somerset BA4 5QE. UK. Printed in the UK. Acknowledgements The Helios Parallel Operating System was written by members of the He- lios group at Perihelion Software Limited (Paul Beskeen, Nick Clifton, Alan Cosslett, Craig Faasen, Nick Garnett, Tim King, Jon Powell, Alex Schuilen- burg, Martyn Tovey and Bart Veer), and was edited by Ian Davies. The Unix compatibility library described in chapter 5, Compatibility,im- plements functions which are largely compatible with the Posix standard in- terfaces. The library does not include the entire range of functions provided by the Posix standard, because some standard functions require memory man- agement or, for various reasons, cannot be implemented on a multi-processor system. The reader is therefore referred to IEEE Std 1003.1-1988, IEEE Stan- dard Portable Operating System Interface for Computer Environments, which is available from the IEEE Service Center, 445 Hoes Lane, P.O. Box 1331, Pis- cataway, NJ 08855-1331, USA. It can also be obtained by telephoning USA (201) 9811393. The Helios software is available for multi-processor systems hosted by a wide range of computer types. Information on how to obtain copies of the Helios software is available from Distributed Software Limited, The Maltings, Charlton Road, Shepton Mallet, Somerset BA4 5QE, UK (Telephone: 0749 344345). -
1 Architecture Reference Manual 2 T414 Transputer Product Data
Contents 1 Architecture reference manual 2 T414 transputer product data 3 T212 transputer product data 4 C011 link adaptor product data 5 C012 link adaptor product data omrnos® Reference manual • transputer architecture 8, inmos, IMS and occam are trade marks of the INMOS Group of Companies. INMOS reserves the right to make changes in specifications at any time and without notice. The information furnished by INMOS in this publication is believed to be accurate; however no responsibility is assumed for its use, nor for any infringements of patents or other rights of third parties resulting from its use. No licence is granted under any patents, trademarks or other rights of the INMOS Group of Companies. Copyright INMOS Limited, 1986 72 TRN 048 02 2 Contents 1 Introduction 5 1.1 Overview 6 1.2 Rationale 7 1.2.1 System design 7 1.2.2 Systems architecture 8 1.2.3 Communication 9 2 Occam model 11 2.1 Overview 11 Occam overview 12 2.2.1 Processes 12 2.2.2 Constructs 13 2.2.3 Repetition 15 2.2.4 Replication 15 2.2.5 Types 16 2.2.6 Declarations, arrays and subscripts 16 2.2.7 Procedures 17 2.2.8 Expressions 17 2.2.9 Timer 17 2.2.10 Peripheral access 18 2.3 Configuration 18 3 Error handling 19 ~------------------------------------------------------~-- _4___ P_rogram_ develo-'-p_m_e_n_t__________ _ 20 4.1- Performance measurement 20 ------------------ ~~--~------~~--~-------------------~-- 4.2 Separate compilation of occam and other languages 20 4.3 Memory map and placement 21 5 Physical architecture 22 5.1 INMOS serial links 22 5.1.1 Overview 22 5.1.2 Electrical specification of links 22 ------5~.~2---=S-ys-t-e--m-se-r-v~ic-e-s-~-------------------------------~23 ---------- 5.2.1 Powering up and down, running and stopping 23 5.2.2 Clock distribution 23 5.3 Bootstrapping from ROM or from a link 23 ------5-.-4--P-e-r-ip-h-eral interfacing 24 6 Notation conventions 26 6.1 Signal naming conventions 26 7 Transputer product numbers 27 3 Preface This manual describes the architecture of the transputer family of products. -
ISRA VISION at a Glance
ISRA VISION Initiating Coverage 18 February 2019 Better than the human eye – Growth story is expected continue In a highly fragmented market environment ISRA VISION ranks Target price (EUR) 36 Share price (EUR) 28 among the leading players for machine vision technologies with a strong focus on software solutions. Driven by market trends as well as R&D efforts, we expect ISRA’s growth story to continue and Forecast changes forecast a revenue growth CAGR of 10.4% until FY 2022/23e. EBIT % 2019e 2020e 2021e is expected to increase by 10.6% during this period. In addition to organic growth, M&A driven growth is very likely. We initiate the Revenues NM NM NM EBITDA NM NM NM coverage of ISRA VISION with Buy and a TP of EUR 36.00. EBIT adj NM NM NM EPS reported NM NM NM EPS adj NM NM NM ISRA VISION among the technology leaders Source: Pareto ISRA is one of the leading providers for machine vision solutions with specialisation in 3D machine vision. The company’s Ticker ISRG.DE, ISR GR competences are mainly concentrated around the internally Sector Industrials developed software application. Future demand is driven by more Shares fully diluted (m) 21.9 Market cap (EURm) 605 complexity and miniaturization, quality requirements and entering Net debt (EURm) -18 into new markets. Customer benefits are cost savings, process Minority interests (EURm) 2 optimization, higher flexibility and a ROI of clearly <1 year. Enterprise value 19e (EURm) 590 Free float (%) 65 Growth story should continue - 5yrs growth CAGR of 10.4% The well diversified customer base in various end-markets helps ISRA to reduce cyclicality. -
Uva-DARE (Digital Academic Repository)
UvA-DARE (Digital Academic Repository) Scalable distributed data structures for database management Karlsson, S.J. Publication date 2000 Document Version Final published version Link to publication Citation for published version (APA): Karlsson, S. J. (2000). Scalable distributed data structures for database management. General rights It is not permitted to download or to forward/distribute the text or part of it without the consent of the author(s) and/or copyright holder(s), other than for strictly personal, individual use, unless the work is under an open content license (like Creative Commons). Disclaimer/Complaints regulations If you believe that digital publication of certain material infringes any of your rights or (privacy) interests, please let the Library know, stating your reasons. In case of a legitimate complaint, the Library will make the material inaccessible and/or remove it from the website. Please Ask the Library: https://uba.uva.nl/en/contact, or a letter to: Library of the University of Amsterdam, Secretariat, Singel 425, 1012 WP Amsterdam, The Netherlands. You will be contacted as soon as possible. UvA-DARE is a service provided by the library of the University of Amsterdam (https://dare.uva.nl) Download date:11 Oct 2021 atabasee Management Scalablee Distributed Data Structures s for r Databasee Management Academischh Proefschrift terr verkrijging van de graad van doctor aann de Universiteit van Amsterdam opp gezag van de Rector Magnificus prof.. dr. J. J. M. Franse tenn overstaan van een door het collegee voor promoties ingestelde commissie, inn het openbaar te verdedigen inn de Aula der Universiteit opp donderdag 14 december 2000, te 11.00 uur doorr Jonas S Karlsson geborenn te Enköping, Sweden Promotor:: Prof. -
STATUS REPORT Sc? (1@’Rq» Lu? Ul __ V? 211 — Q CERN Participation in the GP MIMD ESPRIT Project
CERN LIBRARIES, GENEVA CERN/DRDU 9 1-12 Danc/M5 llltlllllllllulll II\)Illll|lI)I|l)H)|lllllI|ll)) afch , ;, — P A $(100000690 <_ fri · \ xg ·-J ’ STATUS REPORT Sc? (1@’rQ» lu? Ul __ V? 211 — Q CERN participation in the GP MIMD ESPRIT project P.C. Burkimsher, R.W. Dobinson ' , A. King, B. Martin, and I.M. Willers, CERN. J—L. Pages, University of Lausanne A. Schneider, University of Geneva. In collaboration with INMOS (UK), lead partner. Meiko (UK), Parsys (UK), Parsytec (D) and Telmat (F), main partners. and Grupo APD (E), INESC (P), Siemens (D), SICS (S), Southampton University (UK), IRISA (F) OCR Output spokesman z JMU Introduction A proposal was submitted to ESPRIT in January 1990 by INMOS and four European manufacturers of Transputer based computers. The aim of the proposal is to develop high performance parallel processing computers using a new generation of Transputers. ESPRIT is the EEC supported European Strategic Programme for Research and Development in Information Technology. The technical, manpower and budget details of the project are contained in the technical annex [l] of the official contract that has been signed by the lead and main project partners with the EEC. CERN has taken part in the preparatory work for the GP MIMD ESPRIT proposal and must now decide on the continuation of this work within the framework of the approved project. Transputer Technology Today's microprocessors make available on a single chip a significant fraction of the computing performance of a traditional mainframe. A recent trend has been to construct very powerful computing systems of interconnected microprocessors: up to hundreds or even thousands of processor nodes, each with local memory, joined by a fast switching network. -
ALTERNATING-DIRECTION LINE-RELAXATION METHODS on MULTICOMPUTERS* J)RN HOFHAUS and ERIC E VAN DE VELDE$ Abstract
SIAM J. ScI. COMPUT. () 1996 Society for Industrial and Applied Mathematics Vol. 17, No. 2, pp. 454-478, March 1996 010 ALTERNATING-DIRECTION LINE-RELAXATION METHODS ON MULTICOMPUTERS* J)RN HOFHAUS AND ERIC E VAN DE VELDE$ Abstract. We study the multicomputer performance of a three-dimensional Navier-Stokes solver based on alternating-direction line-relaxation methods. We compare several multicomputer implementations, each of which combines a particular line-relaxation method and a particular distributed block-tridiagonal solver. In our experiments, the problem size was determined by resolution requirements of the application. As a result, the granularity of the computations of our study is finer than is customary in the performance analysis of concurrent block-tridiagonal solvers. Our best results were obtained with a modified half-Gauss-Seidel line-relaxation method implemented by means of a new iterative block-tridiagonal solver that is developed here. Most computations were performed on the Intel Touchstone Delta, but we also used the Intel Paragon XP]S, the Parsytec SC-256, and the Fujitsu S-600 for comparison. Key words. Navier-Stokes equations, concurrency, parallelism, block-tridiagonal systems, tridiagonal systems, ADI, alternating directions AMS subject classifications. 65M20, 65N40, 65Y05, 76C05, 76M20 1. Introduction. When using alternating-direction line-relaxation methods for systems of partial-differential equations discretized on a rectangular grid, one must solve many block- tridiagonal systems of linear equations in every relaxation step. This type of computation surfaces in many applications. In our work, we faced it when parallelizing a highly vectorized solver for the three-dimensional, unsteady, and incompressible Navier-Stokes equations [4] for use on multicomputers. -
Implementation of an Environment for Monte Carlo Simulation of Fully 3-D Positron Tomography on a High-Performance Parallel Platform
Parallel Computing 24 (1998) 1523±1536 Implementation of an environment for Monte Carlo simulation of fully 3-D positron tomography on a high-performance parallel platform Habib Zaidi *, Claire Labbe, Christian Morel Division of Nuclear Medicine, Geneva University Hospital CH-1211 Geneva 4, Switzerland Received 15 January 1998; received in revised form 15 April 1998 Abstract 12/02/1998 ext-2001-007 This paper describes the implementation of the Eidolon Monte Carlo program designed to simulate fully three-dimensional (3-D) cylindrical positron tomographs on a MIMD parallel architecture. The original code was written in Objective-C and developed under the NeXT- STEP development environment. Dierent steps involved in porting the software on a parallel architecture based on PowerPC 604 processors running under AIX 4.1 are presented. Basic aspects and strategies of running Monte Carlo calculations on parallel computers are de- scribed. A linear decrease of the computing time was achieved with the number of computing nodes. The improved time performances resulting from parallelisation of the Monte Carlo calculations makes it an attractive tool for modelling photon transport in 3-D positron tomography. The parallelisation paradigm used in this work is independent from the chosen parallel architecture. Ó 1998 Elsevier Science B.V. All rights reserved. Keywords: Monte Carlo simulation; Positron emission tomography; Random numbers; Image recon- struction; Parallel computer 1. Introduction Positron emission tomography (PET) is a well-established imaging modality which provides physicians with information about the body's chemistry not available through any other procedure. Three-dimensional (3-D) PET provides qualitative and * Corresponding author. E-mail: [email protected] 0167-8191/98/$ ± see front matter Ó 1998 Elsevier Science B.V. -
Logp: Towards a Realistic Model of Parallel Computation
LogP: Towards a Realistic Model of Parallel Computation David Culler, Richard Karp,y David Patterson, Abhijit Sahay, Klaus Erik Schauser, Eunice Santos, Ramesh Subramonian, and Thorsten von Eicken Computer Science Division, University of California, Berkeley Abstract A vast body of theoretical research has focused either on overly simplistic models of parallel computation, notably the PRAM, or overly specific models that have few representatives in the real world. Both kinds of models encourage exploitation of formal loopholes, rather than rewarding development of techniques that yield performance across a range of current and future parallel machines. This paper offers a new parallel machine model, called LogP, that reflects the critical technology trends underlying parallel computers. It is intended to serve as a basis for developing fast, portable parallel algorithms and to offer guidelines to machine designers. Such a model must strike a balance between detail and simplicity in order to reveal important bottlenecks without making analysis of interesting problems intractable. The model is based on four parameters that specify abstractly the computing bandwidth, the communi- cation bandwidth, the communication delay, and the efficiency of coupling communication and computation. Portable parallel algorithms typically adapt to the machine configuration, in terms of these parameters. The utility of the model is demonstrated through examples that are implemented on the CM-5. Keywords: massively parallel processors, parallel models, complexity analysis, parallel algo- rithms, PRAM 1 Introduction Our goal is to develop a model of parallel computation that will serve as a basis for the design and analysis of fast, portable parallel algorithms, i.e., algorithms that can be implemented effectively on a wide variety of current and future parallel machines.