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2.1 Accelerators to Reduce Power Consumption Feasibility of Accelerator Generation to Alleviate Dark Silicon in a Novel Architecture Antonio ARNONE PhD UNIVERSITY OF YORK Computer Science June 2017 iii Abstract This thesis presents a novel approach to alleviating Dark Silicon problem by reduc- ing power density. Decreasing the size of transistor has generated an increasing on power consump- tion. To attempt to manage the power issue, processor design has shifted from one single core to many cores. Switching on fewer cores while the others are off helps the chip to cool down and spread power more evenly over the chip. This means that some transistors are always idle while others are working. Therefore, scaling down the size of the chip, and increasing the amount of power to be dissipated, increases the number of inactive transistors. As a result it generates Dark Silicon, which dou- bles every chip generation [63] One of the most effective techniques to deal with Dark Silicon is to implement accelerators that execute the most energy consumer software functions. In this way the CPU is able to dissipate more energy and reduce the dark silicon issue. This work explores a novel accelerator design model which could be interfaced to a Stack CPU and so could optimise the transistor logic area and improve energy effi- ciency to tackle the dark silicon problem based on heterogeneous multi-accelerators (co-processor) in stack structure. The contribution of this thesis is to develop a tool to generate coprocessors from software stack machine code. But it also employs up-to-date code optimisation strategies to enhance the code at the input stage. Analysis of the cores using key metrics, based on 65nm synthesis experiments and industry standard tool-sets. It further introduces a novel architecture to decrease the power density of the acceler- ator. In order to test these expectations, a large-scale synthesis translation experiment was conducted, covering widely recognised benchmarks, and generating a large number of cores (in the thousands). These were evaluated for a range of key metrics: silicon di-area, timing, power, instructions-per-clock, and power density, both with and without code optimisation applied. The results obtained demonstrate that one of two competing core models, ‘Wave- core’ (which is proposed in this thesis), delivers superior power density to the stan- dard approach (which it refers to as Composite core), and that this is achieved with- out significant cost in terms of critical metrics of overall power consumption and critical path delays. Finally, to understand the benefit of these accelerators, these auto-generated cores are analysed in comparison to a standard stack-machine CPU executing the same code sequences. Both the cores generation work and the benchmark CPU assume a 65nm CMOS process node, and are evaluated with industry standard design tools. It is demonstrated that the generated cores achieve better power efficiency improve- ments over the relatively CPU core. v Contents Abstract iii Acknowledgements xv Declaration of Authorship xvii 1 Introduction1 1.1 Hypothesis...................................2 1.2 Novel Contributions.............................3 1.3 Scaling vs Power...............................4 1.4 ARM architecture, 35 years of RISC architecture.............6 1.4.1 Register File and Pipeline architecture...............6 1.5 The History of Stack Architecture......................8 1.5.1 Stack Architecture, a simple architecture............. 10 1.6 Dark Silicon.................................. 13 1.6.1 The Key approaches to improving dark silicon.......... 13 1.7 Summary:................................... 15 2 Accelerator cores and Translator tool 17 2.1 Accelerators to reduce power consumption................ 19 2.2 Low Power Concept............................. 21 2.3 Design Flow.................................. 24 2.4 Accelerator generation; design flow.................... 26 2.5 SW/HW Function translation........................ 28 2.5.1 The Translator tool in detail..................... 32 2.5.2 Testing the translator tool...................... 34 2.6 The Verilog test bench............................ 41 2.7 The Composite Cores Architecture..................... 49 2.8 The Wave-core Architecture......................... 49 2.8.1 The Wave-core architecture: An idea to reduce power...... 50 2.9 Summary:................................... 51 3 Standard Core Generation Experiment 53 3.1 The Baseline core bench marks Input Comparison............ 55 3.1.1 Input operands per core (Smaller benchmarks, baseline case). 55 3.1.2 Input operands per core (Larger benchmarks, baseline case).. 58 3.1.3 Input operands per core (All benchmarks, baseline case).... 58 3.2 The Baseline core benchmarks Output Comparison........... 59 3.2.1 Output operands per core (Smaller benchmarks, baseline case) 59 3.2.2 Output operands per core (Larger benchmarks, baseline case). 59 3.2.3 Output operands per core (All benchmarks, baseline case)... 59 3.3 The number of states in the Finite State Machine............. 62 3.3.1 Number of states per core (Smaller benchmarks, baseline case) 62 vi 3.3.2 Number of states per core (Larger benchmarks, baseline case). 65 3.3.3 Number of states per core (All benchmarks, baseline case)... 65 3.4 The Number of Instructions per Clock Cycle............... 65 3.5 Composite vs Wave-core Total Area.................... 69 3.6 Composite vs Wave-core Timing...................... 72 3.7 Composite vs Wave-core Leakage...................... 73 3.8 Composite vs Wave-core Dynamic power................. 74 3.9 Composite vs Wave-core Total power................... 76 3.10 Composite vs Wave-core Power Density.................. 77 3.11 Composite vs Wave-core Dynamic power for cores with Multiple States 79 3.12 Summary:................................... 82 4 Impact of Code Optimisation (Stack Scheduling Code) 85 4.1 Comparison of Optimised Cores’ Input.................. 86 4.1.1 Input operands per core (Smaller benchmarks, with optimiza- tion).................................. 87 4.1.2 Input operands per core (Larger benchmarks, with optimization) 89 4.1.3 Input operands per core (all benchmarks, with optimization). 89 4.2 Comparison of Optimised Cores’ Output................. 89 4.2.1 Output operands per core (Smaller benchmarks, with optimiza- tion).................................. 91 4.2.2 Output operands per core (Larger benchmarks, with optimiza- tion).................................. 93 4.2.3 Output operands per core (All benchmarks, with optimization) 93 4.3 Comparison of Optimised Cores’ States.................. 95 4.3.1 Number of states per core (Smaller benchmarks, with opti- mization)............................... 96 4.3.2 Number of states per core (Larger benchmarks, with optimiza- tion).................................. 98 4.3.3 Number of states per core (All benchmarks, with optimization) 98 4.4 Comparison of Optimised Cores’ IPC................... 100 4.4.1 IPC per core (Smaller benchmarks, with optimization)..... 101 4.4.2 IPC per core (Larger benchmarks, with optimization)...... 101 4.4.3 IPC per core (All benchmarks, with optimization)........ 104 4.5 Comparing the Area of the optimised benchmarks in Composite and Wave-core architecture............................ 105 4.5.1 Comparing the Area of the optimised benchmarks in Compos- ite architecture............................ 105 4.5.2 Comparing the Area of the optimised benchmarks in Wave- core architecture........................... 107 4.5.3 Comparing Composite vs Wave-core architecture total Area for the optimized benchmarks................... 107 4.6 Comparing the Timing of the optimised benchmarks in Composite and Wave-core architecture......................... 110 4.6.1 Comparing the Timing of the optimised benchmarks in Com- posite architecture.......................... 111 4.6.2 Comparing the Timing of the optimised benchmarks in Wave- core architecture........................... 111 4.6.3 Comparing Composite vs Wave-core Timing of the optimised benchmarks.............................. 114 vii 4.7 Comparing the Static Power of the optimised benchmarks in Com- posite and Wave-core architecture..................... 115 4.7.1 Comparing the Leakage of the optimised benchmarks in Com- posite architecture.......................... 115 4.7.2 Comparing the Leakage of the optimised benchmarks in Wave- core architecture........................... 117 4.8 Comparing the Dynamic Power of the optimised benchmarks in Com- posite and Wave-core architectures..................... 119 4.8.1 Comparing the Dynamic power of the optimised benchmarks in Composite architecture...................... 119 Dynamic power per state...................... 119 4.8.2 Comparing the Dynamic power of the optimised benchmarks in Wave-core architecture...................... 121 4.8.3 Composite vs Wave-core Dynamic power of the optimised bench- marks................................. 122 4.9 Comparing the Total Power of the optimised benchmarks in Compos- ite and Wave-core architecture........................ 124 4.9.1 Composite total power for the optimized benchmarks...... 125 Total power applying clock gating in Composite architecture. 127 4.9.2 Wave-core total power for the optimized benchmarks...... 127 4.9.3 Power gating and Clock gating Composite vs Wave-core Total Power................................. 131 4.10 Comparing the Power Density of the optimised benchmarks in Com- posite and Wave-core architectures..................... 132 4.10.1 Composite Power density for the optimized benchmarks.... 132 Power
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