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Displayport Intel® FPGA IP User Guide

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Displayport Intel® FPGA IP User Guide DisplayPort Intel® FPGA IP User Guide Updated for Intel® Quartus® Prime Design Suite: 21.1 IP Version: 19.3.0 Subscribe UG-01131 | 2021.05.11 Send Feedback Latest document on the web: PDF | HTML Contents Contents 1. DisplayPort Intel® FPGA IP Quick Reference...................................................................9 1.1. DisplayPort Terms and Acronyms........................................................................... 10 2. About This IP................................................................................................................ 13 2.1. Release Information............................................................................................. 13 2.2. Device Family Support..........................................................................................14 2.3. IP Core Verification.............................................................................................. 16 2.4. Performance and Resource Utilization..................................................................... 16 3. Getting Started............................................................................................................. 18 3.1. Installing and Licensing Intel FPGA IP Cores............................................................ 18 3.1.1. Intel FPGA IP Evaluation Mode................................................................... 19 3.2. Specifying IP Parameters and Options.....................................................................21 3.3. Simulating the Design.......................................................................................... 21 3.3.1. Simulating with the ModelSim Simulator..................................................... 22 3.4. Compiling the Full Design and Programming the FPGA.............................................. 22 4. DisplayPort Intel FPGA IP Hardware Design Examples................................................. 23 4.1. DisplayPort Intel FPGA IP Hardware Design Examples for Intel Arria 10, Intel Cyclone 10 GX, and Intel Stratix 10 Devices......................................................... 23 4.2. HDCP Over DisplayPort Design Example for Intel Arria 10 and Intel Stratix 10 Devices.. 23 4.3. DisplayPort Intel FPGA IP Hardware Design Examples for Arria V, Cyclone V, and Stratix V Devices...............................................................................................24 4.3.1. Clock Recovery Core.................................................................................28 4.3.2. Transceiver and Clocking...........................................................................33 4.3.3. Required Hardware...................................................................................35 4.3.4. Design Walkthrough................................................................................. 35 4.3.5. DisplayPort Link Training Flow....................................................................41 4.3.6. DisplayPort Post Link Training Adjust Request Flow (LQA).............................. 42 4.3.7. DisplayPort MST Source User Application.....................................................43 5. DisplayPort Source....................................................................................................... 45 5.1. Main Data Path.................................................................................................... 46 5.1.1. Video Packetizer Path............................................................................... 47 5.1.2. Video Geometry Measurement Path............................................................ 47 5.1.3. Audio and Secondary Stream Encoder Path..................................................48 5.1.4. Training and Link Quality Patterns Generator............................................... 48 5.2. Controller Interface..............................................................................................49 5.3. Sideband Channel................................................................................................ 49 5.4. Source Embedded DisplayPort (eDP) Support...........................................................49 5.5. HDCP 1.3 TX Architecture..................................................................................... 49 5.6. HDCP 2.3 TX Architecture..................................................................................... 53 5.7. Source Interfaces................................................................................................ 59 5.7.1. Controller Interface.................................................................................. 66 5.7.2. AUX Interface..........................................................................................67 5.7.3. Video Interface........................................................................................67 5.7.4. TX Transceiver Interface........................................................................... 71 5.7.5. Transceiver Reconfiguration Interface......................................................... 71 5.7.6. Transceiver Analog Reconfiguration Interface............................................... 72 ® DisplayPort Intel FPGA IP User Guide Send Feedback 2 Contents 5.7.7. Secondary Stream Interface...................................................................... 72 5.7.8. Audio Interface........................................................................................76 5.8. Source Clock Tree................................................................................................ 79 6. DisplayPort Sink........................................................................................................... 81 6.1. Sink Embedded DisplayPort (eDP) Support.............................................................. 83 6.2. Sink Non-GPU Mode Support................................................................................. 84 6.3. HDCP 1.3 RX Architecture..................................................................................... 84 6.4. HDCP 2.3 RX Architecture..................................................................................... 90 6.5. Sink Interfaces.................................................................................................... 94 6.5.1. Controller Interface................................................................................ 101 6.5.2. AUX Interface........................................................................................ 102 6.5.3. Debugging Interface............................................................................... 102 6.5.4. Video Interface...................................................................................... 103 6.5.5. Clocked Video Input Interface.................................................................. 106 6.5.6. RX Transceiver Interface......................................................................... 107 6.5.7. Transceiver Reconfiguration Interface........................................................108 6.5.8. Secondary Stream Interface.................................................................... 109 6.5.9. Audio Interface...................................................................................... 111 6.5.10. Non-GPU Mode EDID Interface............................................................... 112 6.5.11. MSA Interface...................................................................................... 112 6.6. Sink Clock Tree.................................................................................................. 114 7. DisplayPort Intel FPGA IP Parameters........................................................................ 116 7.1. DisplayPort Intel FPGA IP Source Parameters......................................................... 116 7.2. DisplayPort Intel FPGA IP Sink Parameters ............................................................118 8. DisplayPort Intel FPGA IP Simulation Example........................................................... 121 8.1. Design Walkthrough........................................................................................... 121 8.1.1. Copy the Simulation Files to Your Working Directory................................... 122 8.1.2. Generate the IP Simulation Files and Scripts, and Compile and Simulate........123 8.1.3. View the Results.................................................................................... 124 9. DisplayPort API Reference.......................................................................................... 127 9.1. Using the Library................................................................................................127 9.2. btc_dprx_syslib API Reference............................................................................. 129 9.3. btc_dprx_aux_get_request..................................................................................129 9.4. btc_dprx_aux_handler........................................................................................ 130 9.5. btc_dprx_aux_post_reply....................................................................................131 9.6. btc_dprx_baseaddr.............................................................................................131 9.7. btc_dprx_dpcd_gpu_access................................................................................. 131 9.8. btc_dprx_edid_set............................................................................................. 132 9.9. btc_dprx_hpd_get..............................................................................................132
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