DOCSLIB.ORG

United States Patent (19) 11 Patent Number: 5,838,987 Sound LO)))

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
United States Patent (19) 11 Patent Number: 5,838,987 Sound LO))) USOO583.8987A United States Patent (19) 11 Patent Number: 5,838,987 Brightman et al. (45) Date of Patent: Nov. 17, 1998 54 PROCESSOR FOR ELIMINATING 4.885,681 12/1989 Umeno et al. ...................... 395/406 A EXTERNAL SOCHRONOUS SUBSYSTEMS 5,155,838 10/1992 Kishi ....................................... 395/500 5,175,853 12/1992 Kardach et al 395/733 75 Inventors: Thomas B. Brightman, Dallas, Tex.; 55021 a-Y-2 gE. E.OldOC et al...al. SS Eric Sitaphy D. 5,423,008 6/1995 Young et al. ........................... 395/287 s 9. s 5,455,909 10/1995 Blomgren et al. .. 395/183.19 5,560,002 9/1996 Kardach et al. ........................ 395/555 73 Assignee: National Semiconductor Corporation, 5,590,312 12/1996 Marisetty ... ... 395/500 Santa Clara, Calif. 5,590,342 12/1996 Marisetty ........ 395/750.06 5,628,017 5/1997 Kimmerly et al. ..................... 395/704 21 Appl. No.: 540,351 5,657.253 12/1997 Dreyer et al. ...................... 364/551.01 22 Filed: Oct. 6, 1995 OTHER PUBLICATIONS (51) Int. Cl." ...................................................... G06F 15/76 CHIPSystem Architecture, Product Briefs, Oct. 1991, “The 52 U.S. Cl. ............ 395/800.32: 395/591 Super State" Architecture," pp. 15–25. 58 Field of Search ..................................... 395/825, 828, Primary Examiner Alpesh M. Shah 395/835, 865, 412, 500, 182.08, 182.13, Attorney, Agent, or Firm John L. Maxin 18401, 733, 734, 739, 740, 742,800.01, 800.05, 800.28,800.4, 800.32, 390,561, 57 ABSTRACT 568, 369,591, 376 A processing System having a virtual Subsystem architecture 56) References Cited employs a reentrant System management mode mechanism and device handlers along with remappable hardware U.S. PATENT DOCUMENTS resources to Simulate physical Subsystems, all transparent to 4,514,805 4/1985 McDonough et al 395/736 application programs executing on the processing System. 4,689.766 8/1987 Kent. 395/182.21 4,812,975 3/1989 Adachi et al. .......................... 395/500 18 Claims, 3 Drawing Sheets irtual Subsystem Programs 56. GenerationSound LO))) Remappable Hardware Resources 14 Instruction Fetch Instruction Decode Address Calculation 1 21 Memory or I/O SMI Address Calculation 2 Address Generator Compare 54 Bus. If O Compare XSMI U.S. Patent Nov. 17, 1998 Sheet 3 of 3 5,838,987 Application Programs Generation Graphics Display FIG. 3 -counter Comparato intC 5,838,987 1 2 PROCESSOR FOR ELMINATING From the foregoing, it can be seen that there is a need for EXTERNAL SOCHRONOUS SUBSYSTEMS a virtual Subsystem architecture that handles memory CROSS-REFERENCES TO RELATED mapped I/O in a virtual environment, handles Virtual Sub APPLICATIONS systems with a heavily pipelined CPU core, and provides 5 remappable virtual hardware resources, for virtualizing iso This patent is related to commonly assigned U.S. patent chronous real-time run peripheral Subsystems. applications Ser. No. 08/458,326, entitled “Virtualized Audio Generation And Capture. In A Computer', filed Jun. 2, SUMMARY OF THE INVENTION 1995, and Ser. No. 08/498,965 entitled “Virtualized Func tions Within A Microprocessor', filed Jul. 6, 1995, the To overcome the limitations of the prior art described disclosures of both herein incorporated by reference. above, and to overcome other limitations that will become apparent upon reading and understanding the present BACKGROUND OF THE INVENTION Specification, the present invention discloses a virtual Sub 1. Field of the Invention System architecture employing a native central processing The invention relates generally to computer Systems, and unit along with a reentrant System management mode more particularly to a virtual Subsystem architecture that 15 mechanism with multiple threads of execution, for trapping Simulates isochronous or “real-time run' peripheral Sub and Servicing events which are intended to provoke a Systems transparently to existing Software programs. response from a physical Subsystem in near real-time. Exter 2. Description of Related Art nal and internal trap mechanisms generate a System Man Computer Systems generally include provisions for agement Interrupt (SMI) responsive to the occurrence of attachment of peripheral Subsystems, typically through the predetermined external and internal events, respectively. use of an add-on card. These Subsystems are identified or Responsive to the SMI, the native central processing unit "mapped' through memory and I/O address Space recog determines the event that caused the interrupt and executes nized by the central processing unit (CPU). In the PC a Series of instructions to Simulate a response expected from the physical Subsystem. environment, de facto protocols have arisen from the Some 25 what arbitrary memory and I/O mapping made popular A feature of the present invention is the ability to virtu through commercially Successful products, Such as, but not alize subsystems with a heavily pipelined CPU core. limited to, Sound cards, modems, and graphics display Another feature of the present invention is the ability to adapters. Application Software exists which implicitly Virtualize memory mapped physical Subsystems. embeds these de facto protocols-making hardware Another feature of the present invention is the ability to upgrades which deviate from backward compatibility unde Virtualize multiple real-time run peripherals through the use sirable. of a reentrant System management mode mechanism. Imposing backward compatibility on peripheral enhance Another feature of the present invention is remappable ments usually limits performance, increases costs, and Virtual hardware resources. requires additional Space, typically in the form of additional 35 integrated circuits or die Space. The alternative to maintain Another feature of the present invention is a high degree ing backward compatibility is highly unattractive or com of integration and amortization of native central processing mercially unacceptable in that a plethora of legacy Software unit bandwidth to run both application software and to must be abandoned. Virtualize physical Subsystems. By way of further background, CPU pipelining tech 40 Another feature of the present invention is direct effi niques are known for mitigating the latency associated with ciency dependency of the virtualized Subsystems on the executing complex instructions. More Specifically, instruc Speed of the native central processing unit. tion execution is broken down into multiple “phases’ So that Another feature of the present invention is that virtualized more than one instruction in a Series of instructions, are Subsystems are independent of the operating System. executed at any one given time, albeit in different phases. 45 Another feature of the present invention is that virtualized A related, but not entirely relevant technique to the Subsystems do not require any special memory management present invention is the SuperState TM mode of operation handlers. described in the Product Briefs for the CHIPSystemTM Another feature of the present invention is the ease of Architecture, dated October 1991, by Chips and upgrading new programming for virtualized Subsystems. Technologies, Inc., of San Jose, Calif. In this So-called 50 “SuperState TM mode”, software and hardware incompatibili Another feature of the present invention is a reduction in ties are reconciled by intercepting or “trapping incompat the manufacturing cost of the computer System. ible Software commands or interrupts at the external bus These and various other objects, features, and advantages level and translating them into a compatible format. This of novelty which characterize the invention are pointed out “SuperState TM mode”, which is directed to “demand ser 55 with particularity in the claims annexed hereto and forming Vice' peripherals, is completely devoid of any teachings or a part hereof. However, for a better understanding of the Suggestions of eliminating isochronous “real-time run” invention, its advantages, and the objects obtained by its use, peripherals having critical timing constraints, Such as, but reference should be made to the drawings which form a not limited to, Sound cards and modems. Moreover, the further part hereof, and to the accompanying descriptive “SuperState TM mode” is completely devoid of any teachings 60 matter, in which there is illustrated and described a specific or Suggestions of handling memory mapped I/O in a virtual example of a virtual Subsystem architecture, practiced in environment, handling virtual Subsystems with a heavily accordance with the principles of the present invention. pipelined CPU core, or using hardware resources, Such as, but not limited to, counters, timers, comparators, and BRIEF DESCRIPTION OF THE DRAWINGS CODECS, to assist the virtual subsystems and which are 65 FIG. 1 is a general block diagram of a System employing remappable among the virtual Subsystems to avoid duplica a virtual Subsystem architecture, practiced in accordance tion. with the principles of the present invention; 5,838,987 3 4 FIG. 2 is a more detailed block diagram of the virtual 1. Exemplary Computer System Employing A Virtualized Subsystem architecture; Display Subsystem FIG. 3 is a State diagram depicting exemplary reentrancy Reference is now made to FIG. 1 which depicts an in the virtual Subsystem architecture of the present inven exemplary, but not exclusive System employing a virtual tion; and, Subsystem architecture, practiced in accordance with the FIG. 4 is a block diagram of exemplary remappable principles of the present invention. A System circuit board
Load more

Recommended publications
  • Analyzing the Benefits of Scratchpad Memories for Scientific Matrix
    The Pennsylvania State University The Graduate School Department of Computer Science and Engineering ANALYZING THE BENEFITS OF SCRATCHPAD MEMORIES FOR SCIENTIFIC MATRIX COMPUTATIONS A Thesis in Computer Science and Engineering by Bryan Alan Cover c 2008 Bryan Alan Cover Submitted in Partial Fulfillment of the Requirements for the Degree of Master of Science May 2008 The thesis of Bryan Alan Cover was reviewed and approved* by the following: Mary Jane Irwin Evan Pugh Professor of Computer Science and Engineering Thesis Co-Advisor Padma Raghavan Professor of Computer Science and Engineering Thesis Co-Advisor Raj Acharya Professor of Computer Science and Engineering Head of the Department of Computer Science and Engineering *Signatures are on file in the Graduate School. iii Abstract Scratchpad memories (SPMs) have been shown to be more energy efficient, have faster access times, and take up less area than traditional hardware-managed caches. This, coupled with the predictability of data presence and reduced thermal properties, makes SPMs an attractive alternative to cache for many scientific applications. In this work, SPM based systems are considered for a variety of different functions. The first study performed is to analyze SPMs for their thermal and area properties on a conven- tional RISC processor. Six performance optimized variants of architecture are explored that evaluate the impact of having an SPM in the on-chip memory hierarchy. Increasing the performance and energy efficiency of both dense and sparse matrix-vector multipli- cation on a chip multi-processor are also looked at. The efficient utilization of the SPM is ensured by profiling the application for the data structures which do not perform well in traditional cache.
    [Show full text]
  • Memory Architectures 13 Preeti Ranjan Panda
    Memory Architectures 13 Preeti Ranjan Panda Abstract In this chapter we discuss the topic of memory organization in embedded systems and Systems-on-Chips (SoCs). We start with the simplest hardware- based systems needing registers for storage and proceed to hardware/software codesigned systems with several standard structures such as Static Random- Access Memory (SRAM) and Dynamic Random-Access Memory (DRAM). In the process, we touch upon concepts such as caches and Scratchpad Memories (SPMs). In general, the emphasis is on concepts that are more generally found in SoCs and less on general-purpose computing systems, although this distinction is not very clearly defined with respect to the memory subsystem. We touch upon implementations of these ideas in modern research and commercial scenarios. In this chapter, we also point out issues arising in the context of the memory architectures that become exported as problems to be addressed by the compiler and system designer. Acronyms ALU Arithmetic-Logic Unit ARM Advanced Risc Machines CGRA Coarse Grained Reconfigurable Architecture CPU Central Processing Unit DMA Direct Memory Access DRAM Dynamic Random-Access Memory GPGPU General-Purpose computing on Graphics Processing Units GPU Graphics Processing Unit HDL Hardware Description Language PCM Phase Change Memory P.R. Panda () Department of Computer Science and Engineering, Indian Institute of Technology Delhi, New Delhi, India e-mail: [email protected] © Springer Science+Business Media Dordrecht 2017 411 S. Ha, J. Teich (eds.), Handbook of Hardware/Software Codesign, DOI 10.1007/978-94-017-7267-9_14 412 P.R. Panda SoC System-on-Chip SPM Scratchpad Memory SRAM Static Random-Access Memory STT-RAM Spin-Transfer Torque Random-Access Memory SWC Software Cache Contents 13.1 Motivating the Significance of Memory....................................
    [Show full text]
  • Gpgpus: Overview Pedagogically Precursor Concepts UNIVERSITY of ILLINOIS at URBANA-CHAMPAIGN
    GPGPUs: Overview Pedagogically precursor concepts UNIVERSITY OF ILLINOIS AT URBANA-CHAMPAIGN © 2018 L. V. Kale at the University of Illinois Urbana-Champaign Precursor Concepts: Pedagogical • Architectural elements that, at least pedagogically, are precursors to understanding GPGPUs • SIMD and vector units. • We have already seen those • Large scale “Hyperthreading” for latency tolerance • Scratchpad memories • High BandWidth memory L.V.Kale 2 Tera MTA, Sun UltraSPARC T1 (Niagara) • Tera computers, With Burton Smith as a co-founder (1987) • Precursor: HEP processor (Denelcor Inc.), 1982 • First machine Was MTA • MTA-1, MTA-2, MTA-3 • Basic idea: • Support a huge number of hardWare threads (128) • Each With its oWn registers • No Cache! • Switch among threads on every cycle, thus tolerating DRAM latency • These threads could be running different processes • Such processors are called “barrel processors” in literature • But they sWitched to the “next thread” alWays.. So your turn is 127 clocks aWay, always • Was especially good for highly irregular accesses L.V.Kale 3 Scratchpad memory • Caches are complex and can cause unpredictable impact on performance • Scratchpad memories are made from SRAM on chip • Separate part of the address space • As fast or faster than caches, because no tag-matching or associative search • Need explicit instructions to bring data into scratchpad from memory • Load/store instructions exist betWeen registers and scratchpad • Example: IBM/Toshiba/Sony cell processor used in PS/3 • 1 PPE, and 8 SPE cores • Each SPE core has 256 KiB scratchpad • DMA is mechanism for moving data betWeen scratchpad and external DRAM L.V.Kale 4 High BandWidth Memory • As you increase compute capacity of processor chips, the bandWidth to DRAM comes under pressure • Many past improvements (e.g.
    [Show full text]
  • Hardware and Software Optimizations for GPU Resource Management
    Hardware and Software Optimizations for GPU Resource Management A Thesis Submitted in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy by Vishwesh Jatala to the DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING INDIAN INSTITUTE OF TECHNOLOGY KANPUR, INDIA December, 2018 ii Scanned by CamScanner Abstract Graphics Processing Units (GPUs) are widely adopted across various domains due to their massive thread level parallelism (TLP). The TLP that is present in the GPUs is limited by the number of resident threads, which in turn depends on the available resources in the GPUs { such as registers and scratchpad memory. Recent GPUs aim to improve the TLP, and consequently the throughput, by increasing the number of resources. Further, the improvements in semiconductor fabrication enable smaller feature sizes. However, for smaller feature sizes, the leakage power is a significant part of the total power consumption. In this thesis, we provide hardware and software solutions that aim towards the two problems of GPU design: improving throughput and reducing leakage energy. In the first work of the thesis, we focus on improving the performance of GPUs by effective resource management. In GPUs, resources (registers and scratchpad memory) are allocated at thread block level granularity, as a result, some of the resources may not be used up completely and hence will be wasted. We propose an approach that shares the resources of SM to utilize the wasted resources by launching more thread blocks in each SM. We show the effectiveness of our approach for two resources: registers and scratchpad memory (shared memory). On evaluating our approach experimentally with 19 kernels from several benchmark suites, we observed that kernels that underutilize register resource show an average improvement of 11% with register sharing.
    [Show full text]
  • Improving Memory Subsystem Performance Using Viva: Virtual Vector Architecture
    Improving Memory Subsystem Performance using ViVA: Virtual Vector Architecture Joseph Gebis12,Leonid Oliker12, John Shalf1, Samuel Williams12,Katherine Yelick12 1 CRD/NERSC, Lawrence Berkeley National Laboratory Berkeley, CA 94720 2 CS Division, University of California at Berkeley, Berkeley, CA 94720 fJGebis, LOliker, JShalf, SWWilliams, [email protected] Abstract. The disparity between microprocessor clock frequencies and memory latency is a primary reason why many demanding applications run well below peak achievable performance. Software controlled scratchpad memories, such as the Cell local store, attempt to ameliorate this discrepancy by enabling precise control over memory movement; however, scratchpad technology confronts the programmer and compiler with an unfamiliar and difficult programming model. In this work, we present the Virtual Vector Architecture (ViVA), which combines the memory semantics of vector computers with a software-controlled scratchpad memory in order to provide a more effective and practical approach to latency hiding. ViVA requires minimal changes to the core design and could thus be eas- ily integrated with conventional processor cores. To validate our approach, we implemented ViVA on the Mambo cycle-accurate full system simulator, which was carefully calibrated to match the performance on our underlying PowerPC Apple G5 architecture. Results show that ViVA is able to deliver significant per- formance benefits over scalar techniques for a variety of memory access pat- terns as well as two important memory-bound compact kernels, corner turn and sparse matrix-vector multiplication — achieving 2x–13x improvement compared the scalar version. Overall, our preliminary ViVA exploration points to a promis- ing approach for improving application performance on leading microprocessors with minimal design and complexity costs, in a power efficient manner.
    [Show full text]
  • A Dynamic Scratchpad Memory Unit for Predictable Real-Time Embedded Systems
    A Dynamic Scratchpad Memory Unit for Predictable Real-Time Embedded Systems by Saud Wasly A thesis presented to the University of Waterloo in fulfillment of the thesis requirement for the degree of Master of Applied Science in Electrical and Computer Engineering Waterloo, Ontario, Canada, 2012 c Saud Wasly 2012 I hereby declare that I am the sole author of this thesis. This is a true copy of the thesis, including any required final revisions, as accepted by my examiners. I understand that my thesis may be made electronically available to the public. ii Abstract Scratch-pad memory is a popular alternative to caches in real-time embedded systems due to its advantages in terms of timing predictability and power consumption. However, dynamic management of scratch-pad content is challenging in multitasking environments. To address this issue, this thesis proposes the design of a novel Real-Time Scratchpad Memory Unit (RSMU). The RSMU can be integrated into existing systems with minimal architectural modifications. Furthermore, scratchpad management is performed at the OS level, requiring no application changes. In conjunction with a two-level scheduling scheme, the RSMU provides strong timing guarantees to critical tasks. Demonstration and evaluation of the system design is provided on an embedded FPGA platform. iii Acknowledgements My great gratitude is to Allah the only god, the Almighty who guided me in every step of this work with his infinite graciousness and bounties. I would like to thank all the kind people around me who made this possible, to only some of whom it is possible to give particular mention here.
    [Show full text]
  • Architectural Exploration of Heterogeneous Memory Systems Marcos Horro, Gabriel Rodr´Iguez, Juan Tourino,˜ Mahmut T
    1 Architectural exploration of heterogeneous memory systems Marcos Horro, Gabriel Rodr´ıguez, Juan Tourino,˜ Mahmut T. Kandemir Abstract—Heterogeneous systems appear as a viable design whether an access presents reuse that is easily exploitable alternative for the dark silicon era. In this paradigm, a processor by a regular cache, or whether the LRU algorithm and cache chip includes several different technological alternatives for im- conflicts make it advisable to manually allocate the variable plementing a certain logical block (e.g., core, on-chip memories) which cannot be used at the same time due to power constraints. to a scratchpad to better take advantage of the available The programmer and compiler are then responsible for select- locality. Taking into account the hardware characteristics of ing which of the alternatives should be used for maximizing the different available memory modules, access and transfer performance and/or energy efficiency for a given application. costs for each possible allocation are calculated, and a final This paper presents an initial approach for the exploration of allocation is decided considering also memory sizes and power different technological alternatives for the implementation of on-chip memories. It hinges on a linear programming-based budgets. model for theoretically comparing the performance offered by the This paper is organized as follows. Section II introduces available alternatives, namely SRAM and STT-RAM scratchpads scratchpad memories. Section III analyzes the gem5 frame- or caches. Experimental results using a cycle-accurate simulation work and discusses the simulation of scratchpad memories tool confirm that this is a viable model for implementation into in the system.
    [Show full text]
  • Designing Scratchpad Memory Architecture with Emerging STT-RAM Memory Technologies
    Designing Scratchpad Memory Architecture with Emerging STT-RAM Memory Technologies Peng Wang,1 Guangyu Sun,1 Tao Wang,1 Yuan Xie,2 Jason Cong1,3,4 1Center for Energy-Efficient Computing and Applications, School of EECS, Peking University, Beijing, 100871, China 2Computer Science and Engineering Department, Pennsylvania State University, PA 16802, USA 3Computer Science Department, University of California, Los Angeles, CA 90095, USA 4UCLA/PKU Joint Research Institute in Science and Engineering {wang_peng, gsun, wangtao}@pku.edu.cn, [email protected], [email protected] Abstract—Scratchpad memories (SPMs) have been widely used major drawback we need to overcome. Unlike SRAM, in in embedded systems to achieve comparable performance with which read and write operations consume the same time and better energy efficiency when compared to caches. Spin-transfer energy, a write operation of STT-RAM needs much longer torque RAM (STT-RAM) is an emerging nonvolatile memory latency and higher energy than a read operation. Moreover, technology that has low-power and high-density advantages over the latency and energy of write operations in conventional SRAM. In this study we explore and evaluate a series of STT-RAM are several times larger than those of SRAM. scratchpad memory architectures consisting of STT-RAM. The Since on-chip memory is nearest to CPU in the memory experimental results reveal that with optimized design, STT- hierarchy, reducing the access latency of on-chip memory is RAM is an effective alternative to SRAM for scratchpad critical to performance. memory in low-power embedded systems. New STT-RAM device cell designs have been developed I.
    [Show full text]
  • 5. Embedded Systems Dilemma of Chip Memory Diversity By
    International Journal of Engineering, Pure and Applied Sciences, Vol. 1, No. 1, 2016 Embedded Systems Dilemma of Chip Memory Diversity by Scratchpad Memory for Cache On-chip Memory Ravi Kumar Sharma Research Scholar, Department of Computer Application, Surya World University, Rajpura , India Email: [email protected] Abstract: -The aim of this paper is the problem of chip memory selection for computationally intensive applications by proposing scratch pad memory as an alternative to cache. Area and energy for different scratch pad and cache size are computed using CACTI tools while performance was evaluated using the trace results. In this paper, an algorithm integrated into a compiler is presented which analyses the application and selects program and data parts which are placed into the scratchpad. Comparisons against a cache solution show remarkable advantages between 12% and 43% in energy consumption for designs of the same memory size. Key Words-Scratchpad Memory, Cache Memory, CACTI, Compiler, Memory. 1. INTRODUCTION The salient feature of portable devices is light Experimental environment requires the use of a weight and low power consumption. Applications in packing algorithm (which is a compiler support) multimedia, video processing, speech to map the elements onto the scratchpad memory. processing[1], DSP applications and wireless Finally, we report the performance and energy communication require efficient memory design consumption for different cache and scratchpad since on chip memory occupies more than 50% of sizes, for the various applications. We include the the total chip area [2]. This will typically reduce main memory energy consumption to study the the energy consumption of the memory unit, complete system energy requirements.
    [Show full text]
  • Application-Specific Memory Management in Embedded Systems Using Software-Controlled Caches
    CSAIL Computer Science and Artificial Intelligence Laboratory Massachusetts Institute of Technology Application-Specific Memory Management in Embedded Systems Using Software-Controlled Caches Derek Chiou, Prabhat Jain, Larry Rudolph, Srinivas Devadas In the proceedings of the 37th Design Automation Conference Architecture, 2000, June Computation Structures Group Memo 448 The Stata Center, 32 Vassar Street, Cambridge, Massachusetts 02139 ApplicationSp ecic Memory Management for Emb edded Systems Using SoftwareControlled Caches Derek Chiou, Prabhat Jain, Larry Rudolph, and Srinivas Devadas Department of EECS Massachusetts Institute of Technology Cambridge, MA 02139 he and scratchpad memory onchip since each addresses ABSTRACT cac We prop ose a way to improve the p erformance of embed a dierent need Caches are transparent to software since ded pro cessors running dataintensive applications byallow they are accessed through the same address space as the ing software to allo cate onchip memory on an application larger backing storage They often improveoverall software sp ecic basis Onchip memory in the form of cache can p erformance but are unpredictable Although the cache re be made to act like scratchpad memory via a novel hard placement hardware is known predicting its p erformance ware mechanism which we call column caching Column dep ends on accurately predicting past and future reference caching enables dynamic cache partitioning in software by patterns Scratchpad memory is addressed via an indep en mapping data regions to a sp ecied
    [Show full text]
  • FPGA Implementation of a Configurable Cache/Scratchpad
    FPGA Implementation of a Configurable Cache/Scratchpad Memory with Virtualized User-Level RDMA Capability George Kalokerinos, Vassilis Papaefstathiou, George Nikiforos, Stamatis Kavadias, Manolis Katevenis, Dionisios Pnevmatikatos and Xiaojun Yang Institute of Computer Science, FORTH, Heraklion, Crete, Greece – member of HiPEAC {george,papaef,nikiforg,kavadias,kateveni,pnevmati,yxj}@ics.forth.gr Abstract—We report on the hardware implementation of a advances in parallel programming and runtime systems [4][5] local memory system for individual processors inside future allow the use of explicit communication with minimal burden chip multiprocessors (CMP). It intends to support both implicit to the programmers, who merely have to identify the input communication, via caches, and explicit communication, via di- rectly accessible local (”scratchpad”) memories and remote DMA and output data sets of their tasks. (RDMA). We provide run-time configurability of the SRAM Our goal is to provide unified hardware support for both im- blocks near each processor, so that part of them operates as 2nd plicit and explicit communication. To achieve low latency, we level (local) cache, while the rest operates as scratchpad. We also integrate our mechanisms close to the processor, in the upper strive to merge the communication subsystems required by the cache levels, unlike traditional RDMA which is implemented cache and scratchpad into one integrated Network Interface (NI) and Cache Controller (CC), in order to economize on circuits. at the level of the I/O bus. We provide configurability of the The processor communicates with the NI in user-level, through local SRAM blocks that are next to each core, so that they virtualized command areas in scratchpad; through a similar operate either as cache or scratchpad, or as a dynamic mix mechanism, the NI also provides efficient support for synchro- of the two.
    [Show full text]
  • Compiler-Directed Scratchpad Memory Management Via Graph Coloring
    Compiler-Directed Scratchpad Memory Management via Graph Coloring Lian Li, Hui Feng and Jingling Xue University of New South Wales Scratchpad memory (SPM), a fast on-chip SRAM managed by software, is widely used in embed- ded systems. This paper introduces a general-purpose compiler approach, called memory coloring, to assign static data aggregates such as arrays and structs in a program to an SPM. The novelty of this approach lies in partitioning the SPM into a pseudo register file (with interchangeable and aliased registers), splitting the live ranges of data aggregates to create potential data transfer statements between SPM and off-chip memory, and finally, adapting an existing graph coloring algorithm for register allocation to assign the data aggregates to the pseudo register file. Our experimental results using a set of 10 C benchmarks from MediaBench and MiBench show that our methodology is capable of managing SPMs efficiently and effectively for large embedded appli- cations. In addition, our SPM allocator can obtain close to optimal solutions when evaluated and compared against an existing heuristics-based SPM allocator and an ILP-based SPM allocator. Categories and Subject Descriptors: D.3.4 [Programming Languages]: Processors—compilers; optimization; B.3.2 [Memory Structures]: Design Styles—Primary memory; C.3 [Special- Purpose And Application-Based Systems]: Real Time and Embedded Systems General Terms: Algorithms, Languages, Experimentation, Performance Additional Key Words and Phrases: Scratchpad memory, software-managed cache, memory allo- cation, graph coloring, memory coloring, live range splitting, register coalescing 1. INTRODUCTION Scratchpad memory (SPM) is a fast on-chip SRAM managed by software (the application and/or compiler).
    [Show full text]