Chap - a SIMD Graphics Processor Adam Levinthal Thomas Porter Computer Graphics Project Lucasfilm Ltd
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Analyzing the Benefits of Scratchpad Memories for Scientific Matrix
The Pennsylvania State University The Graduate School Department of Computer Science and Engineering ANALYZING THE BENEFITS OF SCRATCHPAD MEMORIES FOR SCIENTIFIC MATRIX COMPUTATIONS A Thesis in Computer Science and Engineering by Bryan Alan Cover c 2008 Bryan Alan Cover Submitted in Partial Fulfillment of the Requirements for the Degree of Master of Science May 2008 The thesis of Bryan Alan Cover was reviewed and approved* by the following: Mary Jane Irwin Evan Pugh Professor of Computer Science and Engineering Thesis Co-Advisor Padma Raghavan Professor of Computer Science and Engineering Thesis Co-Advisor Raj Acharya Professor of Computer Science and Engineering Head of the Department of Computer Science and Engineering *Signatures are on file in the Graduate School. iii Abstract Scratchpad memories (SPMs) have been shown to be more energy efficient, have faster access times, and take up less area than traditional hardware-managed caches. This, coupled with the predictability of data presence and reduced thermal properties, makes SPMs an attractive alternative to cache for many scientific applications. In this work, SPM based systems are considered for a variety of different functions. The first study performed is to analyze SPMs for their thermal and area properties on a conven- tional RISC processor. Six performance optimized variants of architecture are explored that evaluate the impact of having an SPM in the on-chip memory hierarchy. Increasing the performance and energy efficiency of both dense and sparse matrix-vector multipli- cation on a chip multi-processor are also looked at. The efficient utilization of the SPM is ensured by profiling the application for the data structures which do not perform well in traditional cache. -
Memory Architectures 13 Preeti Ranjan Panda
Memory Architectures 13 Preeti Ranjan Panda Abstract In this chapter we discuss the topic of memory organization in embedded systems and Systems-on-Chips (SoCs). We start with the simplest hardware- based systems needing registers for storage and proceed to hardware/software codesigned systems with several standard structures such as Static Random- Access Memory (SRAM) and Dynamic Random-Access Memory (DRAM). In the process, we touch upon concepts such as caches and Scratchpad Memories (SPMs). In general, the emphasis is on concepts that are more generally found in SoCs and less on general-purpose computing systems, although this distinction is not very clearly defined with respect to the memory subsystem. We touch upon implementations of these ideas in modern research and commercial scenarios. In this chapter, we also point out issues arising in the context of the memory architectures that become exported as problems to be addressed by the compiler and system designer. Acronyms ALU Arithmetic-Logic Unit ARM Advanced Risc Machines CGRA Coarse Grained Reconfigurable Architecture CPU Central Processing Unit DMA Direct Memory Access DRAM Dynamic Random-Access Memory GPGPU General-Purpose computing on Graphics Processing Units GPU Graphics Processing Unit HDL Hardware Description Language PCM Phase Change Memory P.R. Panda () Department of Computer Science and Engineering, Indian Institute of Technology Delhi, New Delhi, India e-mail: [email protected] © Springer Science+Business Media Dordrecht 2017 411 S. Ha, J. Teich (eds.), Handbook of Hardware/Software Codesign, DOI 10.1007/978-94-017-7267-9_14 412 P.R. Panda SoC System-on-Chip SPM Scratchpad Memory SRAM Static Random-Access Memory STT-RAM Spin-Transfer Torque Random-Access Memory SWC Software Cache Contents 13.1 Motivating the Significance of Memory.................................... -
A 2000 Frames / S Programmable Binary Image Processor Chip for Real Time Machine Vision Applications
A 2000 frames / s programmable binary image processor chip for real time machine vision applications A. Loos, D. Fey Institute of Computer Science, Friedrich-Schiller-University Jena Ernst-Abbe-Platz 2, D-07743 Jena, Germany {loos,fey}@cs.uni-jena.de Abstract the inflexible and fixed instruction set. To meet that we present a so called ASIP (application specific instruction Industrial manufacturing today requires both an efficient set processor) which combines the flexibility of a GPP production process and an appropriate quality standard of (General Purpose Processor) with the speed of an ASIC. each produced unit. The number of industrial vision appli- cations, where real time vision systems are utilized, is con- tinuously rising due to the increasing automation. Assem- Embedded Vision System bly lines, where component parts are manipulated by robot 1. real scene image sensing, AD- CMOS-Imager grippers, require a fast and fault tolerant visual detection conversion and read out of objects. Standard computation hardware like PC-based 2. grey scale image image segmentation platforms with frame grabber boards are often not appro- representation priate for such hard real time vision tasks in embedded sys- 3. raw binary image image enhancement, tems. This is because they meet their limits at frame rates of representation removal of disturbance a few hundreds images per second and show comparatively ASIP FPGA long latency times of a few milliseconds. This is the result 4. improved binary image calculation of of the largely serial working and time consuming process- projections ing chain of these systems. In contrast to that we designed 5. -
United Health Group Capacity Analysis
Advanced Technical Skills (ATS) North America zPCR Capacity Sizing Lab SHARE Sessions 7774 and 7785 August 4, 2010 John Burg Brad Snyder Materials created by John Fitch and Jim Shaw IBM 1 © 2010 IBM Corporation Advanced Technical Skills Trademarks The following are trademarks of the International Business Machines Corporation in the United States and/or other countries. AlphaBlox* GDPS* RACF* Tivoli* APPN* HiperSockets Redbooks* Tivoli Storage Manager CICS* HyperSwap Resource Link TotalStorage* CICS/VSE* IBM* RETAIN* VSE/ESA Cool Blue IBM eServer REXX VTAM* DB2* IBM logo* RMF WebSphere* DFSMS IMS S/390* xSeries* DFSMShsm Language Environment* Scalable Architecture for Financial Reporting z9* DFSMSrmm Lotus* Sysplex Timer* z10 DirMaint Large System Performance Reference™ (LSPR™) Systems Director Active Energy Manager z10 BC DRDA* Multiprise* System/370 z10 EC DS6000 MVS System p* z/Architecture* DS8000 OMEGAMON* System Storage zEnterprise ECKD Parallel Sysplex* System x* z/OS* ESCON* Performance Toolkit for VM System z z/VM* FICON* PowerPC* System z9* z/VSE FlashCopy* PR/SM System z10 zSeries* * Registered trademarks of IBM Corporation Processor Resource/Systems Manager The following are trademarks or registered trademarks of other companies. Adobe, the Adobe logo, PostScript, and the PostScript logo are either registered trademarks or trademarks of Adobe Systems Incorporated in the United States, and/or other countries. Cell Broadband Engine is a trademark of Sony Computer Entertainment, Inc. in the United States, other countries, or both and is used under license therefrom. Java and all Java-based trademarks are trademarks of Sun Microsystems, Inc. in the United States, other countries, or both. Microsoft, Windows, Windows NT, and the Windows logo are trademarks of Microsoft Corporation in the United States, other countries, or both. -
Gpgpus: Overview Pedagogically Precursor Concepts UNIVERSITY of ILLINOIS at URBANA-CHAMPAIGN
GPGPUs: Overview Pedagogically precursor concepts UNIVERSITY OF ILLINOIS AT URBANA-CHAMPAIGN © 2018 L. V. Kale at the University of Illinois Urbana-Champaign Precursor Concepts: Pedagogical • Architectural elements that, at least pedagogically, are precursors to understanding GPGPUs • SIMD and vector units. • We have already seen those • Large scale “Hyperthreading” for latency tolerance • Scratchpad memories • High BandWidth memory L.V.Kale 2 Tera MTA, Sun UltraSPARC T1 (Niagara) • Tera computers, With Burton Smith as a co-founder (1987) • Precursor: HEP processor (Denelcor Inc.), 1982 • First machine Was MTA • MTA-1, MTA-2, MTA-3 • Basic idea: • Support a huge number of hardWare threads (128) • Each With its oWn registers • No Cache! • Switch among threads on every cycle, thus tolerating DRAM latency • These threads could be running different processes • Such processors are called “barrel processors” in literature • But they sWitched to the “next thread” alWays.. So your turn is 127 clocks aWay, always • Was especially good for highly irregular accesses L.V.Kale 3 Scratchpad memory • Caches are complex and can cause unpredictable impact on performance • Scratchpad memories are made from SRAM on chip • Separate part of the address space • As fast or faster than caches, because no tag-matching or associative search • Need explicit instructions to bring data into scratchpad from memory • Load/store instructions exist betWeen registers and scratchpad • Example: IBM/Toshiba/Sony cell processor used in PS/3 • 1 PPE, and 8 SPE cores • Each SPE core has 256 KiB scratchpad • DMA is mechanism for moving data betWeen scratchpad and external DRAM L.V.Kale 4 High BandWidth Memory • As you increase compute capacity of processor chips, the bandWidth to DRAM comes under pressure • Many past improvements (e.g. -
Design and Architectures for Signal and Image Processing
EURASIP Journal on Embedded Systems Design and Architectures for Signal and Image Processing Guest Editors: Markus Rupp, Dragomir Milojevic, and Guy Gogniat Design and Architectures for Signal and Image Processing EURASIP Journal on Embedded Systems Design and Architectures for Signal and Image Processing Guest Editors: Markus Rupp, Dragomir Milojevic, and Guy Gogniat Copyright © 2008 Hindawi Publishing Corporation. All rights reserved. This is a special issue published in volume 2008 of “EURASIP Journal on Embedded Systems.” All articles are open access articles distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. Editor-in-Chief Zoran Salcic, University of Auckland, New Zealand Associate Editors Sandro Bartolini, Italy Thomas Kaiser, Germany S. Ramesh, India Neil Bergmann, Australia Bart Kienhuis, The Netherlands Partha S. Roop, New Zealand Shuvra Bhattacharyya, USA Chong-Min Kyung, Korea Markus Rupp, Austria Ed Brinksma, The Netherlands Miriam Leeser, USA Asim Smailagic, USA Paul Caspi, France John McAllister, UK Leonel Sousa, Portugal Liang-Gee Chen, Taiwan Koji Nakano, Japan Jarmo Henrik Takala, Finland Dietmar Dietrich, Austria Antonio Nunez, Spain Jean-Pierre Talpin, France Stephen A. Edwards, USA Sri Parameswaran, Australia Jurgen¨ Teich, Germany Alain Girault, France Zebo Peng, Sweden Dongsheng Wang, China Rajesh K. Gupta, USA Marco Platzner, Germany Susumu Horiguchi, Japan Marc Pouzet, France Contents -
Hardware and Software Optimizations for GPU Resource Management
Hardware and Software Optimizations for GPU Resource Management A Thesis Submitted in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy by Vishwesh Jatala to the DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING INDIAN INSTITUTE OF TECHNOLOGY KANPUR, INDIA December, 2018 ii Scanned by CamScanner Abstract Graphics Processing Units (GPUs) are widely adopted across various domains due to their massive thread level parallelism (TLP). The TLP that is present in the GPUs is limited by the number of resident threads, which in turn depends on the available resources in the GPUs { such as registers and scratchpad memory. Recent GPUs aim to improve the TLP, and consequently the throughput, by increasing the number of resources. Further, the improvements in semiconductor fabrication enable smaller feature sizes. However, for smaller feature sizes, the leakage power is a significant part of the total power consumption. In this thesis, we provide hardware and software solutions that aim towards the two problems of GPU design: improving throughput and reducing leakage energy. In the first work of the thesis, we focus on improving the performance of GPUs by effective resource management. In GPUs, resources (registers and scratchpad memory) are allocated at thread block level granularity, as a result, some of the resources may not be used up completely and hence will be wasted. We propose an approach that shares the resources of SM to utilize the wasted resources by launching more thread blocks in each SM. We show the effectiveness of our approach for two resources: registers and scratchpad memory (shared memory). On evaluating our approach experimentally with 19 kernels from several benchmark suites, we observed that kernels that underutilize register resource show an average improvement of 11% with register sharing. -
Improving Memory Subsystem Performance Using Viva: Virtual Vector Architecture
Improving Memory Subsystem Performance using ViVA: Virtual Vector Architecture Joseph Gebis12,Leonid Oliker12, John Shalf1, Samuel Williams12,Katherine Yelick12 1 CRD/NERSC, Lawrence Berkeley National Laboratory Berkeley, CA 94720 2 CS Division, University of California at Berkeley, Berkeley, CA 94720 fJGebis, LOliker, JShalf, SWWilliams, [email protected] Abstract. The disparity between microprocessor clock frequencies and memory latency is a primary reason why many demanding applications run well below peak achievable performance. Software controlled scratchpad memories, such as the Cell local store, attempt to ameliorate this discrepancy by enabling precise control over memory movement; however, scratchpad technology confronts the programmer and compiler with an unfamiliar and difficult programming model. In this work, we present the Virtual Vector Architecture (ViVA), which combines the memory semantics of vector computers with a software-controlled scratchpad memory in order to provide a more effective and practical approach to latency hiding. ViVA requires minimal changes to the core design and could thus be eas- ily integrated with conventional processor cores. To validate our approach, we implemented ViVA on the Mambo cycle-accurate full system simulator, which was carefully calibrated to match the performance on our underlying PowerPC Apple G5 architecture. Results show that ViVA is able to deliver significant per- formance benefits over scalar techniques for a variety of memory access pat- terns as well as two important memory-bound compact kernels, corner turn and sparse matrix-vector multiplication — achieving 2x–13x improvement compared the scalar version. Overall, our preliminary ViVA exploration points to a promis- ing approach for improving application performance on leading microprocessors with minimal design and complexity costs, in a power efficient manner. -
A SIMD Microprocessor for Image Processing
A SIMD microprocessor for image processing Author: Zhiqiang Qiu Student ID: 20716003 Email: [email protected] Supervisor: Prof. Dr. Thomas Bräunl Computational Intelligence - Information Processing Systems (CIIPS) School of Electrical, Electronic and Computer Engineering The University of Western Australia 1 November 2013 A SIMD microprocessor for image processing Abstract The aim of this project is to design a Single Instruction Multiple Data (SIMD) microprocessor for image processing. Image processing is an important topic in computer science. There are many interesting applications based on image processing, such as stereo matching, 3D object reconstruction and edge detection. The core of image processing is matrix manipulations on the digital image. A digital image captured by a modern digital camera is made up of millions of pixels. The common challenge for most of image processing applications is the amount of data needs to be processed. It will be very slow if each pixel is processed in a sequential order. In addition, general-purpose microprocessors are highly inefficient for image processing due to their complicated internal circuit and large instruction set. One particular solution is to process all pixels simultaneously. A SIMD microprocessor with a simple instruction set can significantly increase the overall processing speed. This project focuses on the development of a SIMD image processor using software simulation. It takes a three step approach. The first step is to improve and further develop our circuit simulation software, Retro. Retro is a powerful circuit design tool with build-in real time graphical simulation. A number of improvements have been made to Retro to fulfil our design requirements. -
Traffic Management Using Image Processing and Arm Processor
International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056 Volume: 07 Issue: 05 | May 2020 www.irjet.net p-ISSN: 2395-0072 TRAFFIC MANAGEMENT USING IMAGE PROCESSING AND ARM PROCESSOR Bhaskar MS1, Nandana CH1, Navya S1, Pooja P1 1Department of ECE, Sai Vidya Institute of Technology, India-560064. ---------------------------------------------------------------------***--------------------------------------------------------------------- Abstract - In this paper, we aim to establish a smart and 2. With the advancement in computer technology, this system efficient traffic surveillance system which monitors the has an advantage of instantaneity, reliability and security. enormous movement of vehicles that cause traffic congestion. 3. It has easy maintenance. Here, we hope to develop a vision-based vehicle detection module that identifies the presence of vehicles and counts The rest of the paper is organized as follows: them. We achieve it with the help of Mali-C52, which is an ARM Section II: System overview based video processor which captures the real time video of Section III: System design and prototype the area of interest (AOI). This video is processed in various stages and is later interfaced with an ARM microcontroller Section IV: Conclusion which controls the traffic. II: SYSTEM OVERVIEW Key Words: Traffic congestion, Vehicle detection, MALI C52, Area of Interest (AOI) In the very first step, we obtain the real time video which is read and converted into images and then frames. This frame I: INTRODUCTION can be processed in a series of steps which are listed below: The rapid growth in the number of vehicles is a key feature of A. VEHICLE DETECTION BY BACKGROUND good economic development. -
Suchitra Sathyanarayana +1-858-717-2399 [email protected]
Suchitra Sathyanarayana +1-858-717-2399 [email protected] EDUCATION Doctor of Philosophy Nanyang Technological University, Singapore (Thesis submitted) M.Eng. (by research) Computer Eng., Nanyang Technological University, Singapore [2004-2006] B.Eng. (with Honors) Computer Eng., Nanyang Technological University, Singapore [1999-2003] RESEARCH EXPERIENCE Image Processing Architectures: Responsible for innovating high speed image processing cores by exploiting underlying parallelisms and image symmetries - (i) line feature extractor based on Hough Transform, which gives 1000x speedup; (ii) a novel parallel image rotation engine that achieves order of magnitude speedups especially for high-resolution images; (iii) low-cost pattern recognition system that achieves on-the-fly image rotation using line buffers and recognition using a simplified MLP neural network; (iv) a parallel EZW Wavelet encoding architecture that can be deployed for Haar based image compression systems. Hardware efficient techniques for Vision based Advanced Driver Assistance: As part of my PhD thesis, I developed computationally efficient techniques that detects and classifies various kinds of road markings, including lane markings, arrow markings of different types, zigzag markings, pedestrian markings etc. The proposed techniques are scale-invariant, hardware efficient and robust to complexities in road scenes such as shadows, lighting and weather changes. Vision-based Medical Applications: As part of my M.Eng (by research) thesis, I developed real-time techniques to assess the movements of camera during medical endoscopy. This included methods to infer camera rotations and longitudinal movements using image unrolling and corresponding matching of features. I am also currently involved with another PhD project on vision-based patient monitoring system, using multiple cues such as breathing and movements to infer abnormal patient behavior. -
Image Processor May Be Copied by Individuals and Not - for - Profit
DISTRIBUTION RELIGION THE IMAGE PROCESSOR MAY BE COPIED BY INDIVIDUALS AND NOT - FOR - PROFIT INSTITUTIONS WITHOUT CHARGE FOR - PROFIT INSTITUTIONS WILL HAVE TO NEGOTIATE FOR PERMISSION TO COPY I VIEW MY RESPONSIBILITY TO THE EVOLUTION OF NEW CONSCIOUSNESS HIGHER THAN MY RESPONSIBILITY TO MAKE PROFIT ; I THINK CULTURE HAS TO LEARN TO USE HIGH-TEK MACHINES FOR PERSONAL AESTHETIC, .RELIGIOUS, INTUITIVE, COMPREHENSIVE, EXPLORATORY GROWTH THE DEVELOPMENT OF MACHINES LIKE THE IMAGE PROCESSOR IS PART OF THIS EVOLUTION I AM PAID BY THE STATE, AT LEAST IN PART, TO DO AND DISEMINATE THIS INFORMATION ; SO I DOI As I am sure you (who are you) understand a work like developing and expanding the Image Processor requires much money and time . The 'U' does not have much money for evolutionary work and getting of grants are almost as much work as holding down a job . Therefore, I have the feeling that if considerable monies were to be made with a copy of the Image Processor, I would like some of it . So, I am asking (not telling) that if considerable money were made, by an individual with a copy of. the Image Processor, or if a copy of the Image Processor were sold (to an individual or not-for-profit institution), I would like 20% gross profit . I Things like $100 .00 honorariums should be ignored . Of course enforcing such a request is too difficult to be bothered with . But let it be known that I consider it to be morally binding Much Love . Daniel J . Sandin Department of Art University of Illinois at Chicago Circle Box 4348 Chicago, Illinois 60680 Office phone : 312-996-8689 Lab phone: 312-996-2312 Messages : 312-996-3337 (Department of Art) NOTES ON THE AESTHETICS OF 'copying-an-Ima ge Processor' : Being a 'copier' of many things, in this case the first copier of an Image Processor, .1 trust the following notes to find meaning to .