CSAIL Computer Science and Artificial Intelligence Laboratory
Massachusetts Institute of Technology
Application-Specific Memory Management in Embedded Systems Using Software-Controlled Caches
Derek Chiou, Prabhat Jain, Larry Rudolph, Srinivas Devadas
In the proceedings of the 37th Design Automation Conference Architecture, 2000, June
Computation Structures Group Memo 448
The Stata Center, 32 Vassar Street, Cambridge, Massachusetts 02139
Application Sp eci c Memory Management for Emb edded Systems
Using Software Controlled Caches
Derek Chiou, Prabhat Jain, Larry Rudolph, and Srinivas Devadas Department of EECS Massachusetts Institute of Technology
Cambridge, MA 02139
he and scratchpad memory on chip since each addresses
ABSTRACT cac
We prop ose a way to improve the p erformance of embed
a di erent need Caches are transparent to software since
ded pro cessors running data intensive applications byallow
they are accessed through the same address space as the
ing software to allo cate on chip memory on an application
larger backing storage They often improveoverall software
sp eci c basis On chip memory in the form of cache can
p erformance but are unpredictable Although the cache re
be made to act like scratchpad memory via a novel hard
placement hardware is known predicting its p erformance
ware mechanism which we call column caching Column
dep ends on accurately predicting past and future reference
caching enables dynamic cache partitioning in software by
patterns Scratchpad memory is addressed via an indep en
mapping data regions to a sp eci ed sets of cache columns
dent address space and thus must be managed explicitly
or ways When a region of memory is exclusively mapp ed
by software oftentimes a complex and cumb ersome prob
to an equivalent sized partition of cache column caching
lem but provides absolutely predictable p erformance Thus
provides the same functionality and predictability as a ded
icated scratchpad memory for time critical parts of a real
even though a pure cache system may p erform b etter over
time application The ratio between scratchpad size and
all scratchpad memories are necessary to guarantee that
cache size can b e easily and quickly varied for each applica
critical p erformance metrics are always met
tion or each task within an application Thus software has
much ner software control of on chip memory providing
Of course b oth caches and scratchpad memories should b e
the ability to dynamically tradeo p erformance for on chip
available to emb edded systems so that the appropriate mem
memory
ory structure can b e used in each instance A static divi
sion however is guaranteed to b e sub optimal as di erent
ve di erent requirements Previous research
1. INTRODUCTION applications ha
As time to market requirements of electronic systems de
has shown that even within a single application dynami
mand ever faster design cycles an ever increasing number
cally varying the partitioning b etween cache and scratchpad
of systems are built around a programmable emb edded pro
memory can signi cantly improve p erformance
cessor that implements an ever increasing amountoffunc
tionality in rmware running on the emb edded pro cessor
We prop ose a way to dynamically allo cate cache and scratch
The advantages of doing so are twofold software is simpler
pad memories from a common p o ol of memory In partic
to implement than a dedicated hardware solution and soft
ular we prop ose column caching a simple mo di cation
ware can b e easily changed to address design errors late de
that enables software to dynamically partition a cache into
sign changes and pro duct evolution Only the most
several distinct caches and scratchpad memories at a column
time critical tasks need to b e implemented in hardware
granularity In our reference implementation each way of
an n way set asso ciativecache is a column By exclusively
On chip memory in the form of cache scratchpad SRAM
allo cating a region of address space to an equal sized region