The Architecture of a Reusable Built-In Self-Test for Link Training, IO and Memory

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The Architecture of a Reusable Built-In Self-Test for Link Training, IO and Memory AN ABSTRACT OF THE DISSERTATION OF Bruce Querbach for the degree of Doctor of Philosophy in Electrical and Computer Engineering presented on June 12, 2015. Title: The Architecture of a Reusable Built-In Self-Test for Link Training, IO and Memory Defect Detection and Auto Repair on 14nm Intel SOC. Abstract approved: ______________________________________________________ Patrick Y. Chiang The complexity of designing and testing today’s system on chip (SOC) is increasing due to greater integrated circuit (IC) density and higher IO and memory frequencies. SOCs for the mobile phone and tablet market have the unique challenge of short product development windows, at times less than six months, and low cost board and platform that limits physical access to test access ports (TAP). This dissertation presents the architecture of a reusable built-in self-test (BIST) engine called converged pattern generator and checker (CPGC) that was developed to address the above challenges. It is used in the critical path of millions of x86 SOC for DDR3, DDR4, LP-DDR3, LP-DDR4 IO initialization and link training. The CPGC is also an essential BIST engine for IO and memory defect detection, and in some cases, the automatic repair of detected memory defects. The software and hardware infrastructure that leverages CPU L2/L3 cache to enable cache based testing (CBT) and the parallel execution of the CPGC Intel BIST engine is shown to improve test time 60x to 170x over conventional TAP based testing. In addition, silicon results are presented showing that CPGC enables easy debug of inter symbol interference (ISI) and crosstalk issues in silicon and boards, enables fast IO link training, improves validation time by 3x, and in some instances, reduces SOC and platform power by 5% to 11% through closed loop IO circuit power optimization. This CPGC BIST engine has been developed into a reusable IP solution, which has been successfully designed into at least 11 Intel CPUs and SOCs (32nm-14nm), with seven of these successfully debugged, tested, and launched into the market place. Ultimately has led to over 100 million CPUs being shipped within one quarter using this architecture. ©Copyright by Bruce Querbach June 12th, 2015 All Rights Reserved The Architecture of a Reusable Built-In Self-Test for Link Training, IO and Memory Defect Detection and Auto Repair on 14nm Intel SOC by Bruce Querbach A DISSERTATION submitted to Oregon State University in partial fulfillment of the requirements for the degree of Doctor of Philosophy Presented June 12, 2015 Commencement June 2015 Doctor of Philosophy dissertation of Bruce Querbach presented on June 12, 2015 APPROVED: Major Professor, representing Electrical and Computer Engineering Director of the school of Electrical Engineering and Computer Science Dean of the Graduate School I understand that my dissertation will become part of the permanent collection of Oregon State University libraries. My signature below authorizes release of my dissertation to any reader upon request. Bruce Querbach, Author ACKNOWLEDGEMENTS The author expresses sincere appreciation to: 1. Patrick Chiang for his patience and advice throughout the years 2. Sudeep Puligundla for his insights and advice throughout this process 3. Rahul Khanna for his collaboration, showing me the ropes, and for his patience over many paper revisions 4. Sabyasachi Deyati for his inspiration, advice, and paper contribution 5. David Blankenbeckler for paper collaboration and sharing his experience 6. Peter Yanyang Tan for collecting RMT and JTAG data and for paper contribution 7. Roger R Rees for his guidance, advice over the years, and paper reviews 8. Anne Meixner for her advice and paper edit and review 9. Ron Anderson for sharing his insights on DDR debug, data collection, and paper contribution 10. Adam Taylor for sharing his expertise, post silicon data validation collection, and paper contribution 11. Daniel Becerra for collecting valuable data on DDR interface and for paper contribution 12. Zale T Schoenborn for his visionary ideas and support over the years, and paper contribution 13. David G Ellis for his guidance over the years, for teaching, for sharing his expertise in digital design, and for paper contribution 14. Yulan Zhang for her efforts and contribution in simulation and modeling CPGC, and paper contribution 15. Thilak K Poriyani House Raju, and Rucha P Purandare for their simulation, design, validation, and data collection 16. Van Lovelace for sharing his knowledge on BIOS and MRC and paper contribution 17. Joe Crop for his advice, paper edits, and paper contribution 18. Amy Querbach for her patience and support throughout time 19. Ram Mallela, Buz Hampton (GM), John D Barton (VP), and Rani Borkar (Sr. VP) for management support and funding Contribution of authors From Intel Corporation: Sudeep Puligundla, Rahul Khanna, David Blankenbeckler, Peter Yanyang Tan, Ron Anderson, Adam Taylor, Daniel Becerra, Zale T Schoenborn, David G Ellis, Yulan Zhang, and Van Lovelace. From Georgia Institute of Technology: Sabyasachi Deyati From Oregon State University: Joe Crop and Patrick Chiang. TABLE OF CONTENTS Page 1 Dissertation Overview ................................................................................................ 1 2 Introduction and Literature Review ............................................................................ 4 2.1 Challenges of IO Bandwidth, Frequency, and Low Power .................................. 4 2.2 Process Variation.................................................................................................. 7 2.3 Temperature Variation ......................................................................................... 8 2.4 Aging Effects........................................................................................................ 9 2.5 Calibration Methods and BIST .......................................................................... 11 2.6 High Speed Differential IO (HSIO) ................................................................... 15 2.7 Memory Single Ended IO .................................................................................. 17 2.8 Memory Cell Fault Models ................................................................................ 20 2.9 Memory Test Algorithms ................................................................................... 25 2.10 Research Goals and methodology .................................................................. 27 2.10.1 Goal ............................................................................................................. 27 2.10.2 Methodology ............................................................................................... 28 2.11 References ...................................................................................................... 30 3 Comparison of hardware and software stress method .............................................. 35 3.1 Introduction ........................................................................................................ 36 3.2 The APGC Architecture ..................................................................................... 38 3.3 The Aggressor/Victim Pattern Rotation ............................................................. 40 3.4 The Software Learning Algorithm and Pattern .................................................. 41 TABLE OF CONTENTS Page 3.5 Margin Result ..................................................................................................... 41 3.6 Receiver Voltage Margin – Low Side ................................................................ 42 3.7 Receiver Voltage Margin – High Side ............................................................... 42 3.8 Receiver Timing Margin – Low Side ................................................................. 43 3.9 Transmitter Voltage Margin – Low Side ........................................................... 43 3.10 Transmitter Voltage Margin – High Side ....................................................... 44 3.11 Transmitter Timing Margin – Low Side......................................................... 44 3.12 Comparison of Test Execution Time of APGC and Software ........................ 45 3.13 Conclusion ...................................................................................................... 46 3.14 Acknowledgements ........................................................................................ 47 3.15 References ...................................................................................................... 48 4 Improved Debug, Validation and Test Time ............................................................ 51 4.1 Introduction ........................................................................................................ 52 4.2 Failure Modes ..................................................................................................... 55 4.3 CPGC Architecture ............................................................................................ 58 4.3.1 Architecture for Software Assisted Repair Technology ............................. 59 4.3.2 Unified Pattern Sequencer .......................................................................... 61 4.3.3 LMN ............................................................................................................ 62 4.3.4 Fixed Pattern Buffer .................................................................................... 62 TABLE OF CONTENTS
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