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ITRS Past, Present and Future Paolopaolo Garginigargini Chairmanchairman ITRSITRS Fellowfellow IEEE,IEEE, Fellowfellow II--JSAPJSAP

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ITRS Past, Present and Future Paolopaolo Garginigargini Chairmanchairman ITRSITRS Fellowfellow IEEE,IEEE, Fellowfellow II--JSAPJSAP ITRS Past, Present and Future PaoloPaolo GarginiGargini ChairmanChairman ITRSITRS FellowFellow IEEE,IEEE, FellowFellow II--JSAPJSAP May, 2015 ConFab P.Gargini 1 AgendaAgenda InIn thethe beginningbeginning GeometricalGeometrical ScalingScaling ITRSITRS 1.01.0 EquivalentEquivalent ScalingScaling PostPost CMOSCMOS ITRSITRS 2.02.0 3D3D PowerPower ScalingScaling HeterogeneousHeterogeneous IntegrationIntegration May, 2015 ConFab P.Gargini 2 TheThe FirstFirst PlanarPlanar IntegratedIntegrated CircuitCircuit ~1961~1961 May, 2015 ConFab P.Gargini 3 Integrated Circuits Economics Gordon Moore at Fairchild Semiconductors May, 2015 ConFab P.Gargini 4 MooreMoore’’ss LawLaw -- 19651965 2X/Year ~65,000 May, 2015 ConFab P.Gargini 5 Question April 19, 1965 With unit cost falling as the number of components per circuit rises, by 1975 economics may dictate squeezing as many as 65,000 components on a single silicon chip What could you do with 65,000 components? Gordon Moore May, 2015 ConFab P.Gargini 6 May, 2015 ConFab P.Gargini 7 ENIAC (Electronic Numerical Integrator and Computer) ENIAC weighted 30 tons and occupied 1500 squared feet of space. May, 2015 ConFab P.Gargini 8 The Semiconductor Business in the 70s System Designer Product Proprietary Definition Product Definition Open Semiconductor Market Company Custom Standard Components Components System Integration May, 2015 ConFab P.Gargini 9 The SX-70 The story of the struggle between Fairchild Instruments and Texas Instruments for the contract to supply the integrated circuitry for Polaroid's SX-70 camera, introduced in 1972, is related. Research and development work by both companies is described. The problems caused by Polaroid's secrecy regarding the overall camera design are highlighted IEEE Spectrum archive Volume 26 Issue 5, May 1989 May, 2015 ConFab P.Gargini 10 Phase 1 First Age of Scaling (Self-aligned Silicon Gate) May, 2015 ConFab P.Gargini 11 Basic MOS Device (1968-2003) Gate Source Drain Substrate May, 2015 ConFab P.Gargini 12 MOSMOS TransistorTransistor ScalingScaling (1972) Scaled Constant Parameter Voltage Voltage S < 1 Supply Voltage (Vdd) S 1 Channel Length (Lg, Le) S S Channel Width (W) S S Gate Oxide Thickness (Tox) S S Substrate Doping (N) 1/s 1/s Drive Current (Id) S 1/s * Gate Capacitance (Cg) S S Gate Delay S S 2 Active Power S 3 S * Does Not Include Carrier Velocity Saturation R. H. Dennard et Others, “Design of Micron MOS Switching Devices”, IEDM, 1972 May, 2015 ConFab P.Gargini 13 MOSMOS TransistorTransistor ScalingScaling (1970s)(1970s) S=0.7 [0.5x per 2 nodes] Pitch Gate May, 2015 ConFab P.Gargini 14 MooreMoore’’ss LawLaw andand DennardDennard’’ss ScalingScaling LawsLaws ConvergenceConvergence 50% AREA READUCION GENERATION TO GENERATION => 30% LINEAR FEATURE REDUCTION 0.5 = 0.7 50% May, 2015 ConFab P.Gargini 15 May, 2015 ConFab P.Gargini 16 Memory Cell Evolution May, 2015 ConFab P.Gargini 17 Second Update of Moore’s Law 20 19 2X/2Year 18 17 1975 16 15 14 13 12 11 10 9 8 of the number 7 2 1965 6 2X/Year 5 Log 4 3 2 1 components per integrated function integrated per components 0 1976 1977 1978 1979 1966 1968 1970 1971 1972 1973 1967 1969 1974 1975 1980 1959 1960 1961 1962 1963 1964 1965 Year International Electron Device Meeting, December 1975 May, 2015 ConFab P.Gargini 18 ICIC IndustryIndustry atat aa GlanceGlance (1975)(1975) Driver Cost/transistor -> 50% Reduction How 2x Density/2 years (Moore) Method Geometrical Scaling (Dennard) May, 2015 ConFab P.Gargini Let’s Have a Start up! 1948 1955 1957 1965 1968 1973 May, 2015 ConFab P.Gargini 20 The Computer Hobbyists May, 2015 ConFab P.Gargini 21 IBM Total Solution May, 2015 ConFab P.Gargini 22 Operating system IBM BASIC / PC DOS 1.0 CP/M-86 UCSD p-System CPU Intel 8088 @ 4.77 MHz Memory 16 kB ~ 256 kB Sound 1-channel PWM August 12, 1981 May, 2015 ConFab P.Gargini 23 First Moore’s Law Acceleration May, 2015 ConFab P.Gargini 24 May, 2015 ConFab P.Gargini 2525 May, 2015 Log2 components per integrated function 16 18 20 22 24 26 28 30 32 34 10 12 14 0 2 4 6 8 256K 64M 16K 16G 4M 1K 1G 1959 64 1960 1961 1962 Over 40yearsofMoore 1963 Over 40yearsofMoore 1964 FLASH 2 FLASH 1 EPROM MPU DRAM 1965 1966 1967 1968 1970 1969 1970 1971 1972 1973 1974 1975 1976 ConFab 1977 1978 1980 1979 1980 1981 1982 1983 1984 1985 1986 1987 1990 1988 2X/1Y ’ 1989 ’ s Law 1990 s Law 1991 1992 1993 1994 1995 2X/2Y 1996 4X/3Y 1997 2000 P.Gargini 1998 1999 2000 2001 2002 2003 2004 26 26 2005 Wintel Windows May, 2015 ConFab P.Gargini 27 The Semiconductor Business in the 80-90s Wintel Product Proprietary Definition Product Software Design OS and Apps Semiconductor Open Company Market Standard Standard Components Components System Integration May, 2015 ConFab P.Gargini 28 1994 NTRS 1998 2001 2004 2007 2010 1995 0.25 µm 0.18 µm 0.13 µm 0.10 µm 0.07 µm 0.35 µm Isolation LOCOS/ STI †/SOI STI †/SOI Gate thermal thermal/rapid thermal oxidation oxide Gate n; n/p poly; poly/ silicide electrode Source/dr LDD*/MD same + raised S/D ain D ‡; S/D ext Interconn planar ect Wires Al based Al, Cu ( thick) Interlevel oxide oxide; air; polyimide; low dielectric dielectric Via studs W W/Al/Cu May, 2015 ConFab P.Gargini 29 May, 2015 ConFab P.Gargini GateGate DielectricDielectric ScalingScaling You Are Here! 4 3 1999 2 2001 Gate 1.2nm SiO Tox equivalent (nm) 2 1 2003 Silicon substrate 2005 0 4 8 12 Monolayers From My Files 1997 NTRS May, 2015 ConFab P.Gargini 31 1998 ITRS Update •Participation extended to: EECA, EIAJ, KSIA, TSIA at WSC on April 23,1998 •1st Meeting held on July 10/11,1998in San Francisco •2nd meeting held on December 10/11,1998at SFO •50% of tables in 1997 NTRS required some changes •1998 ITRS Update posted on web in April 1999 Tutorial for SEMI P.Gargini May, 2015 ConFab P.Gargini 32 CMOSCMOS FutureFuture DirectionsDirections 1970-2004 Traditional Scaling 70%/2-3year Features 2005-2014 More Moore Equivalent Scaling 70% / 2-3year 2000-2014 SOC, SIP,3D Integrated Solutions 2X Performance/2-3year 2010-20XX From My Files New Devices ??/2-3yearNanotech ITRS 7/11/1998 May, 2015 ConFab P.Gargini 33 ITRS 7/11/1998 May, 2015 ConFab P.Gargini 34 Phase 2 Second Age of Scaling (Equivalent Scaling) May, 2015 ConFab P.Gargini 35 ITRS 1.0 May, 2015 ConFab P.Gargini TheThe IdealIdeal MOSMOS TransistorTransistor Metal Gate Insulator Source Drain Fully Surrounding Fully Enclosed, Metal Electrode Depleted Semiconductor High-K Low Resistance Gate Insulator Source/Drain Band Engineered Semiconductor From My Files May, 2015 ConFab P.Gargini 37 EquivalentEquivalent ScalingScaling StrainedStrained SiliconSilicon HighHigh--K/MetalK/Metal GateGate MultiMulti--gategate HigherHigher PerformancePerformance May, 2015 ConFab P.Gargini 38 ICIC IndustryIndustry atat aa GlanceGlance From Geometrical to Equivalent Scaling (1998(1998-->2003)>2003) Driver Cost/transistor-> 50% Reduction How 2x Density/2 years (Moore) Method Equivalent Scaling (ITRS1.0) May, 2015 ConFab P.Gargini 39 May, 2015 ConFab P.Gargini 40 High-k/Metal-Gate (year 2000) May, 2015 ConFab P.Gargini 41 MobilityMobility InnovationInnovation Strained Strained N-Channel P-Channel 2003 Transistor Transistor High Stress Film SiGe SiGe May, 2015 ConFab Source: Intel P.Gargini 42 Improved Transistor Performance 1000 1.0 V PMOS NMOS 100 IOFF (nA/um) 90 nm 65 nm 10 2002 2004 2004 1 0.2 0.4 0.6 0.8 1.0 1.2 ION (mA/um) 65 nm transistors increase drive current 10-15% with enhanced strain IntelIntel May, 2015 ConFab P.Gargini GateGate OxideOxide LeakageLeakage 10 1000 100 SiO2 Physical 10 Gate Tox Leakage (nm) 1 (relative.) 0.1 1 0.01 .50um .35um .25um .18um .13um 90nm 65nm 45nm 32nm Technology Generation Gate oxide scaling stopped due to leakage 2008 ISS US 44 May, 2015 ConFab P.Gargini May, 2015 ConFab2007 P.Gargini 4545 GateGate OxideOxide LeakageLeakage 10 1000 100 SiO2 Physical 10 Gate Hi-k Tox Leakage (nm) 1 (relative.) Hi-k 0.1 1 0.01 .50um .35um .25um .18um .13um 90nm 65nm 45nm 32nm Technology Generation High-k dielectric breaks through this barrier 2008 ISS US 46 May, 2015 ConFab P.Gargini HighHigh--k+Metalk+Metal GateGate PerformancePerformance // PowerPower BenefitsBenefits Transistor Performance vs. S/D Leakage 1000 65 nm 45 nm Leakage Current 100 >20% (nA/um) Higher Drive >5x Lower Leakage 10 0.5 1.0 1.5 Transistor Drive Current (rel.) Source: Intel Internal 25% Idsat gain demonstrated for 45nm CMOS vs. 65nm CMOS at fixed Ioff Transistor Scailing / Tahir Ghani May, 2015 ConFab P.Gargini SurroundingSurrounding thethe SemiconductorSemiconductor Metal Gate Insulator Source Drain Drain Source Drain Gate Gate Source Source Drain BOX Si fin - Body! FinFET Tri-Gate May, 2015 ConFab P.Gargini 48 22 nm Tri-Gate Transistor Gates Fins Mark Bohr, Kaizad Mistry, May 2011 May, 2015 ConFab P.Gargini 49 IncubationIncubation TimeTime StrainedStrained SiliconSilicon Metal Gate Insulator •• 19921992-->>20032003 Source Drain HKMGHKMG •• 19961996-->2007>2007 1998 RaisedRaised S/DS/D •• 19931993-->2009>2009 MultiGatesMultiGates •• 19971997-->2011>2011 ~ 12-15 years May, 2015 ConFab P.Gargini 50 NRINRI FundedFunded UniversitiesUniversities FindingFinding thethe NextNext SwitchSwitch Notre Dame Purdue Illinois-UC Penn State Michigan UT-Dallas SUNY-Albany GIT Harvard Cornell GIT Purdue RPI Columbia Caltech MIT NCSU Yale UVA TUNNEL GRAPHENE FET SPIN LOGIC Columbia Harvard SPIN Purdue UVA Yale UC Santa Barbara UC Los Angeles GRAPHENE Stanford C Berkeley Notre Dame UC Irvine U. Nebraska/Lincoln UC Sana Barbara U. Maryland Stanford Cornell Illinois UC U Denver Caltech Portland State UT-Austin Rice Texas A&M UC Berkeley U Iowa UT-Dallas ASU Notre Dame MIT U.
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