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July, 2015 P.Gargini ITRS/RC July, 2015 ITRS/RC P.Gargini ITRS Past, Present and Future PaoloPaolo GarginiGargini ChairmanChairman ITRSITRS FellowFellow IEEE,IEEE, FellowFellow II--JSAPJSAP July, 2015 ITRS/RC P.Gargini 2 AgendaAgenda InIn thethe beginningbeginning GeometricalGeometrical ScalingScaling ITRSITRS 1.01.0 EquivalentEquivalent ScalingScaling PostPost CMOSCMOS ITRSITRS 2.02.0 3D3D PowerPower ScalingScaling HeterogeneousHeterogeneous IntegrationIntegration July, 2015 ITRS/RC P.Gargini 3 MooreMoore’’ss LawLaw -- 19651965 2X/Year ~65,000 July, 2015 ITRS/RC P.Gargini 4 The Semiconductor Business in the 70s System Designer Product Proprietary Definition Product Definition Open Semiconductor Market Company Custom Standard Components Components System Integration July, 2015 ITRS/RC P.Gargini 5 The SX-70 The story of the struggle between Fairchild Instruments and Texas Instruments for the contract to supply the integrated circuitry for Polaroid's SX-70 camera, introduced in 1972, is related. Research and development work by both companies is described. The problems caused by Polaroid's secrecy regarding the overall camera design are highlighted IEEE Spectrum archive Volume 26 Issue 5, May 1989 July, 2015 ITRS/RC P.Gargini 6 Phase 1 First Age of Scaling (Self-aligned Silicon Gate) July, 2015 ITRS/RC P.Gargini 7 MOSMOS TransistorTransistor ScalingScaling (1972) Scaled Constant Parameter Voltage Voltage S < 1 Supply Voltage (Vdd) S 1 Channel Length (Lg, Le) S S Channel Width (W) S S Gate Oxide Thickness (Tox) S S Substrate Doping (N) 1/s 1/s Drive Current (Id) S 1/s * Gate Capacitance (Cg) S S Gate Delay S S 2 Active Power S 3 S * Does Not Include Carrier Velocity Saturation R. H. Dennard et Others, “Design of Micron MOS Switching Devices”, IEDM, 1972 July, 2015 ITRS/RC P.Gargini 8 MOSMOS TransistorTransistor ScalingScaling (1970s)(1970s) S=0.7 [0.5x per 2 nodes] Pitch Gate July, 2015 ITRS/RC P.Gargini 9 Memory Cell Evolution July, 2015 ITRS/RC P.Gargini 10 Second Update of Moore’s Law 20 19 2X/2Year 18 17 1975 16 15 14 13 12 11 10 9 8 of the number of 7 2 1965 6 2X/Year 5 Log 4 3 2 1 components per integrated function 0 1976 1977 1978 1979 1966 1968 1970 1971 1972 1973 1967 1969 1974 1975 1980 1959 1960 1961 1962 1963 1964 1965 Year International Electron Device Meeting, December 1975 July, 2015 ITRS/RC P.Gargini 11 ICIC IndustryIndustry atat aa GlanceGlance (1975)(1975) Driver Cost/transistor -> 50% Reduction How 2x Density/2 years (Moore) Method Geometrical Scaling (Dennard) July, 2015 ITRS/RC P.Gargini The Computer Hobbyists July, 2015 ITRS/RC P.Gargini 13 Operating system IBM BASIC / PC DOS 1.0 CP/M-86 UCSD p-System CPU Intel 8088 @ 4.77 MHz Memory 16 kB ~ 256 kB Sound 1-channel PWM August 12, 1981 July, 2015 ITRS/RC P.Gargini 14 First Moore’s Law Acceleration July, 2015 ITRS/RC P.Gargini 15 Wintel Windows July, 2015 ITRS/RC P.Gargini 16 July, 2015 Log2 components per integrated function 10 12 14 16 18 20 22 24 26 28 30 32 34 0 2 4 6 8 256K 64M 16G 16K 4M 1G 1K 1959 64 1960 1961 1962 Over 40yearsof Moore 1963 Over 40yearsof Moore 1964 FLASH 2 FLASH 1 EPROM MPU DRAM 1965 1966 1967 1968 1970 1969 1970 1971 1972 1973 1974 1975 1976 ITRS/RC 1977 1978 1980 1979 1980 1981 1982 1983 1984 1985 1986 1987 1990 1988 2X/1Y ’ 1989 ’ s Law 1990 s Law 1991 1992 1993 1994 1995 2X/2Y 1996 4X/3Y 1997 2000 P.Gargini 1998 1999 2000 2001 2002 2003 2004 17 17 2005 The Semiconductor Business in the 80-90s Wintel Product Proprietary Definition Product Software Design OS and Apps Semiconductor Open Company Market Standard Standard Components Components System Integration July, 2015 ITRS/RC P.Gargini 18 GateGate DielectricDielectric ScalingScaling You Are Here! 4 3 1999 2 2001 Gate 1.2nm SiO Tox equivalent (nm) 2 1 2003 Silicon substrate 2005 0 4 8 12 Monolayers From My Files 1997 NTRS July, 2015 ITRS/RC P.Gargini 19 Semiconductor Industry Globalization $B July, 2015 ITRS/RC P.Gargini 1998 ITRS Update • Participation extended to: EECA, EIAJ, KSIA, TSIA at WSC on April 23,1998 • 1st Meeting held on July 10/11,1998 in San Francisco • 2nd meeting held on December 10/11,1998 at SFO • 50% of tables in 1997 NTRS required some changes • 1998 ITRS Update posted on web in April 1999 Tutorial for SEMI P.Gargini July, 2015 ITRS/RC P.Gargini 21 Phase 2 Second Age of Scaling (Equivalent Scaling) July, 2015 ITRS/RC P.Gargini 22 ITRS 1.0 July, 2015 ITRS/RC P.Gargini TheThe IdealIdeal MOSMOS TransistorTransistor Metal Gate Insulator Source Drain Fully Surrounding Fully Enclosed, Metal Electrode Depleted Semiconductor High-K Low Resistance Gate Insulator Source/Drain Band Engineered Semiconductor From My Files July, 2015 ITRS/RC P.Gargini 24 EquivalentEquivalent ScalingScaling StrainedStrained SiliconSilicon HighHigh--K/MetalK/Metal GateGate MultiMulti--gategate HigherHigher PerformancePerformance July, 2015 ITRS/RC P.Gargini 25 ICIC IndustryIndustry atat aa GlanceGlance (1998(1998-->2003)>2003) Driver Cost/transistor-> 50% Reduction How 2x Density/2 years (Moore) Method Equivalent Scaling ( ITRS1) July, 2015 ITRS/RC P.Gargini 26 July, 2015 ITRS/RC P.Gargini 27 High-k/Metal-Gate (year 2000) July, 2015 ITRS/RC P.Gargini 28 MobilityMobility InnovationInnovation Strained Strained N-Channel P-Channel 2003 Transistor Transistor High Stress Film SiGe SiGe July, 2015 ITRS/RC Source: Intel P.Gargini 29 July, 2015 ITRS/RC2007 P.Gargini 3030 2010 ITRS Summary MPU/high-performance2009 ITRS - Technology ASIC Half TrendsPitch and Gate Length Trends 1000 2009 ITRS MPU/ASIC Metal 1 (M1) ½ Pitch (nm) [historical trailing at 2-yr cycle; extended to 2013; then 3-yr cycle] 2009 ITRS MPU Printed Gate Length (GLpr) (nm) [3-yr cycle from 2011/35.3nm] 1 100 2009 ITRS MPU Physical Gate Length (nm) [begin 3.8-yr cycle from 2009/29.0nm] 2 3 16nm Nanometers (1e-9) 4 10 Equivalent Geometrical Scaling Scaling Near-Term Long-Term 1 1995 2000 2005 2010 2015 2020 2025 Year of Production 2009 ITRS: 2009-2024 July, 2015 ITRS/RC P.Gargini 31 22 nm Tri-Gate Transistor Gates Fins Mark Bohr, Kaizad Mistry, May 2011 July, 2015 ITRS/RC P.Gargini 32 TransistorTransistor InnovationsInnovations EnableEnable TechnologyTechnology CadenceCadence 2003 2005 2007 2009 2011 90 nm 65 nm 45 nm 32 nm 22 nm SiGe SiGe 2nd Gen. 2nd Gen. First to SiGe SiGe Gate-Last Gate-Last Implement Strained Silicon Strained Silicon High-k Metal Gate High-k Metal Gate Tri-Gate Strained Silicon High k Metal gate Tri-Gate July, 2015 ITRS/RC P.Gargini 33 IncubationIncubation TimeTime StrainedStrained SiliconSilicon Metal Gate Insulator •• 19921992-->>20032003 Source Drain HKMGHKMG •• 19961996-->2007>2007 1998 RaisedRaised S/DS/D •• 19931993-->2009>2009 MultiGatesMultiGates •• 19971997-->2011>2011 ~ 12-15 years July, 2015 ITRS/RC P.Gargini 34 Dec 2010 July, 2015 ITRS/RC P.Gargini 35 July, 2015 ITRS/RC P.Gargini 36 2D 3D July, 2015 ITRS/RC P.Gargini 37 Question How many more technology generations can Equivalent Scaling be extended for ? July, 2015 ITRS/RC P.Gargini 38 Multigate FET Offers a Simple Way for Scaling and Improving Performance 5 4 3 Semicon Japan, December 6, 2013 July, 2015 ITRS/RC P.Gargini 39 Mark Bohr, August 11, 2014 July, 2015 ITRS/RC P.Gargini 40 Mark Bohr, August 11, 2014 July, 2015 ITRS/RC P.Gargini 41 Mark Bohr, August 11, 2014 July, 2015 ITRS/RC P.Gargini 42 Second Moore’s Law Acceleration July, 2015 ITRS/RC P.Gargini 43 Mark Bohr, August 11, 2014 July, 2015 ITRS/RC P.Gargini 44 Mark Bohr, August 11, 2014 July, 2015 ITRS/RC P.Gargini 45 TechnologyTechnology NodeNode ScalingScaling Today’s Challenge 14 10 7 5 Technology Node (nm) 3 2021 2019 2017 2015 2013 1 2013 ITRS July, 2015 ITRS/RC P.Gargini 46 Apr 19th 2015 July, 2015 ITRS/RC P.Gargini 47 Phase 3 Third Age of Scaling (3D Power Scaling) July, 2015 ITRS/RC P.Gargini 48 July, 2015 ITRS/RC P.Gargini July, 2015 ITRS/RC P.Gargini 3D NAND Architecture July, 2015 ITRS/RC P.Gargini 51 July, 2015 ITRS/RC P.Gargini 52 July, 2015 ITRS/RC P.Gargini 53 July, 2015 ITRS/RC P.Gargini Kinam Kim, ISSCC, Feb 23, 2015 July, 2015 ITRS/RC P.Gargini 55 Toshiba Develops World's First 48-Layer BiCS (Three Dimensional Stacked Structure Flash Memory) Toshiba, and sample shipments of the 3D structure adopted NAND-type flash memory of 48-layer Date March 27, 2015 Toshiba has announced that the 26th, began sample shipments of NAND-type flash memory that employs a three-dimensional (3D) structure of stacking the storage element vertically. First of the 3D flash memory for the company. At 48 the number of influences layer performance, it exceeded the existing products of competing Korea Samsung Electronics (32 layers). Compared to existing planar structure product, and appeal to the point of excellent writing speed and reliability of data to be proposed, such as enterprise data centers (DC). (Nobuyuki Goto) July, 2015 ITRS/RC P.Gargini 56 July, 2015 ITRS/RC P.Gargini 57 Vertical Logic Architecture July, 2015 ITRS/RC P.Gargini 58 ICIC IndustryIndustry atat aa GlanceGlance (2015(2015-->2021)>2021) Driver Cost/transistor & power reduction How 2x Density/2 years (Moore) Method 3D Power Scaling (ITRS2) July, 2015 ITRS/RC P.Gargini …but the World has changed under are very own eyes July, 2015 ITRS/RC P.Gargini 60 Biochips Sensors Diversification Actuators =Heterogeneous=HeterogeneousHV IntegrationIntegration Power More than Moore: Passives Non-digital content Interacting with people and(SiP) environment MM+MtMMM+MtM System-in-package Analog/RF 2006 Combining SoC and SiP: Heterogeneous Integration 130nm 61 90nm Information Processing 65nm 2006 P.Gargini Digital content 45nm System-on-chip(SoC) 32nm 22nm More Moore: Miniaturization Moore: More Baseline CMOS: CPU, Memory, Logic Memory, CPU, CMOS: Baseline 16 nm.
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