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SIMD-Aware Word Length Optimization for Floating-Point To

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SIMD-Aware Word Length Optimization for Floating-Point To ANNÉE 2017 THÈSE / UNIVERSITÉ DE RENNES 1 sous le sceau de l’Université Bretagne Loire pour le grade de DOCTEUR DE L’UNIVERSITÉ DE RENNES 1 Mention : Informatique Ecole doctorale Matisse présentée par Ali Hassan El Moussawi Préparée à l’Unité Mixte de Recherche 6074 – IRISA Institut de recherche en informatique et systèmes aléatoires UFR Informatique Electronique Thèse soutenue à Rennes SIMD-aware Word le 16/12/2016 devant le jury composé de : Length Optimiza- David Defour MCF - Université de Perpignan / Rapporteur tion for Floating- Lionel Lacassagne PR - Université Pierre et Marie Curie / Rapporteur point to Fixed-point Karine Heydemann MCF - Université Pierre et Marie Curie / Examina- Conversion targe- trice Daniel Menard ting Embedded Pro- PR - INSA Rennes / Examinateur Tomofumi Yuki cessors CR - INRIA Bretagne Atlantique / Examinateur Steven Derrien PR - Université de Rennes 1 / Directeur de thèse Certes, la science guide, dirige et sauve; l’ignorance égare, trompe et ruine. Remerciements Steven a toujours été là pour me conseiller et me motiver, je tiens à le remercier infiniment pour tout ce qu’il a fait pour contribuer à la réussite de mes travaux de thèse. Je remercie d’autant Tomofumi Yuki pour le temps qu’il a consacré pour discuter des divers aspects de cette thèse. Ses conseils avaient un impact important sur ces travaux. Je tiens également à remercier Patrice Quinton pour sa contribution à la revue/correction de ce manuscrit. Je remercie tous les membres du jury, qui m’ont fait l’honneur en acceptant de juger mes travaux, surtout Lionel Lacassagne et David Defour qui ont eu la charge de rapporteurs. Je remercie tout le personnel de l’Inria/Irisa, notamment les membres de l’équipe CAIRN pour le chaleureux accueil qu’ils m’ont réservé. Je remercie, en particulier, Nadia Derouault qui s’est occupée de toutes les démarches administratives, Nicolas Simon et Antoine Morvan pour l’assistance avec les outils de développement, ainsi que Gaël Deest, Simon Rokicki, Baptiste Roux et tous les autres. Last but not least, je tiens à remercier ma famille pour leur support durant toutes ces années. Table of Contents Résumé en Français v List of Figures xi List of Tables xv Glossary xvii 1 Introduction 1 1.1 Context and Motivations . 2 1.2 ALMA Project . 4 1.3 Timeline . 6 1.4 Contributions and Organization . 8 2 Background: Floating-point to Fixed-point Conversion 11 2.1 Introduction . 12 2.2 Floating-point Representation . 12 2.3 Fixed-point Representation . 14 2.4 Floating-point vs. Fixed-point . 16 2.5 Floating-point to Fixed-point Conversion Methodologies . 19 2.5.1 Integer Word Length Determination . 19 2.5.2 Word Length Optimization . 21 2.5.3 Fixed-point Code Generation . 22 2.6 Automatic Conversion Tools . 23 2.6.1 Matlab Fixed-point Converter . 23 2.6.2 IDFix ...................................... 24 2.7 Conclusion . 27 3 Background: Single Instruction Multiple Data 29 3.1 Introduction . 30 3.2 SIMD Instruction Sets . 31 3.2.1 Conventional Vector Processors . 31 3.2.2 Multimedia extensions . 32 i ii TABLE OF CONTENTS 3.3 Exploiting Multimedia extensions . 36 3.3.1 Manual Simdization . 37 3.3.2 Automatic Simdization Methodologies . 38 3.4 Conclusion . 42 4 Superword Level Parallelism 45 4.1 Introduction . 46 4.2 Related work . 47 4.2.1 Original SLP .................................. 48 4.2.2 Original SLP Extensions and Enhancements . 49 4.3 Holistic SLP ...................................... 50 4.3.1 Overview . 51 4.3.2 Shortcomings . 59 4.4 Proposed Holistic SLP Algorithm Enhancements . 64 4.4.1 Pack Flow and Conflict Graph (PFCG) . 65 4.4.2 Group Selection Procedure . 66 4.4.3 Algorithm complexity . 72 4.4.4 Pseudo-code . 74 4.5 Experimental Setup and Results . 78 4.5.1 Implementation . 78 4.5.2 Target processors . 79 4.5.3 Benchmarks . 81 4.5.4 Tests Setup . 81 4.5.5 Results . 82 4.6 Conclusion . 88 5 SLP-aware Word Length Optimization 91 5.1 Introduction . 92 5.2 Motivations and Related Work . 94 5.3 Joint WLO and SLP extraction . 96 5.3.1 Overview and Intuition . 97 5.3.2 Processor Model . 98 5.3.3 SLP-aware WLO algorithm . 101 5.3.4 Accuracy-aware SLP extraction algorithm . 106 5.3.5 SLP-aware Scalings Optimization . 109 5.4 Source-to-source Compilation Flow . 112 5.4.1 Flow Overview . 112 5.4.2 Integer Word Length determination . 114 5.4.3 Accuracy evaluation . 115 5.4.4 Select and sort Basic-blocks for SLP . 115 5.4.5 Fixed-point/SIMD Code Generation . 115 5.5 Experimental evaluation and Results . 116 TABLE OF CONTENTS iii 5.5.1 Experimental Setup . 116 5.5.2 WLO-then-SLP source-to-source flow . 117 5.5.3 Benchmarks . 118 5.5.4 Target Processors . 119 5.5.5 Results . 119 5.5.6 Floating-point vs. Fixed-point . 121 5.5.7 WLO+SLP vs. WLO-then-SLP . 121 5.6 Conclusion . 123 6 Conclusion 125 A Target Processor Models 129 A.1 XENTIUM . 129 A.2 ST240 . 129 A.3 KAHRISMA . 130 A.4 VEX . 130 Publications 133 Bibliography 135 iv TABLE OF CONTENTS Résumé en Français Les processeurs embarqués sont soumis à des contraintes strictes de coût, consommation électrique et performance. Afin de limiter leur coût et/ou leur consommation électrique, certain processeurs ne disposent pas de support matériel pour l’arithmétique à virgule flottante. D’autre part, les applications dans plusieurs domaines, tel que le traitement de signal et la télécommunication, sont généralement spécifiées en utilisant l’arithmétique à virgule flottante, pour des raisons de simplicité. Cette implémentation prototype est ensuite adaptée/optimisée en fonction de l’architecture cible. Porter de telles applications sur des processeurs embarqués sans support matériel pour l’arithmétique à virgule flottante, nécessite une émulation logicielle, qui peut sévèrement dé- grader les performances de l’application. Pour éviter cela, l’application est convertie pour utiliser l’arithmétique à virgule fixe, qui a l’avantage d’être plus efficace à implémenter sur des unités de calcul entier. Les deux representations, à virgule flottante et à virgule fixe sont illustrées dans la fig. 1. La conversion de virgule flottante en virgule fixe est une procédure délicate qui implique W I F 1 E M s i f s e m virgule (implicite) LSB LSB exposant mantisse partie entière partie fractionnelle Nombre representé: sif * 2-F (-1)s * mantisse * 2exposant Figure 1 – Comparaison des representations à virgule flottante (droite) et à virgule fixe (gauche). des compromis subtils entre performance et précision de calcul. Elle permet, entre autre, de réduire la taille des données au prix d’une dégradation de la précision de calcul. En effet, utiliser des opérations à virgule fixe, tout en gardant la précision complète des résultats, nécessite une augmentation considérable des tailles de mots des données. Par exemple, le résultat exact d’une multiplication entre deux nombres de taille w, nécessite une taille de 2w. Cette augmentation de la taille de mots peut dépasser la taille maximale supportée par le processeur cible, nécessitant ainsi une émulation logicielle d’opérateurs de taille plus grande, qui peut aussi bien dégrader la performance de l’application. Afin d’éviter cela, les tailles des données (et des résultats des opérations) sont réduites en appliquant des quantifications, qui correspondent à éliminer les bits de poids faibles. Ces opérations de quantification introduisent des erreurs de calcul, appelées v vi Résumé en Français erreurs de quantifications, qui se propagent dans le système et peut engendrer une erreur impor- tante en sortie, dégradant ainsi la précision du résultat. En règle générale, plus la quantification est grande (i.e. plus la taille des données est réduite), plus la précision est faible mais meilleur est la performance. Il existe donc un compromis entre précision de calcule et performance. Par ailleurs, la plupart des processeurs embarquées fournissent un support pour le calcul vectoriel de type SIMD ("Single Instruction Multiple Data") afin d’améliorer la performance. En effet, cela permet l’exécution d’une opération sur plusieurs données simultanément, réduisant ainsi le temps d’exécution. Cependant, il est généralement nécessaire de transformer l’application pour exploiter les unités de calcul vectoriel. Cette transformation de vectorisation est sensible à la taille des données; plus leurs tailles diminuent, plus le taux de vectorisation augmente. Il apparaît donc un autre compromis entre vectorisation et tailles de données. En revanche, la vectorisation ne conduit toujours pas a une amélioration de performance, elle peut même la dégrader ! En fait, afin d’appliquer une opération vectorielle, il faut d’abord agréger ou compacter les données de chacun des opérandes pour former un vecteur, qui correspond en générale à un registre SIMD. De même, il faut décompacter les données afin de les utiliser séparément, comme le montre la fig. 2. Ces opérations de (dé)compactage peuvent engendrer a1 a2 ... aN ... En mémoire ... compacter compacter a1 b1 a2 b2 aN bN a1 a2 ... aN b1 b2 ... bN Vectorisation ... Compacté + + + + en Registre SIMD c1 c2 cN c1 c2 ... cN décompacter c1 c2 ... cN Figure 2 – Illustration de la transformation de vectorisation remplacant N opérations scalaires par une seule opération SIMD plus les opérations de (dé)compactage. un surcoût important dans le cas où les données sont mal organisées en mémoire. Du coup, afin d’améliorer efficacement la performance, la transformation de vectorisation doit prendre en considération ce surcoût. La conversion de virgule flottante en virgule fixe et la vectorisation sont deux transformations délicates qui nécessitent un temps de développement très élevé. Pour remédier à ça et réduire les délais de mise sur le marché des applications, une multitude de travaux ont ciblé l’automatisation vii (complète ou partielle) de ces transformations.
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