(12) United States Patent (10) Patent No.: US 9,626,896 B2 Lee Et Al

USOO9626896B2

(12) United States Patent (10) Patent No.: US 9,626,896 B2 Lee et al. (45) Date of Patent: Apr. 18, 2017

(54) DISPLAY DEVICE AND MOBILE (58) Field of Classification Search ELECTRONIC APPARATUS INCLUDING None THE SAME See application file for complete search history. (71) Applicant: SAMSUNGELECTRONICS CO., (56) References Cited LTD., Suwon-si, Gyeonggi-do (KR) U.S. PATENT DOCUMENTS (72) Inventors: Seung-Gun Lee, Hwaseong-si (KR): 4.415,985 A * 11/1983 McDaniel ...... GOSB 19,409 Hyo-Jin Kim, Hwaseong-si (KR); 6.229,765 B1 5, 2001 Rabi 345,501 Hak-Seong Lee, Hwaseong-si (KR) 6,393.2634. 4-1 B1 5/2002 Hayashi 6,747,916 B1 6/2004 Fleury et al. (73) Assignee: SAMSUNGELECTRONICS CO., 6,876,600 B2 4/2005 Ito et al. LTD., Suwon-si, Gyeonggi-Do (KR) 7,181,006 B2 2/2007 Shimazaki 8,547,800 B2 10/2013 Kiyomizu (*) Notice: Subject to any disclaimer, the term of this 2003/0051211 A1* 3/2003 Fujisaki ...... Google9. patent is extended or adjusted under 35 U.S.C. 154(b) by 19 days. (Continued) (21) Appl. No.: 14/615,097 FOREIGN PATENT DOCUMENTS KR 102005OOO1526 1, 2005 (22) Filed: Feb. 5, 2015 KR 102O110051897 5, 2011 (65) Prior Publication Data Primary Examiner — Andrew Sasinowski Assistant Examiner — Henok Heyi US 2015/0325213 A1 Nov. 12, 2015 (74) Attorney, Agent, or Firm — F. Chau & Associates, (30) Foreign Application Priority Data LLC (57) ABSTRACT May 7, 2014 (KR) ...... 10-2014-OO53899 A mobile device includes a display driver integrated circuit (51) Int. Cl. (DDI), a display panel, and an application processor. The G09G 5/00 (2006.01) DDI provides an internal synchronization signal based on an G09G 3/20 (2006.01) internal clock signal as a synchronization signal. The appli G09G 5/8 (2006.01) cation processor calculates a time offset corresponding to a G09G 3/3208 (2016.01) difference between a real time and the internal synchroni (52) U.S. Cl. zation signal, and provides the time offset to the DDI. The CPC ...... G09G3/2096 (2013.01); G09G 3/3208 DDI calculates a time to be displayed based on the time (2013.01); G09G 5/008 (2013.01); G09G 5/18 offset and a current time provided from the application (2013.01); G09G 2300/0426 (2013.01); G09G processor, and displays the time to be displayed in the 2310/0243 (2013.01); G09G 2370/10 display panel in a self clock display mode. (2013.01) 21 Claims, 14 Drawing Sheets

RUN SPAY DEWC S210

SEF COCK MODE START S220

SEF COCKDISPLAY MODE S230

UPDATE CURRENT RE & STORE OFFSE WALU

UPDATE NEW CURRENTE & STORE NE OFFSE WALE

S260 COMPARE OFFSWALE

OK EXEND TEPDATE PERIOD

SLEEP OUT US 9,626,896 B2 Page 2

(56) References Cited U.S. PATENT DOCUMENTS

2005/011 1304 A1* 5, 2005 Pikula ...... GO4G 3/00 368,47 2011/0254829 A1 10/2011 Agevik et al. 2011/0285833 A1* 11/2011 Tsurumoto ...... G09G 3/003 34.8/56 2012fO155584 A1* 6, 2012 Wilkinson ...... GO4G 7700 375,354 2012/02873.25 A1* 11/2012 Oikawa ...... HO4N 5,772 348,333.02 2013,0082615 A1 * 4, 2013 Williams ...... HOSB 33,0827 315, 186 2013/0142300 A1* 6, 2013 Takemura ...... GO4F 1,005 377/20 2013/0314360 A1* 11/2013 Saitoh ...... G06F 3,0412 345,173 2015,0033060 A1 1/2015 Kim ...... G06F 1/12 T13/400 * cited by examiner U.S. Patent Apr. 18, 2017 Sheet 1 of 14 US 9,626,896 B2

F. G. 1

OO 200 500

ECLKDP

F. G. 2

100

20 110 130 1 AO

MOBILE SENSING CONNECTV TY MODULE CAMERA & 10 OFFSET re H-131 MODULE

itCALCULATOR was assure was wwres 133 MCC OFV 105

ECLK CT RTG

173

150 160 170 18O U.S. Patent Apr. 18, 2017 Sheet 2 of 14 US 9,626,896 B2

HHA|HCl

9'0|-

U.S. Patent Apr. 18, 2017 Sheet 3 of 14 US 9,626,896 B2

F. G. 4

220

MCC 221 RGB TO 230 DT

MCC 223 ECLK TO 230 CLK

MCC 225 HS, VS TO 230 HS, IWS

F.G. 5

113 115

SYNC (IVS) COUNTER COMPARATOR OFV

REFT U.S. Patent Apr. 18, 2017 Sheet 4 of 14 US 9,626,896 B2

F.G. 6

R E F OF V O VS

FIG 7

260

261 263

ME CLK COUNTER ADJUSTER DCT

CT OFV U.S. Patent Apr. 18, 2017 Sheet S of 14 US 9,626,896 B2 FG. 8

281 280

FG. 9

RUN D!SPLAY DEVICE S110

TRANSMT SYNC SIGNAL S120

CALCULATE TIME OFFSET S130

TRANSMT TIME OFFSET AND CURRNET T ME & SLEEP N S40

ENTER INTO SELF CLOCK DISPLAY MODE S150

SLEEP OUT S160

END U.S. Patent Apr. 18, 2017 Sheet 6 of 14 US 9,626,896 B2

FIG 10

100 200

S110 OPERATING OPERATING

SYNC OPERATING

S130 CALCULATE TME OFFSET OPERATING

S140 OERATING

S150 STOP DISPLAY SELF CLOCK

S160 OPERATING OPERATING U.S. Patent Apr. 18, 2017 Sheet 7 of 14 US 9,626,896 B2

FG 11

100b 300 500

120 11 Ob 130 140

SENSING CONNECTV TY MOBILE MODULE CAMERA & 1/O CPU SENSOR1-131 MODULE SENSOR2-133 MCC 105 ECLKCT RTG MEMORY NTERFACE POWER SUPPLY 173b

150 160 ITR 170b 180

U.S. Patent Apr. 18, 2017 Sheet 9 of 14 US 9,626,896 B2

F.G. 14

350

351 352 353

OFFSET WS COUNTER REGISTER CALCULATOR

CTi CT(i+1) CT CT(i+1) OFV

COMPARATOR 354

INTERRUPT TR SIGNAL GENERATOR

357

CLK INTERNAL TIMER DCT

OFV U.S. Patent Apr. 18, 2017 Sheet 10 of 14 US 9,626,896 B2

sus-a- &-- -

o U.S. Patent Apr. 18, 2017 Sheet 11 of 14 US 9,626,896 B2

FG 16

CSTART

RUN DISPLAY DEVCE S210

SELF CLOCK MODE START S220

SELF CLOCK DISPLAY MODE S230

UPDATE CURRENT TIME & STORE OFFSET VALUE S240

UPDATE NEW CURRENT TIME & STORE N-S250 NEW OFFSET VALUE

COMPARE OFFSET VALUE

EXTEND TIME UPDATE PERIOD S270

SLEEP OUT S280 U.S. Patent Apr. 18, 2017 Sheet 12 of 14 US 9,626,896 B2

FG 17

100b 300

S210, S220: OPERATING OPERATING

S230. STOP OPERATING

UPDATE CT STORE S240: OFFSET

S250: STORE NEW OFFSET

U.S. Patent Apr. 18, 2017 Sheet 13 of 14 US 9,626,896 B2

F.G. 18

U.S. Patent Apr. 18, 2017 Sheet 14 of 14 US 9,626,896 B2

F.G. 19

600

3D IMAGE SENSOR 700

2D IMAGE SENSOR 800 620 N- CONNECTV TY

USER INTERFACE 640 MEMORY 630 DEVICE

POWER 650 SUPPLY US 9,626,896 B2 1. 2 DISPLAY DEVICE AND MOBILE The time adjuster may receive the current time and the time ELECTRONIC APPARATUS INCLUDING offset, may adjust the current time based on the counting THE SAME value and the time offset, and may provide the digital time information. CROSS-REFERENCE TO RELATED In an exemplary embodiment, the DDI may further APPLICATION include a symbol memory and a control logic circuit. The symbol memory may store a plurality of timing symbols that This application claims priority under 35 U.S.C. S 119 to are used for displaying the time to be displayed. The control Korean Patent Application No. 10-2014-0053899, filed on logic circuit may control the symbol memory Such that, May 7, 2014, in the Korean Intellectual Property Office, the 10 among the plurality of timing symbols, timing symbols disclosure of which is incorporated by reference herein in its associated with the time to be displayed may be output. entirety. In an exemplary embodiment, the DDI may further include a selection circuit. The selection circuit may select TECHNICAL FIELD one of an image signal and the time to be displayed, and may 15 provide the selected one of the image signal and the time to Exemplary embodiments of the present inventive concept be displayed to a timing controller in response to a mode relate to a display device, and more particularly to, a mobile change signal. The mode change signal may be one of the electronic apparatus including the display device. self clock display mode and a video mode. The image signal provided from the application processor may be displayed in DISCUSSION OF THE RELATED ART the video mode. In an exemplary embodiment, the application processor Some Smart phones have a display device capable of may include an offset calculator and a real time generator. displaying high-definition television (HDTV) signals. The The offset calculator may calculate the real time and the time Smartphone may include a display driver integrated circuit offset based on the synchronization signal. The real time (IC) for managing the HDTV signals to the display device. 25 generator may generate the real time. For example, the display device may be an organic light In an exemplary embodiment, the application processor emitting display (OLED). may be connected to the DDI through a high speed serial In addition, the Smartphones can be configured to connect interface (HSSI). The application processor may enter into a to wearable devices. sleep mode in the self clock display mode. The display 30 device may include a watch-typed wearable device. SUMMARY According to an exemplary embodiment of the present inventive concept, a mobile device includes an application According to an exemplary embodiment of the present processor, a display panel, and a display driver integrated inventive concept, a mobile device includes a display driver circuit (DDI). The application processor provides a current integrated circuit (DDI), a display panel, and an application 35 time indicating a real time in response to an interrupt signal processor. The DDI provides an internal synchronization that is periodically received. The DDI provides an internal signal based on an internal clock signal as a synchronization synchronization signal based on an internal clock signal, signal. The application processor calculates a time offset adjusts a period of the interrupt signal that is provided to the corresponding to a difference between a real time and the application processor based on time offsets, and calculates a internal synchronization signal, and provides the time offset 40 time to be displayed based on the current time. Further, the to the DDI. The DDI calculates a time to be displayed based DDI displays the time to be displayed in the display panel. on the time offset and a current time provided from the Each of the time offsets corresponds to a difference between application processor, and displays the time to be displayed the current time and the internal synchronization signal. in the display panel in a self clock display mode. In an exemplary embodiment, the DDI may include an In an exemplary embodiment, the DDI may include an 45 oscillator, an internal synchronization signal generator, and oscillator, an internal synchronization signal generator, and a timer logic circuit. The oscillator may generate the internal a timer logic circuit. The oscillator may generate the internal clock signal. The internal synchronization signal generator clock signal. The internal synchronization signal generator may generate an internal horizontal synchronization signal may generate an internal horizontal synchronization signal and an internal vertical synchronization signal based on the and an internal vertical synchronization signal based on the 50 internal clock signal. The timer logic circuit may generate internal clock signal. The timer logic circuit may generate digital time information corresponding to the time to be digital time information corresponding to the time to be displayed based on an internal synchronization signal, the displayed based on the time offset, the internal clock signal, internal clock signal, and the current time. The internal and the current time. synchronization signal may be one of the internal horizontal In an exemplary embodiment, the DDI may further 55 synchronization signal and the internal vertical synchroni include an interface that provides the application processor Zation signal. with one of the internal horizontal synchronization signal In an exemplary embodiment, the timer logic circuit may and the internal vertical synchronization signal as the Syn include a register, a comparator, and an interrupt signal chronization signal. generator. The register may store the time offsets. The In an exemplary embodiment, the timer logic circuit may 60 comparator may calculate a difference between two con include a register and an internal timer. The register may secutive time offsets among the time offsets, and may output store the time offset. The internal timer may output the a digital code corresponding to the difference between the digital time information based on the internal clock signal, two consecutive time offsets. The interrupt signal generator the current time, and the time offset stored in the register. may adjust an activation period of the interrupt signal, in In an exemplary embodiment, the internal timer may 65 response to the digital code. include a counter and a time adjuster. The counter may count In an exemplary embodiment, the interrupt signal gen the internal clock signal, and may output a counting value. erator may increase the activation period of the interrupt US 9,626,896 B2 3 4 signal in response to the digital code when there is no and an internal clock signal and displays the time to be difference between the two consecutive time offsets. displayed in a display panel in the self clock display mode. In an exemplary embodiment, the interrupt signal gen erator may maintain the activation period of the interrupt BRIEF DESCRIPTION OF THE DRAWINGS signal in response to the digital code when there is a difference between the two consecutive time offsets. Illustrative, non-limiting exemplary embodiment of the In an exemplary embodiment, the DDI may further present inventive concept will be more clearly understood include a temperature sensor. The temperature sensor may from the following detailed description taken in conjunction sense an operating temperature of the DDI. The temperature with the accompanying drawings. sensor may provide the interrupt signal generator with a 10 FIG. 1 is a block diagram illustrating an example of a temperature signal that is activated when the sensed oper display device according to an exemplary embodiment of ating temperature is out of a reference time range. The the present inventive concept. interrupt signal generator may provide the interrupt signal to FIG. 2 is a block diagram illustrating an example of the the application processor in response to the temperature application processor in FIG. 1 according to an exemplary 15 embodiment of the present inventive concept. signal. FIG. 3 is a block diagram illustrating an example of the In an exemplary embodiment, the application processor display driver integrated circuit (DDI) in FIG. 1 according may enter into a sleep mode after the application processor to an exemplary embodiment of the present inventive con transmits the current time to the DDI in response to the cept. interrupt signal. FIG. 4 is a circuit diagram illustrating the selection unit in According to an exemplary embodiment, a mobile elec FIG.3 according to an exemplary embodiment of the present tronic apparatus includes a mobile device and a display inventive concept. device. The display device operates in cooperation with the FIG. 5 is a block diagram illustrating an example of the mobile device. The display device includes an application offset calculator in FIG. 2 according to an exemplary processor and a display driver integrated circuit (DDI). The 25 embodiment of the present inventive concept. application processer includes a real time generator that FIG. 6 is a timing diagram illustrating that the time offset generates a real time. The DDI is connected to the applica is calculated. tion processor through a high speed serial interface (HSSI). FIG. 7 is a block diagram illustrating an example of the The DDI provides an internal synchronization signal based internal timer in FIG.3 according to an exemplary embodi on an internal clock signal. The DDI calculates a time to be 30 ment of the present inventive concept. displayed based on a time offset corresponding to a differ FIG. 8 illustrates the symbol memory in FIG.3 according ence between a current time provided from the application to an exemplary embodiment of the present inventive con processor and the internal Synchronization signal, and dis cept. plays the time to be displayed in a display panel in a self FIGS. 9 and 10 are flow charts illustrating operation of the 35 display device of FIG. 1 according to an exemplary embodi clock display mode. ment of the present inventive concept. In an exemplary embodiment, the mobile device may FIG. 11 is a block diagram illustrating an example of a include a Smart phone, and the display device may include display device according to an exemplary embodiment of a watch-typed wearable device. the present inventive concept. In an exemplary embodiment, the DDI may include may 40 FIG. 12 is a block diagram illustrating an example of the include an oscillator, an internal synchronization signal application processor in FIG. 11 according to an exemplary generator, and a timer logic circuit. The oscillator may embodiment of the present inventive concept. generate the internal clock signal. The internal Synchroni FIG. 13 is a block diagram illustrating an example of the Zation signal generator may generate an internal horizontal DDI in FIG. 11 according to an exemplary embodiment of synchronization signal and an internal vertical synchroniza 45 the present inventive concept. tion signal based on the internal clock signal. The timer logic FIG. 14 is a block diagram illustrating an example of the circuit may generate digital time information corresponding timer logic circuit in FIG. 13 according to an exemplary to the time to be displayed based on the time offset, the embodiment of the present inventive concept. internal clock signal and the current time. FIG. 15 illustrates various signals in the timer logic circuit In an exemplary embodiment, the DDI may include an 50 of FIG. 14 according to an exemplary embodiment of the oscillator, an internal synchronization signal generator, and present inventive concept. a timer logic. The oscillator may generate the internal clock FIGS. 16 and 17 are flowcharts illustrating operation of signal. The internal synchronization signal generator may the display device of FIG. 11 according to an exemplary generate an internal horizontal synchronization signal and an embodiment of the present inventive concept. 55 FIG. 18 is a block diagram illustrating a mobile electronic internal vertical synchronization signal based on the internal apparatus according to an exemplary embodiment of the clock signal. The timer logic may generate digital time present inventive concept. information corresponding to the time to be displayed based FIG. 19 is a block diagram illustrating the mobile device on an internal synchronization signal, the internal clock of FIG. 18 according to an exemplary embodiment of the signal and the current time. The internal synchronization 60 present inventive concept. signal may be one of the internal horizontal synchronization signal and the internal vertical synchronization signal. DETAILED DESCRIPTION OF THE Accordingly, the DDI may reduce power consumption by EMBODIMENTS cutting off interfacing with the application processor in the self clock display mode because the DDI calculates for itself 65 Various exemplary embodiments of the present inventive the time to be displayed based on the current time and the concept will be described more fully hereinafter with refer time offset corresponding to a difference between a real time ence to the accompanying drawings, in which exemplary US 9,626,896 B2 5 6 embodiments thereof are shown. The present inventive The data packet DP may include the image data, a horizontal concept may, however, be embodied in many different forms synchronization signal, a vertical synchronization signal, and should not be construed as limited to the exemplary and a data enable signal. embodiments set forth herein. These exemplary embodi In addition, the application processor 100 may provide the ments of the present inventive concept are just that— DDI 200 with a time offset OFV and a current time CT that examples—and many implementations and variations are indicates a real time in response to a synchronization signal possible that do not require the details provided herein. It SYNC provided from the DDI 200. The time offset OFV should also be emphasized that the present inventive concept may correspond to a difference between the real time and an provides details of alternative examples, but such listing of internal clock signal that is internally generated in the DDI alternatives is not exhaustive. Furthermore, any consistency 10 200. The DDI 200 may include an RC oscillator that of detail between various examples should not be interpreted generates the internal clock signal. The internal clock signal as requiring Such detail it is impracticable to list every may have an error with respect to the real time, and the error possible variation for every feature described herein. The may correspond to the time offset OFV. language of the claims should be referenced in determining The DDI 200, in a video mode, may process the image the requirements of the present inventive concept. Like 15 data in the data packet DP and may output a display data numerals may refer to like elements throughout. DDTA to the display panel 500. In addition, the DDI 200, in It will be understood that, although the terms first, second, a self clock display mode, may calculate internally a time to third etc. may be used herein to describe various elements, be displayed based on the time offset OFV and the current these elements should not be limited by these terms. These time CT and may output the time to be displayed to the terms are used to distinguish one element from another. display panel 500 as the display data DDTA. For example, Thus, a first element discussed below could be termed a the DDI 200, in the self clock display mode, may reduce second element without departing from the teachings of the power consumption by calculating internally the time to be present inventive concept. As used herein, the term “and/or displayed and outputting the time to be displayed to the includes any and all combinations of one or more of the display panel 500 as the display data DDTA without inter associated listed items. 25 facing with the application processor 100. It will be understood that when an element is referred to In an exemplary embodiment, the application processor as being “connected' or “coupled to another element, it can 100 and the DDI 200 may provide an interface such as a be directly connected or coupled to the other element or mobile industry processor interface (MIPI), a mobile display intervening elements may be present. In contrast, when an digital interface (MDDI), a compact display port (CDP), or element is referred to as being “directly connected” or 30 the like. In an exemplary embodiment, the DDI 200 may “directly coupled to another element, there are no inter include a graphic memory for a high speed serial interface. vening elements present. Other words used to describe the Without the graphic memory, the DDI 200 may consume relationship between elements should be interpreted in a like more power and may produce more heat. Further, the load on fashion (e.g., “between versus “directly between.” “adja the application processor 100 may be reduced when the cent versus “directly adjacent,” etc.). 35 graphic memory is included within the DDI 200. Display The terminology used herein is for the purpose of describ data that is input from the application processor 100 may be ing particular exemplary embodiments only and is not written into the graphic memory, and data stored in the intended to be limiting of the present inventive concept. As graphic memory may be output through a scan operation. In used herein, the singular forms “a,” “an and “the are an exemplary embodiment, the graphic memory may be a intended to include the plural forms as well, unless the 40 dual port dynamic random access memory (DRAM). context clearly indicates otherwise. It will be further under The display panel 500 may display the display data DDTA stood that the terms “comprises” and/or “comprising,” when in units of frames according to a control of the DDI 200. The used in this specification, specify the presence of Stated display panel 500 may be one of an organic light-emitting features, integers, steps, operations, elements, and/or com display (OLED) panel, a liquid crystal display (LCD) panel, ponents, but do not preclude the presence or addition of one 45 a plasma display panel (PDP), an electrophoretic display or more other features, integers, steps, operations, elements, panel, and an electrowetting display panel. However, the components, and/or groups thereof. present inventive concept is not limited thereto. Unless otherwise defined, all terms (including technical FIG. 2 is a block diagram illustrating an example of the and Scientific terms) used herein have the same meaning as application processor in FIG. 1 according to an exemplary commonly understood by one of ordinary skill in the art to 50 embodiment of the present inventive concept. which the present inventive concept belongs. It will be Referring to FIG. 2, the application processor 100 may further understood that terms, such as those defined in include a mobile central processing unit (CPU) 110, a commonly used dictionaries, should be interpreted as having connectivity and input/output unit 120, a sensing module a meaning that is consistent with their meaning in the 130, a camera module 140, a memory 150, an interface 160, context of the relevant art and will not be interpreted in an 55 a real time generator 170, and a power supply 180 which are idealized or overly formal sense unless expressly so defined connected to each other via a system bus 105. herein. The mobile CPU 110 may control an overall operation of FIG. 1 is a block diagram illustrating an example of a the application processor 100 and may include an offset display device according to an exemplary embodiment of calculator that generates the time offset OFS. the present inventive concept. 60 The connectivity and input/output unit 120 may commu Referring to FIG. 1, a display device 10 may include an nicate with an external device, and may receive/output data application processor 100, a display driver integrated circuit from/to a user. The connectivity and input/output unit 120 (DDI) 200, and a display panel 500. may include a baseband chipset and may perform Bluetooth The application processor 100 may control an overall communication. operation of the display device 10. The application processor 65 The sensing module 130 may sense a current status of the 100 may provide the DDI 200 with a data packet DP display device 10 Such as a user's contact and may generate including image data in response to a clock signal ECLK. sensing signals for controlling the display device 10. The US 9,626,896 B2 7 8 sensing module 130 may include an acceleration sensor 131 internal clock signal ICLK to the timing controller 230 in and a gyro sensor 133. The acceleration sensor 131 may be response to the mode change signal MCC. The selection unit a device that converts a change of acceleration with respect 220 may also select one pair of the synchronization signals to one direction to an electrical signal. The gyro sensor 133 HS and VS and the internal synchronization signals IHS and may sense an inclination of the display device 10 and may 5 IVS, and may provide the selected pair of the synchroniza generate a sensing signal indicating an inclined amount. tion signals HS and VS and the internal synchronization The camera module 140 may include an image sensor and signals IHS and IVS to the timing controller 230 in response may process image frames Such as still images or moving to the mode change signal MCC. images captured by the image sensor in an image-capturing The timing controller 230 may provide the data driver 233 mode. The camera module 140 may display the processed 10 with one of the image data RGB and the time to be displayed image frames in the display panel 500. The image frames DT as a display data DTA. The timing controller 230 may processed by the cameral module 140 may be stored in the generate a data control signal DCS for controlling the data memory 150 or may be transmitted to an external device via driver 233 and a gate control signal GCS for controlling the the connectivity and input/output unit 120. gate driver 235. The timing controller 230 may provide the The memory 120 may store programs for processing and 15 data control signal DCS to the data driver 233 and may controlling the mobile CPU 110 and may temporarily store provide the gate control signal GCS to the gate driver 235, data that are input or output. The memory 160 may include based one pair of the synchronization signals HS and VS and at least one storage media Such as a flash memory type, a the internal synchronization signals IHS and IVS. The data hard disk type, a multimedia card micro type, a random driver 233 and the gate driver 235 may display the display access memory (RAM), and a read-only memory (ROM). data DTA as the display data DDTA in units of frames, based The interface 160 may perform interfacing with the DDI on the data control signal DCS and the gate control signal 200. The interface 160 may perform high speed serial GCS. interfacing with the DDI 200. For example, the mobile CPU The oscillator 240 may generate the internal clock signal 110 may provide the DDI 200 with the time offset OFV ICLK and may provide the internal clock signal ICLK to the generated by the offset calculator 111 via the interface 160. 25 internal synchronization signal generator 243 and the timer The real time generator 170 may include a crystal oscil logic circuit 250. The internal synchronization signal gen lator 173, and may generate the current time CT correspond erator 243 may divide the internal clock signal ICLK and ing to the real time and the clock signal ECLK. The current may generate the internal horizontal synchronization signal time CT may be provided to the DDI 200 vial the interface IHS and the internal vertical synchronization signal IVS. 160. In addition, the current time CT may be provided to the 30 The internal synchronization signal generator 243 may pro offset calculator 111. vide the internal horizontal synchronization signal IHS and The power supply 180 may provide power required for the internal vertical synchronization signal IVS to the inter operating the display device 10. The power supply 180 may face 210 and the selection unit 220. The interface 210 may include a rechargeable battery. When the display device 10 provide the application processor 100 with one of the is a portable device Such as a wearable device, capacity of 35 internal horizontal synchronization signal IHS and the inter the power supply 180 is limited. Therefore, reduction of nal vertical synchronization signal IVS as the synchroniza power consumption of the display device 10 is important. tion signal SYNC. The internal vertical synchronization FIG. 3 is a block diagram illustrating an example of the signal IVS may have a frequency of about 60 Hz. display driver integrated circuit (DDI) in FIG. 1 according The timer logic circuit 250 may include a register 251 and to an exemplary embodiment of the present inventive con 40 an internal timer 260. The timer logic circuit 250 may cept. receive the time offset OFV and the current time CT and the Referring to FIG. 3, the DDI 200 may include an interface internal clock signal ICLK, and may provide the control 210, a selection unit 220, a timing controller 230, a data logic circuit 270 with digital time information DCT corre driver 233, a gate driver 235, an oscillator 240, an internal sponding to the time to be displayed, based on the time offset synchronization signal generator 243, a timer logic circuit 45 OFV, the current time CT, and the internal clock signal 250, a control logic circuit 270, and a symbol memory 280. ICLK. The register 251 may store the time offset OFV and The interface 210 may receive a clock signal ECLK, the may provide the time offset OFV to the internal timer 260. data packet DP the time offset OFV, and the current time CT The internal timer 260 may generate the digital time infor from the application processor 100, and may provide the mation DT based on the time offset OFV, the current time synchronization signal SYNC to the application processor 50 CT, and the internal clock signal ICLK. 100. The interface 210 may provide the timer logic circuit The control logic circuit 270 may receive the digital time 250 with the time offset OFV and the current time CT. The information DCT and may provide the symbol memory 280 interface 210 may also provide the selection unit 220 with with addresses associated with timing symbols correspond the clock signal ECLK, image data RGB included in the data ing to the digital time information DCT. The symbol packet DP, a horizontal synchronization signal HS, and a 55 memory 280 may output, to the selection unit 220, the vertical synchronization signal VS. timing symbols designated by the addresses as the time to be The selection unit 220 may further receive a time to be displayed DT, in response to the addresses from the control displayed DT, an internal clock signal ICLK, an internal logic circuit 270. horizontal synchronization signal IHS, and an internal ver FIG. 4 is a circuit diagram illustrating the selection unit in tical synchronization signal IVS. The selection unit 220 may 60 FIG.3 according to an exemplary embodiment of the present select one of the image data RGB and the time to be inventive concept. displayed DT, and may provide the selected one of the image Referring to FIG. 4, the selection unit 220 may include data RGB and the time to be displayed DT to the timing first through third multiplexers 221, 223, and 225. controller 230 in response to a mode change signal MCC. The first multiplexer 221 may select one of the image data The selection unit 220 may also select one of the clock 65 RGB and the time to be displayed DT, and may provide the signal ECLK and the internal clock signal ICLK, and may selected one of the image data RGB and the time to be provide the selected one of the clock signal ECLK and the displayed DT to the timing controller 230 in response to the US 9,626,896 B2 9 10 mode change signal MCC. For example, the first multiplexer time information DCT based on the counting value CV2 221 may select the image data RGB when the mode change after the time adjuster 263 receives the current time CT. The signal MCC directs the video mode. The first multiplexer time adjuster 263 may output the digital time information 221 may select the time to be displayed DT when the mode DCT corresponding to the real time by correcting errors of change signal MCC directs the self clock display mode. The the counting value CV2 based on the time offset OFV. For second multiplexer 223 may select one of the clock signal example, when the counting value CV2 is less than the ECLK and the internal clock signal ICLK, and may provide reference time value REFT based on the current time CT, the the selected one the clock signal ECLK and the internal time adjuster 263 may add the counting value CV2 and the clock signal ICLK to the timing controller 230 in response time offset OFV to the current time CT, and may output the to the mode change signal MCC. For example, the second 10 digital time information DCT. In addition, when the count multiplexer 223 may select the clock signal ECLK when the ing value CV2 is greater than the reference time value REFT mode change signal MCC directs the video mode. The based on the current time CT, the time adjuster 263 may second multiplexer 223 may select the internal clock signal sequentially add the counting value CV2 to the current time ICLK when the mode change signal MCC directs the self CT and subtract the time offset OFV from the current time clock display mode. The third multiplexer 225 may select 15 CT, and may output the digital time information DCT. one pair of the synchronization signals HS and VS and the FIG. 8 illustrates the symbol memory in FIG.3 according internal synchronization signals IHS and IVS, and may to an exemplary embodiment of the present inventive con provide the selected pair of the synchronization signals HS cept. and VS and the internal synchronization signals IHS and Referring to FIG. 8, the symbol memory 280 may store a IVS to the timing controller 230 in response to the mode plurality of timing symbols 281-28k that are used for change signal MCC. For example, the third multiplexer 225 displaying the time to be displayed. The symbol memory may select the synchronization signals HS and VS when the 280 may provide the selection unit 220 with timing symbols mode change signal MCC directs the video mode. The third of the plurality of timing symbols 281-28k associated with multiplexer 225 may select the internal synchronization the digital time information DCT as the time to be displayed signals IHS and IVS when the mode change signal MCC 25 in response to addresses from the control logic circuit 270. directs the self clock display mode. The symbol memory 280 may be implemented separately FIG. 5 is a block diagram illustrating an example of the from the graphic memory or may be implemented as a offset calculator in FIG. 2 according to an exemplary portion of the graphic memory. embodiment of the present inventive concept. FIGS. 9 and 10 are flowcharts illustrating operation of the Referring to FIG. 5, the offset calculator 111 may include 30 display device of FIG. 1 according to an exemplary embodi a counter 113 and a comparator 115. The counter 113 may ment of the present inventive concept. count the synchronization signal SYNC (e.g., the internal Hereinafter, an operation of the display device 10 will be vertical synchronization signal IVS) to a predetermined described in detail with reference to FIGS. 1 through 10. number, and may output a counting value CV1 to the The display device 10 is run (S.110). When the display comparator 115. The comparator 115 may compare the 35 device 10 is run, the application processor 100 and the DDI counting value CV1 and a reference time value REFT, and 200 may be in an operating state. When the DDI 200 does may output the time offset OFV indicating a difference not receive the image data RGB from the application pro between the counting value CV1 and the reference time cessor 100 for a predetermined time, the DDI 200 may value REFT. The reference time value REFT may be pro transmit the synchronization signal SYNC to the application vided from the real time generator 170 in FIG. 2. 40 processor 100 for entering into the self clock display mode FIG. 6 is a timing diagram illustrating that the time offset (S210). When the application processor 100 receives the is calculated. synchronization signal SYNC, the application processor 100 Referring to FIGS. 5 and 6, when a frequency of the (e.g., the mobile CPU 110) may calculate the time offset internal vertical synchronization signal IVS is 60 Hz, sixty OFV corresponding to a difference between the synchroni clocks must be counted during one second. However, when 45 zation signal SYNC and the current time CT based on the the oscillator 240 which serves as a base for generating the real time, by counting toggling of the synchronization signal internal vertical synchronization signal IVS is an RC oscil SYNC (S130). The application processor 100 may transmit lator, an error may occur in the internal vertical synchroni the time offset OFV and the current time CT to the DDI 200 zation signal IVS. Therefore, a time required for the internal (S140). The application processor 100 may enter into a sleep vertical synchronization signal IVS to toggle sixty times 50 mode after transmitting the time offset OFV and the current may be greater than the reference time value REFT. The time CT to the DDI 200. The DDI 200 may enter into the self difference between the time required for the internal vertical clock display mode and may calculate the time to be synchronization signal IVS and the reference time value displayed DT based on the time offset OFV and the current REFT may correspond to the time offset OFV. time CT. The DDI 200 may display the time to be displayed FIG. 7 is a block diagram illustrating an example of the 55 DT in the display panel 500 periodically (S150). In the self internal timer in FIG.3 according to an exemplary embodi clock display mode, interfacing relationship between the ment of the present inventive concept. application processor 100 and the DDI 200 may be cut off. Referring to FIG. 7, the internal timer 260 may include a When the data such as the image data RGB is to be counter 261 and a time adjuster 263. The counter 261 may transmitted from the application processor 100 to the DDI count the internal clock signal ICLK and may output a 60 200, the application processor 100 may exit from the sleep counting value CV2 indicating the counted internal clock mode (S160). signal ICLK. The time adjuster 263 may receive the count FIG. 11 is a block diagram illustrating another example of ing value CV2, the current time CT, and the time offset OFV. a display device according to an exemplary embodiment of and may output the digital time information DCT corre the present inventive concept. sponding to the time to be displayed based on the counting 65 Referring to FIG. 11, a display device 20 may include an value CV2, the current time CT, and the time offset OFV. application processor 100b, a DDI 300, and a display panel The time adjuster 263 may output periodically the digital SOO. US 9,626,896 B2 11 12 The application processor 100b may control an overall CT to the DDI 300 whenever the real time generator 170b operation of the display device 20. The application processor receives the interrupt signal ITR from the DDI 300. 100 may provide the DDI 200 with a data packet DP FIG. 13 is a block diagram illustrating an example of the including image data in response to a clock signal ECLK. DDI in FIG. 11 according to an exemplary embodiment of The data packet DP may include the image data, a horizontal the present inventive concept. synchronization signal, a vertical synchronization signal, Referring to FIG. 13, the DDI 300 may include an and a data enable signal. interface 310, a selection unit 320, a timing controller 330, In addition, the application processor 100b may provide a data driver 333, a gate driver 335, an oscillator 340, an the DDI 300 with a current time CT indicating a real time in internal synchronization signal generator 341, a timer logic response to an interrupt signal ITR provided from the DDI 10 circuit 350, a control logic circuit 370, and a symbol 3OO. memory 380. The DDI may further include a temperature The DDI 300, in a video mode, may process the image sensor 390. The temperature sensor 390 may sense an data in the data packet DP and may output display data operating temperature of the DDI 300 and may provide a DDTA to the display panel 500. In addition, the DDI 300, in temperature signal TS to the timer logic circuit 350. The a self clock display mode, may calculate internally the time 15 temperature sensor 390 may provide the timer logic circuit offset OFV and may adaptively adjust a receiving period of 350 with the temperature signal TS that is activated when the current time CT from the application processor 100b based sensed operating temperature is out of a reference time on the time offset OFV. The time offset OFV may correspond range. to a difference between the real time and an internal clock The interface 310 may receive the clock signal ECLK, the signal that is internally generated in the DDI 300. The DDI data packet DP and the current time CT from the application 300 may include an RC oscillator that generates the internal processor 100b, and may provide the interrupt signal ITR to clock signal. The internal clock signal may have an error the application processor 100b. The interface 310 may with respect to the real time, and the error may correspond provide the timer logic circuit 350 with the current time CT. to the time offset OFV. For example, the DDI 300, in the self The interface 310 may also provide the selection unit 320 clock display mode, may reduce power consumption by 25 with the clock signal ECLK, image data RGB included in adaptively adjusting the receiving period (or updating the the data packet DP. a horizontal synchronization signal HS, period) of the current time CT from the application proces and a vertical synchronization signal VS. Sor 100, calculating the time to be displayed, and outputting The selection unit 320 may further receive a time to be the time to be displayed as the display data DDTA in the displayed DT, an internal clock signal ICLK, an internal display panel 500. 30 horizontal synchronization signal IHS, and an internal ver In an exemplary embodiment, the application processor tical synchronization signal IVS. The selection unit 320 may 100b and the DDI 300 may provide an interface such as an select one of the image data RGB and the time to be MIPI, an MDDI, a CDP, or the like. In an exemplary displayed DT, and may provide the selected one of the image embodiment, the DDI 300 may include a graphic memory data RGB and the time to be displayed DT to the timing for a high speed serial interface (HSSI). When the graphic 35 controller 330 in response to the mode change signal MCC. memory is not used, the DDI 300 may consume more power The selection unit 320 may also select one of the clock and produce more heat. Further, the load on the application signal ECLK and the internal clock signal ICLK, and may processor 100b may be reduced when the graphic memory provide the selected one of the clock signal ECLK and the is included within the DDI 300. Display data that is input internal clock signal ICLK to the timing controller 330 in from the application processor 100b may be written into the 40 response to the mode change signal MCC. The selection unit graphic memory, and data stored in the graphic memory may 320 may also select one pair of the synchronization signals be output through a scan operation. In an exemplary embodi HS and VS and the internal synchronization signals IHS and ment, the graphic memory may be a dual port DRAM. IVS, and may provide the selected pair of the synchroniza FIG. 12 is a block diagram illustrating an example of the tion signals HS and VS and the internal synchronization application processor in FIG. 11 according to an exemplary 45 signals IHS and IVS to the timing controller 330 in response embodiment of the present inventive concept. to the mode change signal MCC. Referring to FIG. 12, the application processor 100b may The timing controller 330 may provide the data driver 333 include a mobile CPU 110b, a connectivity and input/output with one of the image data RGB and the time to be displayed unit 120, a sensing module 130, a camera module 140, a DT as a display data DTA. The timing controller 330 may memory 150, an interface 160, a real time generator 170b, 50 generate a data control signal DCS for controlling the data and a power supply 180 which are connected to each other driver 233 and a gate control signal GCS for controlling the via a system bus 105. gate driver 335. The timing controller 330 may provide the The application processor 100b of FIG. 12 may differ data control signal DCS to the data driver 333 and may from the application processor 100 of FIG. 2 in operations provide the gate control signal GCS to the gate driver 335, of the mobile CPU 110b and the real time generator 170b, 55 respectively, based one pair of the synchronization signals and thus there will be description on the operations of the HS and VS and the internal synchronization signals IHS and mobile CPU 110b and the real time generator 170b, and IVS. The data driver 333 and the gate driver 335 may display description on operations of other components will be the display data DTA as the display data DDTA in units of omitted. frames, based on the data control signal DCS and the gate The mobile CPU 110b may control an overall operation of 60 control signal GCS. the application processor 100b. The mobile CPU 110b may The oscillator 340 may generate the internal clock signal output a mode change signal MCC directing an operating ICLK, and may provide the internal clock signal ICLK to the mode of the DDI 300. internal synchronization signal generator 341 and the timer The real time generator 170b may include a crystal logic circuit 350. The internal synchronization signal gen oscillator 173b and may generate the current time CT 65 erator 341 may divide the internal clock signal ICLK, and corresponding to the real time and the clock signal ECLK. may generate the internal horizontal synchronization signal The real time generator 170b may provide the current time IHS and the internal vertical synchronization signal IVS. US 9,626,896 B2 13 14 The internal synchronization signal generator 341 may pro and the time offsets OFVi. A configuration of the internal vide the internal horizontal synchronization signal IHS and timer 357 may be substantially the same as the configuration the internal vertical synchronization signal IVS to the selec of the internal timer 260 of FIG. 7. tion unit 320. The internal vertical synchronization signal FIG. 15 illustrates various signals in the timer logic circuit IVS may have a frequency of about 60 Hz. of FIG. 14 according to an exemplary embodiment of the The timer logic circuit 350 may receive the internal present inventive concept. synchronization signals IHS and IVS, the current time CT, Referring to FIGS. 14 and 15, the counter 351 may output and the internal clock signal ICLK, and may provide the a counting value CV31 by counting toggling numbers of the control logic circuit 370 with a digital time information DCT internal vertical synchronization signal IVS during a time corresponding to the time to be displayed based on the 10 internal synchronization signals IHS and IVS, the current interval between current times CT(1) and CT(2), and may time CT, and the internal clock signal ICLK. In addition, the output a counting value CV32 by counting toggling numbers timer logic circuit 350 may provide the application proces of the internal vertical synchronization signal IVS during a sor 100b with the interrupt signal ITR for receiving the time interval between current times CT(2) and CT(3). The current time CT via the interface 310. 15 offset calculator 352 may calculate a time offset OFV1 by The control logic circuit 370 may receive the digital time comparing a reference time value REFT2 with the counting information DCT, and may provide the symbol memory 380 value CV31, may calculate a time offset OFV2 by compar with addresses associated with timing symbols correspond ing a reference time value REFT2 with the counting value ing to the digital time information DCT. The symbol CV32, and may store the time offsets OFV1 and OFV2 in the memory 380 may output to the selection unit 320 the timing register 352. The comparator 354 may compare the time symbols designated by the addresses as the time to be offsets OFV1 and OFV2 with each other, and may provide displayed DT, in response to the addresses from the control the interrupt signal generator 355 with the digital code MC logic circuit 370. indicating a difference between the time offsets OFV1 and A configuration of the selection unit 320 may be substan OFV2. When the digital code MC indicates that the two tially the same as the configuration of the selection unit 220 25 consecutive time offsets OFV1 and OFV2 are different from of FIG. 4. each other, the interrupt signal generator 355 may maintain FIG. 14 is a block diagram illustrating an example of the the activation interval of an interrupt signal ITR1. For timer logic circuit in FIG. 13 according to an exemplary example, periods T1 and T21 of the interrupt signal ITR1 embodiment of the present inventive concept. may be the same as each other. When the digital code MC Referring to FIG. 14, the timer logic circuit 350 may 30 indicates that the two consecutive time offsets OFV1 and include a counter 351, an offset calculator 352, a register OFV2 are the same as each other, the interrupt signal 353, a comparator 354, an interrupt signal generator 355, generator 355 may increase the activation interval of an and an internal timer 357. interrupt signal ITR2. For example, a period T22 may be The counter 351 may count toggling numbers of the greater than a period T1 with respect to an interrupt signal internal vertical synchronization signal IVS during each 35 ITR2. time interval between current times CT(i) and CT(i+1) Therefore, the display device 20 may reduce power con which are consecutively received, and may output a count sumption because the DDI 300 determines whether the time ing value CV3 indicating the toggling numbers of the offsets are the same, and adaptively adjusts the activation internal vertical synchronization signal IVS during each period of the interrupt signal ITR to increase the receiving time interval. The offset calculator 352 may calculate a 40 period of the current time CT from the application processor difference of the counting value CV3 and each time interval 1OOb. between the current times CT(i) and CT(i+1) which are FIGS. 16 and 17 are flowcharts illustrating operation of consecutively received, and may output each time offset the display device of FIG. 11 according to an exemplary OFVito the register 353. The register 353 may store the time embodiment of the present inventive concept. offsets OFVi. The comparator 354 may compare two con 45 Hereinafter, an operation of the display device 20 of FIG. secutive time offsets of the time offsets OFVi stored in the 11 will be described in detail with reference to FIGS. 11 register 353, and may provide the interrupt signal generator through 17. 355 with a digital code indicating a difference between the The display device 20 is run (S210). When the display two consecutive time offsets. The interrupt signal generator device 20 is run, the application processor 100b and the DDI 355 may adaptively adjust an activation period of the 50 300 may be in operating state. When the DDI 300 does not interrupt signal ITR according to the digital code MC. For receive the image data RGB from the application processor example, when the digital code MC indicates that the two 100b for a predetermined time, a self clock display mode consecutive time offsets are Substantially the same as each may begin (S220). In this case, the application processor other, the interrupt signal generator 355 may increase the 100b and the DDI 300 may also be in the operating state. activation interval of the interrupt signal ITR. For another 55 The application processor 100b may enter into a sleep mode, example, when the digital code MC indicates that the two and the DDI 300 may enter into a self clock display mode consecutive time offsets are different from each other, the (S230). The application processor 100b may transmit (or interrupt signal generator 355 may maintain or decrease the update) the current time CT to the DDI 300 in response to activation interval of the interrupt signal ITR. The interrupt the interrupt signal ITR from the DDI 300. The DDI 300 signal generator 355 may activate the interrupt signal ITR 60 may calculate the time offset OFV based on the current time and may provide the activated interrupt signal ITR to the CT, and may store the time offset OFV in the register 353 application processor 100b regardless of the digital code MC (S240). After a predetermined time elapses, the application when the interrupt signal generator 355 receives the tem processor 100b may transmit (or update) a new current time perate signal TS which is activated. CT to the DDI 300 in response to the interrupt signal ITR The internal timer 357 may periodically generate the 65 from the DDI 300, and the DDI 300 may calculate a new digital time information DCT corresponding to the real time time offset OFV based on the new current time CT and may based on the internal clock signal ICLK, the current time CT, store the new time offset OFV in the register 353 (S250). US 9,626,896 B2 15 16 The comparator 354 may compare the time offsets with The display device 641 may be installed on the first each other and may provide the interrupt signal generator surface of the mobile device 600, and may display the results 355 with the digital code MC indicating the difference of the first sensing, the second sensing, and the third sensing. between the time offsets. The interrupt signal generator 355 FIG. 19 is a block diagram illustrating the mobile device may determine whether the time offsets are the same as each 5 of FIG. 18 according to an exemplary embodiment of the other based on the digital code MC (S260). When the time present inventive concept. offsets are the same as each other (OK in S260), the interrupt Referring to FIG. 19, the mobile device 600 may include signal generator 355 may increase the activation period of an application processor 610, a connectivity unit 620, a the interrupt signal ITR (S270). In an exemplary embodi memory device 630, a 3D image sensor 700, a 2D image 10 sensor 800, a user interface 640, and a power supply 650. ment, the interrupt signal generator 355 may provide the According to an exemplary embodiment of the present application processor 100b with information notifying that inventive concept, the mobile device 600 may be a prede the activation period of the interrupt signal ITR is increased. termined mobile system, Such as a mobile phone, a Smart When the time offsets are different from each other (NG in phone, a tablet PC, a laptop computer, a Personal Digital S260), the interrupt signal generator 355 may maintain the 15 Assistant (PDA), a Portable Multimedia Player (PMP), a activation period of the interrupt signal ITR, and the opera digital camera, a music player, a portable game console, a tion may return to the step (S240). When the data is not navigation system, or the like. received in the step (S270), the operation may return to the The application processor 610 may execute an operating step (S250), and the application processor 100b may exit system (OS) to operate the mobile device 600. In addition, from the sleep mode (S280). the application processor 610 may execute various applica FIG. 18 is a block diagram illustrating a mobile electronic tions to provide an internet browser, a game, and a dynamic apparatus according to an exemplary embodiment of the image. In addition, the application processor 610 may present inventive concept. include a single core or multi-cores. In addition, the appli Referring to FIG. 18, a mobile electronic apparatus 30 cation processor 610 may further include a cache memory may include a mobile device 600 and a display device 900. 25 positioned inside or outside the application processor 610. The mobile device 600 may be a smart phone, and the The connectivity unit 620 may communicate with exter display device 900 may be a watch-type wearable device nal devices. For example, the connectivity unit 620 can that operates in cooperation with the mobile device 600. perform Universal Serial Bus (USB) communication, Eth The display device 900 may employ the display device 10 ernet communication, Near Field Communication (NFC), of FIG. 1 or the display device 20 of FIG. 11, and may 30 Radio Frequency Identification (RFID) communication, mobile telecommunication or memory card communication. operate in a self clock display mode to reduce power For example, the connectivity unit 620 may include a consumption. The display device 900 may include the baseband chipset, and may support communications such as display panel 500 and the camera module 130. GSM, GPRS, WCDMA, HSxPA, or the like. The display device 900 may operate in cooperation with 35 The memory device 630 may store data processed by the the mobile device 600, and may display in the display panel application processor 610 or may operate as a working 500 messages or phone calls received by the mobile device memory. In addition, the memory device 630 may store a 600. In addition, the display device 900 may transmit images bottom image for booting the mobile device 600, a file captured by the camera module 130 to the mobile device system related to the operating system to operate the mobile 600. In addition, the display device 900 may run various 40 device 600, a device driver related to external devices applications independently from the mobile device 600. connected to the mobile device 600, and the applications The mobile device 600 may include a three-dimensional executed in the mobile device 600. For example, the (3D) image sensor 700, a two-dimensional (2D) image memory device 630 may include a volatile memory, such as sensor 800, and a display device 641. The mobile device 600 a Dynamic Random Access Memory (DRAM), a Static may further include a touch screen 644, buttons 643 and 645, 45 Random Access Memory (SRAM), a mobile DRAM, a a microphone 647, and a speaker 648. double data rate (DDR) synchronous DRAM (SDRAM), a The 3D image sensor 700 may be installed on a first low power DDR (LPDDR) SDRAM, a graphic DDR surface (e.g., a front surface) of the mobile device 600. The (GDDR) SDRAM, a Rambus DRAM (RDRAM), or the 3D image sensor 700 may perform a first sensing to detect like, or may include a nonvolatile memory, such as an a proximity of a Subject, and a second sensing to recognize 50 Electrically Erasable Programmable Read-Only Memory a gesture of the Subject by acquiring distance information for (EEPROM), a Flash Memory, a Phase Change Random the subject. The 3D image sensor 700 may include a sensing Access Memory (PRAM), a Resistance Random Access unit 710 having a plurality of depth pixels, and may include Memory (RRAM), a Nano Floating Gate Memory (NFGM), a light source unit 740 for emitting an infrared ray or a a Polymer Random Access Memory (PoRAM), a Magnetic near-infrared ray. 55 Random Access Memory (MRAM), a Ferroelectric Random The 2D image sensor 800 may be installed on the first Access Memory (FRAM), or the like. surface of the mobile device 600 and may perform a third The 3D image sensor 700 may perform the first sensing sensing to acquire color image information for the Subject. and the second sensing. The 2D image sensor 800 may The 2D image sensor 800 may include a second sensing unit perform the third sensing. 810 having a plurality of color pixels. 60 The user interface 640 may include at least one input In the exemplary embodiment illustrated in FIG. 19, the device, such as a keypad, the buttons 643 and 645, or the 3D image sensor 700 and the 2D image sensor 800 may be touch screen 644, and/or at least one output device. Such as prepared as two integrated circuit chips separated from each the speaker 648 or the display device 641. The power supply other. For example, the mobile device 600 may include two 650 may supply an operating Voltage to the mobile system sensing modules. In this case, the depth pixels and the color 65 600. pixels may constitute two pixel arrays separated from each The mobile device 600 or components of the mobile other. device 600 may be mounted by using various types of US 9,626,896 B2 17 18 packages, such as Package on Package (PoP), Ball grid a register configured to store the time offset; and arrays (BGAs), Chip scale packages (CSPs), Plastic Leaded an internal timer configured to output the digital time Chip Carrier (PLCC), Plastic Dual In-Line Package (PDIP), information based on the internal clock signal, the Die in Waffle Pack, Die in Wafer Form, Chip On Board current time, and the time offset stored in the register. (COB), Ceramic Dual In-Line Package (CERDIP), Plastic 5 5. The display device of claim 4, wherein the internal Metric Quad Flat Pack (MQFP), Thin Quad Flat-Pack timer includes: (TQFP), Small Outline Integrated Circuit (SOIC), Shrink a counter configured to count the internal clock signal, Small Outline Package (SSOP). Thin Small Outline Package and to output a counting value; and (TSOP). Thin Quad Flat-Pack (TQFP), System. In Package a time adjuster configured to receive the current time and (SIP), Multi Chip Package (MCP), Wafer-level Fabricated 10 the time offset, to adjust the current time based on the Package (WFP), Wafer-Level Processed Stack Package counting value and the time offset, and to provide the (WSP), or the like. digital time information. According to an exemplary embodiment of the present 6. The display device of claim 4, wherein the DDI further inventive concept, the DDI may reduce power consumption includes: by cutting off interfacing with the application processor in a 15 a symbol memory configured to store a plurality of timing self clock display mode because the DDI calculates for itself symbols that are used for displaying the time to be the time to be displayed based on the current time and the displayed; and time offset corresponding to a difference between a real time a control logic circuit configured to control the symbol and an internal clock signal, and displays the time to be memory such that, among the plurality of timing sym displayed in a display panel in the self clock display mode. bols, timing symbols associated with the time to be The present inventive concept may be applied to a mobile displayed are output. phone, a smart phone, a PDA, and a PMP. 7. The display device of claim 1, wherein the DDI further The foregoing is illustrative of exemplary embodiments, includes a selection circuit configured to select one of the and the present inventive concept should not be construed as image signal and the time to be displayed, and to provide the limited the exemplary embodiments thereof. Although a few 25 selected one of the image signal or the time to be displayed exemplary embodiments have been described, those skilled to a timing controller in response to a mode change signal, in the art will readily appreciate that many modifications are and possible in the exemplary embodiments without materially wherein the mode change signal is one of the self clock departing from the spirit and scopes of the present inventive display mode and a video mode, and the image signal concept. Accordingly, all Such modifications are intended to 30 provided from the application processor is displayed in be included within the scope of the present inventive con the vide mode. cept as defined in the claims. 8. The display device of claim 1, wherein the application What is claimed is: processor includes: 1. A display device comprising: an offset calculator configured to calculate the real time a display driver integrated circuit (DDI) configured to 35 and the time offset based on the synchronization signal; provide an internal synchronization signal based on an and internal clock signal as a synchronization signal; a real time generator configured to generate the real time. a display panel; and 9. The display device of claim 1, wherein the application an application processor configured to calculate a time processor is connected to the DDI through a high speed offset corresponding to a difference between a real time 40 serial interface (HSSI), and wherein the application proces and the internal synchronization signal, and to provide sor is configured to enter into a sleep mode in the self clock the time offset to the DDI, display mode. wherein the DDI is configured to calculate a time to be 10. The display device of claim 1, wherein the time to be displayed based on the time offset and a current time displayed is an actual clock time in ante meridiem or post provided from the application processor, and to display 45 meridiem. the time to be displayed in the display panel in a self 11. A display device comprising: clock display mode during which the application pro an application processor configured to provide a current cessor does not transmit an image signal. time indicating a real time in response to an interrupt 2. The display device of claim 1, wherein the DDI signal; comprises: 50 a display panel; and an oscillator configured to generate the internal clock a display driver integrated circuit (DDI) configured to signal; provide an internal synchronization signal based on an an internal synchronization signal generator configured to internal clock signal, to adjust a period of the interrupt generate an internal horizontal synchronization signal signal that is provided to the application processor and an internal vertical synchronization signal based on 55 based on time offsets, to calculate a time to be dis the internal clock signal; and played based on the current time, and to display the a timer logic circuit configured to generate digital time time to be displayed in the display panel, information corresponding to the time to be displayed wherein each of the time offsets is calculated based on the based on the time offset, the internal clock signal, and current time and the internal synchronization signal. the current time. 60 12. The display device of claim 11, wherein the DDI 3. The display device of claim 2, wherein the DDI further comprises: includes an interface configured to provide the application an oscillator configured to generate the internal clock processor with one of the internal horizontal synchronization signal; signal and the internal vertical synchronization signal as the an internal synchronization signal generator configured to synchronization signal. 65 generate an internal horizontal synchronization signal 4. The display device of claim 2, wherein the timer logic and an internal vertical synchronization signal based on circuit includes: the internal clock signal; and US 9,626,896 B2 19 20 a timer logic circuit configured to generate digital time an application processor including a real time generator information corresponding to the time to be displayed configured to generate a real time; and based on the internal synchronization signal, the inter a display driver integrated circuit (DDI) connected to the nal clock signal, and the current time, and application processor through a high speed serial inter wherein the internal synchronization signal is one of the face (HSSI), and the DDI configured to provide an internal horizontal synchronization signal and the inter internal synchronization signal based on an internal nal vertical synchronization signal. clock signal, 13. The display device of claim 12, wherein the timer wherein the DDI is configured to calculate a time to be logic circuit includes: displayed based on a time offset corresponding to a a register configured to store the time offsets: 10 difference between a current time provided from the a comparator configured to calculate a difference between application processor and the internal synchronization two consecutive time offsets among the time offsets, signal, and to display the time to be displayed in a and to output a digital code corresponding to the display panel in a self clock display mode during which difference between the two consecutive time offsets; the application processor does not transmit an image and 15 signal. an interrupt signal generator configured to adjust an 19. The mobile electronic apparatus of claim 18, wherein activation period of the interrupt signal, in response to the mobile device includes a smartphone, and the display the digital code. device includes a watch-typed wearable device. 14. The display device of claim 13, wherein the interrupt 20. The mobile electronic apparatus of claim 18, wherein signal generator is configured to increase the activation the DDI comprises: period of the interrupt signal in response to the digital code an oscillator configured to generate the internal clock when there is no difference between the two consecutive signal; time offsets. an internal synchronization signal generator configured to 15. The display device of claim 13, wherein the interrupt generate an internal horizontal synchronization signal signal generator is configured to maintain the activation 25 and an internal vertical synchronization signal based on period of the interrupt signal in response to the digital code the internal clock signal; and when there is a difference between the two consecutive time a timer logic circuit configured to generate digital time offsets. information corresponding to the time to be displayed 16. The display device of claim 13, wherein the DDI based on the time offset, the internal clock signal, and further includes a temperature sensor configured to sense an 30 the current time. operating temperature of the DDI, 21. The mobile electronic apparatus of claim 18, wherein wherein the temperature sensor is configured to provide the DDI comprises: the interrupt signal generator with a temperature signal an oscillator configured to generate the internal clock that is activated when the sensed operating temperature signal; is out of a reference time range, and 35 an internal synchronization signal generator configured to wherein the interrupt signal generator is configured to generate an internal horizontal synchronization signal provide the interrupt signal to the application processor and an internal vertical synchronization signal based on in response to the temperature signal. the internal clock signal; and 17. The display device of claim 11, wherein the applica a timer logic circuit configured to generate digital time tion processor is configured to enter into a sleep mode after 40 information corresponding to the time to be displayed the application processor transmits the current time to the based on the internal synchronization signal, the inter DDI in response to the interrupt signal. nal clock signal, and the current time, and 18. A mobile electronic apparatus comprising: wherein the internal synchronization signal is one of the a mobile device; and internal horizontal synchronization signal and the inter a display device configured to operate in cooperation with 45 nal vertical synchronization signal. the mobile device, the display device including: