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TU Wien Aktuelle Speichertechnologien (RAM)

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TU Wien Aktuelle Speichertechnologien (RAM) TU Wien Embedded Computing Systems Institut fur¨ Technische Informatik Mark Volcic 0425294 033/535 Aktuelle Speichertechnologien (RAM) Bakkalaureatsarbeit Im Rahmen der LVA SE Seminar mit Bakkalaureatsarbeit Betreuung: Andreas Steininger Wien, 1. Juni 2007 1 Inhaltsverzeichnis Abbildungsverzeichnis 4 Tabellenverzeichnis 6 1 Ubersicht¨ 7 2 Begriffserkl¨arung 8 2.1 random access – read only . 8 2.1.1 RAM – random access memory . 8 2.1.2 ROM – read only memory . 8 2.2 volatile – non volatile . 8 2.2.1 volatile memory . 8 2.2.2 non-volatile memory . 9 2.3 Latenzzeit versus Datendurchsatz . 9 3 DRAM – Klein und billig 11 3.1 Allgemeines . 11 3.2 Aufbau und Funktionsweise . 11 3.2.1 1-Bit-Speicherzelle . 11 3.2.2 Speichermatrix . 12 3.2.3 Lesen und Schreiben . 13 3.2.4 Refresh . 15 3.2.5 Zusammenfassung . 15 3.3 Technologien . 16 3.3.1 FPM-DRAM – Fast Page Mode DRAM . 16 Burst-Mode . 16 Beispiel . 16 Interleaving . 17 3.3.2 EDO-DRAM – Extended Data Out DRAM . 17 Beispiel . 18 3.3.3 Burst EDO . 18 3.3.4 SDRAM – Synchronous DRAM . 19 Beispiel . 20 Read-Timing . 20 Write-Timing . 20 3.3.5 RDRAM – Rambus DRAM . 21 3.3.6 DDR-SDRAM – Double Data Rate SDRAM . 22 Pins und Symbole . 22 Read-Timing . 23 Write-Timing . 24 Inhaltsverzeichnis 2 3.3.7 DDR2-SDRAM . 24 Terminierung . 25 Pins und Symbole . 26 Read-Timing . 26 Write-Timing . 27 3.3.8 DDR3-SDRAM . 28 3.4 Anwendungen . 29 3.4.1 Embedded DRAM . 29 3.5 Zusammenfassung . 29 3.5.1 Vorteile . 29 3.5.2 Nachteile . 29 Gegenuberstellung¨ . 30 4 SRAM – Schnell und teuer 32 4.1 Allgemeines . 32 4.2 Aufbau und Funktionsweise . 32 4.2.1 6T-SRAM . 32 4.2.2 Lesen und Schreiben . 33 Standby . 33 Lesen . 33 Schreiben . 35 4.2.3 4T-SRAM . 36 4.2.4 1T-SRAM . 36 Lesen . 38 Schreiben . 38 Dual Port SRAM . 39 Multi Port SRAM . 40 4.2.5 Speichermatrix . 41 4.3 Technologien . 41 4.3.1 ASRAM – Asynchronous SRAM . 41 4.3.2 SSRAM – Synchronous SRAM . 42 Burst SRAM . 43 Pipelined Burst SRAM . 43 Zero Bus Turn-around SRAM – ZTB SRAM . 44 Double Date Rate SRAM – DDR SRAM . 44 Quad Data Rate SRAM – QDR-SRAM . 45 Quad Data Rate II SRAM – QDRII-SRAM . 47 4.4 Anwendungen . 48 4.4.1 Cache . 48 Funktionsweise . 48 4.5 Zusammenfassung . 49 5 MRAM – Speicher der Zukunft? 50 5.1 Aufbau und Funktionsweise . 50 5.1.1 Lesen . 52 Twin Cell Method . 52 Reference Cell Method . 52 Self-Referenced Method . 53 Inhaltsverzeichnis 3 5.1.2 Schreiben . 53 5.2 Speichermatrix . 54 5.2.1 XPT – Crosspoint . 54 Lesen . 54 Schreiben . 55 5.2.2 1T1MTJ - 1 Transistor 1 Magnetic Tunnel Junction . 55 Lesen . 56 Schreiben . 57 5.3 Zusammenfassung . 58 6 VRAM – Video Random Access Memory 59 6.1 Aufbau und Funktionsweise . 59 6.2 Weiterentwicklungen . 60 6.2.1 WRAM – Window RAM . 60 6.2.2 SGRAM – Synchronous Graphics RAM . 60 DDR-SGRAM – Double Data Rate Synchronous Graphics RAM . 61 Beispiel - Vergleich von SGRAM und DDR-SGRAM . 61 6.2.3 MDRAM – Multibank DRAM . 61 6.2.4 CDRAM – Cache DRAM . 62 6.2.5 IDRAM – Integrated DRAM . 62 6.2.6 3DRAM – 3 Dimenisonal RAM . 62 6.2.7 GDDR-SDRAM – Graphics Double Data Rate SDRAM . 63 Lesen . 63 Schreiben . 64 6.2.8 GDDR2-SDRAM . 64 6.2.9 GDDR3-SDRAM . 65 6.2.10 GDDR4-SDRAM . 65 6.3 Zusammenfassung . 66 7 Zusammenfassung 67 Literaturverzeichnis 68 4 Abbildungsverzeichnis 1.1 Uberblick¨ der unterschiedlichen Speichertypen . 7 2.1 Verdeutlichung der Latenzzeiten [16] . 9 3.1 Aufbau einer DRAM-Speicherzelle . 11 3.2 Blockdiagramm eines DRAMS . 12 3.3 Aufbau einer Speichermatrix [9] . 13 3.4 Timing-Diagramm eines Lesezyklus [9] . 15 3.5 Timing-Diagramm eines FPM-DRAMs im Burst-Mode [8] . 17 3.6 Timing-Diagramm eines EDO-DRAMs im Burst-Mode [8] . 18 3.7 Timing-Diagramm eines BEDO-DRAMs im Burst-Mode [8] . 19 3.8 SDRAM: Timing-Diagramm (Lesen) [29] . 20 3.9 SDRAM: Timing-Diagramm (Schreiben) [29] . 21 3.10 DDR-SDRAM: Timing-Diagramm (Lesen) [16] . 23 3.11 DDR-SDRAM: Timing-Diagramm (Schreiben) [16] . 24 3.12 Terminierung – DDR- und DDR2-SDRAM [5] . 25 3.13 Terminierung – DDR- und DDR2-SDRAM [5] . 26 3.14 DDR2-SDRAM: Timing-Diagramm (Lesen) [25] . 27 3.15 DDR2-SDRAM: Lesen - Beispiel [25] . 27 3.16 DDR2-SDRAM: Timing-Diagramm (Schreiben) [25] . 28 3.17 DDR2-SDRAM: Schreiben - Beispiel [25] . 28 3.18 Uberblick¨ der DDR-Technologien und deren Markteinfuhrung¨ [28] 31 4.1 Aufbau einer SRAM-Speicherzelle [51] . 33 4.2 Blockdiagramm [43] . 33 4.3 Lesen einer SRAM-Speicherzelle [32] . 34 4.4 6T-SRAM-Speicherzelle mit Sense-Amplifier [32] . 35 4.5 SRAM mit Widerst¨anden [51] . 36 4.6 Aufbau einer 1T-SRAM-Speicherzelle [32] . 37 4.7 Dual Port RAM mit Intel 8086 Prozessor [39] . 39 4.8 Dual Ported RAM [43] . 40 4.9 SRAM-Speichermatrix [43] . 41 4.10 Blockdiagramm eines ASRAM [35] . 42 4.11 Blockdiagramm eines SSRAM [35] . 42 4.12 Timing-Diagramm eines synchronen SRAM [35] . 43 4.13 Timing-Diagramm eines synchronen SRAM im Burst-Mode [35] . 43 4.14 Timing-Diagramme im Vergleich (Pipelined SRAM, synchrones SRAM) [35] . 43 4.15 Timing-Diagramm eines DDR-SRAMs [18] . 44 Abbildungsverzeichnis 5 4.16 Lesen und Schreiben im Vergleich – (a) Standard-SRAM; (b) QDR- SRAM [3] . 45 4.17 Blockdiagramm eines QDR-SRAM [3] . 46 4.18 Timing-Diagramm eines QDR-SRAM (Burst 2) [12] . 46 4.19 Vergleich der Geschwindigkeiten diverser SRAM-Technologien [12] 47 4.20 Timing-Diagramm eines QDRII-SRAM (Burst 4) [38] . 47 4.21 Interner Aufbau eines PC-Speicher-Systems [35] . 48 4.22 Schematischer Aufbau – Prozessor und Cache [18] . 48 4.23 Samsung QDR SRAM Roadmap [40].
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