10 Gigabit Ethernet Switch Subsystem User Guide for Keystone II Devices

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10 Gigabit Ethernet Switch Subsystem User Guide for Keystone II Devices

KeyStone II Architecture 10 Gigabit Ethernet Subsystem User Guide Literature Number: SPRUHJ5 February 2013 www.ti.com Release History Release Date Description/Comments SPRUHJ5 February 2013 Initial Release. ø-ii KeyStone II Architecture 10 Gigabit Ethernet Subsystem User Guide SPRUHJ5—February 2013 Submit Documentation Feedback www.ti.com Contents Contents Release History. ø-ii List of Tables . ø-ix List of Figures . .ø-xiv List of Procedures . .ø-xviii Preface ø-xix About This Manual. ø-xix Notational Conventions. ø-xix Related Documentation from Texas Instruments . ø-xx Trademarks. ø-xx Chapter 1 Introduction 1-1 1.1 Purpose of the Peripheral . 1-2 1.2 Features . 1-2 1.3 10 Gigabit Ethernet Subsystem Functional Block Diagram. 1-3 1.4 3-Port 10GbE Switch Sub-Module Functional Block Diagram . 1-4 1.5 Industry Standard(s) Compliance Statement . 1-5 Chapter 2 Architecture 2-1 2.1 Clock Control . 2-2 2.1.1 10GbE Subsystem Clock & SerDes Configuration Clock . .2-2 2.1.2 SerDes Clock Domain . .2-2 2.1.3 MDIO Clock . .2-2 2.1.4 CPTS reference clock . .2-2 2.1.5 MAC-MII Clocks . .2-2 2.2 Memory Map . 2-3 2.3 Packet DMA Architecture. 2-3 2.4 10 Gigabit Ethernet Switch Architecture . 2-4 2.4.1 Streaming Packet Interface . .2-5 2.4.1.1 Transmit Streaming Packet Interface . .2-5 2.4.1.2 Transmit VLAN Processing . .2-6 2.4.1.3 Receive Streaming Packet Interface . .2-6 2.4.2 Media Access Controller Module Architecture. .2-7 2.4.2.1 Data Receive Operations. .2-7 2.4.2.2 Data Transmission . .2-9 2.4.3 MAC FIFO Architecture . .2-12 2.4.4 Statistics Module Architecture . .2-13 2.4.4.1 Accessing Statistics Registers . .2-13 2.4.4.2 Statistics Interrupts . .2-13 2.4.4.3 Receive Statistics Descriptions . .2-13 2.4.4.4 Transmit (only) Statistics Descriptions . .2-18 2.4.4.5 Receive and Transmit (shared) Statistics Descriptions . .2-21 2.4.5 Time Synchronization Module Architecture . .2-23 2.4.5.1 Time Synchronization Submodule Components . .2-24 2.4.5.2 Time Synchronization Events . .2-25 2.4.5.3 Time Synchronization Initialization. .2-31 2.4.5.4 Detecting and Processing Time Synchronization Events. .2-32 2.4.6 Address Lookup Engine (ALE) Module Architecture . .2-32 2.4.6.1 ALE Table . .2-34 SPRUHJ5—February 2013 KeyStone II Architecture 10 Gigabit Ethernet Subsystem User Guide ø-iii Submit Documentation Feedback Contents www.ti.com 2.4.6.2 Reading Entries from the ALE Table . .2-34 2.4.6.3 Writing Entries to the ALE Table. .2-34 2.4.6.4 ALE Table Entry Types . .2-35 2.4.6.5 ALE Packet Forwarding Process . .2-39 2.4.6.6 ALE Learning Process . .2-44 2.4.7 10GbE Additional Features . ..

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