IGEP TM V2 HARDWARE REFERENCE MANUAL

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IGEP TM v2

HARDWARE REFERENCE

MANUAL

Document: MAN-PR-IGEP0020-RCx Revision: 2.0 Date: February 6, 2013

IGEPTM v2 Hardware Reference Manual

Table of contents

Table of contents ...... 2 1 COPYRIGHT NOTICE ...... 4 2 WARRANTY ...... 4 3 ORDERING INFORMATION ...... 5 4 OVERVIEW ...... 6 4.1 ABOUT THIS MANUAL ...... 6 4.2 IGEP™ v2 DESCRIPTION ...... 6 4.3 IGEPTM v2 FEATURES ...... 8 4.4 IGEP™ v2 BLOCK DIAGRAM ...... 11 4.5 GENERAL VIEW ...... 12 5 ON-BOARD DEVICES & INTERFACES ...... 14 5.1 SUMMARY ...... 14 5.2 IGEP™ v2 CONNECTORS MAP ...... 15 5.3 OMAP PROCESSOR ...... 16 5.4 MEMORY ...... 16 5.5 POWER MANAGEMENT ...... 16 5.6 WIFI/BLUETOOTH INTERFACE ...... 17 5.6.1 BLOCK DIAGRAM ...... 17 5.6.2 INTERFACES ...... 17 5.6.3 POWER-ON RESET SEQUENCE FOR WLAN ...... 18 5.6.4 WLAN RESET/PDN PINS...... 19 5.6.5 BLUETOOTH RESET PINS ...... 19 5.6.6 PCM INTERFACE ...... 20 5.6.7 IGEP™ v2 ANTENNAS (INTERNAL/EXTERNAL - UD11, JD21, JD22) ...... 20 5.7 MAIN 5Vdc POWER: J200 ...... 24 5.8 JTAG DEBUG: J400 ...... 24 5.9 RS485: J940 ...... 26 5.10 SERIAL PORT DEBUG (+ EXTRA RS232) J960 ...... 28 5.10.1 DEBUG CABLE MODIFICATIONS (ONLY REV C) ...... 29 5.10.2 NEW FEATURES ON REV C ...... 30 5.10.3 HOW TO USE UART 1 ...... 31 5.11 KEYBOARD MATRIX 4x4: J970 ...... 32 5.12 TFT INTERFACE CONNECTORS: JA41 & JA42...... 34

DOCUMENT FROM ISEE 2007 S.L. Ref: MAN-PR-IGEP0020-RCx 2

IGEPTM v2 Hardware Reference Manual

5.12.1 CONNECTOR JA41 ...... 34 5.12.2 CONNECTOR JA42 ...... 37 5.12.3 CONNECTORs JA41-JA42 COUNTERPARTs ...... 38 5.13 ANALOG TO DIGITAL CONVERTER: JC20 & JC21 ...... 39 5.14 CAMERA INTERFACE: JC30...... 41 5.15 S-VIDEO SIGNALS: TP400 & TP401 ...... 43 5.16 RTC BACKUP BATTERY...... 44 5.17 USB 2.0 OTG: J830 ...... 47 5.18 USB 2.0 HOST: J800...... 48 5.19 ETHERNET: JB01 ...... 49 5.20 AUDIO: J650 & J640 ...... 50 5.21 DVI-D INTERFACE: JA01 ...... 53 5.22 MICRO-SD: J900...... 54 5.23 LED INDICATORS: D240 & D440 ...... 54 6 EXPANSION CONNECTOR J990: GPIO ...... 55 6.1 PINOUT TABLE OF EXPANSION CONNECTOR...... 58 7 EXPANDING IGEP™ v2 CAPABILITIES ...... 59 7.1 IGEP™ v2 EXPANSION BOARD ...... 59 7.2 IGEP™ RADAR LAMBDA...... 60 8 MECHANICAL SPECIFICATIONS ...... 61 9 ELECTRICAL CHARACTERISTICS ...... 62 10 LIST OF TABLES...... 64 11 LIST OF FIGURES ...... 64 12 KNOWN ISSUES ...... 66 13 TROUBLESHOOTING ...... 66 14 CHANGE HISTORY ...... 66

DOCUMENT FROM ISEE 2007 S.L. Ref: MAN-PR-IGEP0020-RCx 3

IGEPTM v2 Hardware Reference Manual

1 COPYRIGHT NOTICE

This document is copyrighted, 2011, by ISEE 2007 SL. All rights are reserved. ISEE reserves the right to make improvements to the products described in this manual at any time without notice. No part of this manual may be reproduced, copied, translated or transmitted in any form or by any means without the prior written permission of the original manufacturer. Information provided in this manual is intended to be accurate and reliable. However, the original manufacturer assumes no responsibility for its use, nor for any infringements upon the rights of third parties which may result from its use.

2 WARRANTY

THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE.

The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user indemnifies ISEE 2007 SL from all claims arising from the handling or use of the goods. Due to the open construction of the product, it is the user’s responsibility to take any and all appropriate precautions with regard to electrostatic discharge.

EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.

ISEE 2007 SL currently deals with a variety of customers for products, and therefore our arrangement with the user is not exclusive. ISEE assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein.

Please read specifically, the Warnings and Restrictions notice in this manual prior to handling the product. This notice contains important safety information about temperatures and voltages. For additional information on IGEP™ environmental and/or safety programs, please contact with ISEE ([email protected]).

No license is granted under any patent right or other intellectual property right of ISEE covering or relating to any machine, process, or combination in which such ISEE products or services might be or are used.

NOTE: It could be found a detailed warranty and sales conditions of IGEP™ on ISEE website: http://www.isee.biz

DOCUMENT FROM ISEE 2007 S.L. Ref: MAN-PR-IGEP0020-RCx 4

IGEPTM v2 Hardware Reference Manual

3 ORDERING INFORMATION

IGEP™ Device Orderable #PN Marking

IGEP™ v2 IGEP0020-RCx Datamatrix code label with “IGEP0020-RCx” Table 1 Ordering information

DOCUMENT FROM ISEE 2007 S.L. Ref: MAN-PR-IGEP0020-RCx 5

IGEPTM v2 Hardware Reference Manual

4 OVERVIEW

4.1 ABOUT THIS MANUAL

This manual describes IGEP™ v2 hardware features. IGEP™ v2 is an IGEP™ technology device from ISEE. You can find additional information at our website www.iseebcn.com

The “4 OVERVIEW” chapter describes general features of this base board and show the block diagram. The “5 ON-BOARD DEVICES & INTERFACES” chapter describes in more detail each device and interface connectors included on this product. “6 EXPANSION CONNECTOR J990: GPIO” chapter describes in detail the function of each pin of the expansion connector included on the board. 8 MECHANICAL SPECIFICATIONS chapter describes the mechanical characteristics of the product and finally chapter 9 ELECTRICAL CHARACTERISTICS show a table with the electrical specifications of the product.

At the end of this document you will find a list of tables, figures and change log. You will find these elements in chapters: “10 LIST OF TABLES”, “11 LIST OF FIGURES”, ”12 KNOWN ISSUES”, ”13 TROUBLESHOOTING” and “14 CHANGE HISTORY”.

4.2 IGEP™ v2 DESCRIPTION IGEP™ v2 is an embedded processor development board based on Texas Instruments OMAP3530/DM3730 processor.

Texas Instruments OMAP3530/DM3730 processor @720MHz/1GHz

o DSP TMS320DM-C64+ 500 MHz / 800 MHz

o NEON SIMD Coprocessor o Video Acceleration

o Camera Interface

RAM 512 MBytes LPDDR SDRAM – 200 MHz

NAND Flash 512 Mbytes On board micro-SD socket

Debug RS232 & JTAG

Connection to single +5V power supply.

Designed for industrial and commercial purposes.

USB OTG 2.0 on mini AB connector USB HOST 2.0 HS

DOCUMENT FROM ISEE 2007 S.L. Ref: MAN-PR-IGEP0020-RCx 6

IGEPTM v2 Hardware Reference Manual

Ethernet 10/100 Mb Base T on RJ45 Ports (x2) Audio Stereo Input Jack & Output Jack Wi-Fi & Bluetooth DVI Video Output TFT Interface 24 bit

Optional RTC Battery Backup for TPS65950 (Super Capacitor or Rechargeable Battery). Optional 3Msps ADC LED Indicators

Size: 93x64mm

Non-populated parts: o J400 JTAG connector o J990: GPIO expansion connector o J970: 4x4 keyboard connector o JD22: External wifi antenna connector o JA41 and JA42: TFT interface o JC30: Camera interface o UC20 3MBps ADC + JC21 Hirose connector o Super Capacitor or Rechargeable Battery.

IGEP™ v2 Top View IGEP™ v2 Bottom View Bottom 3D View Bottom 3D View

Figure 1 IGEP™ v2 View

Contact ISEE sales for custom assembly boards for fully previous IGEP™ v2 revision B compatible (mechanical, electrical and logical) on IGEP0020-RCx PCBs.

DOCUMENT FROM ISEE 2007 S.L. Ref: MAN-PR-IGEP0020-RCx 7

IGEPTM v2 Hardware Reference Manual

4.3 IGEPTM v2 FEATURES

Figure 2 IGEP™ v2 GENERAL VIEW

Feature Specifications

ARM CPU Texas Instruments OMAP3530/DM3730 720MHz/1GHz L1 cache: 112 KB (DSP), 64 KB (ARM) L2 cache: 96 KB (DSP), 256 KB (ARM) NEON SIMD Coprocessor DMA, Interrupt controllers, Timers

DSP TMS320DM-C64+ 500 Mhz / 800 Mhz

2D/3D graphics Power VR SGX 530 (100/200 Mhz) providing 2D/3D graphics acceleration acceleration with OpenGL ES 1.0, OpenGL ES 2.0 and OpenVG support.

Video acceleration IVA2.2 Subsystem TMS320C64+ DSP core running at rate up to 520MHz. Supporting H.264, H.263, MPEG-4, MPEG-2, JPEG, WMV9 and additional codecs.

Camera Interface Camera ISP processing capability to connect RAW image sensor modules Table 2 Processor

DOCUMENT FROM ISEE 2007 S.L. Ref: MAN-PR-IGEP0020-RCx 8

IGEPTM v2 Hardware Reference Manual

Feature Specifications

RAM Memory 512 MBytes LPDDR SDRAM – 200 Mhz

Storage NAND Flash 512 Mbytes On board micro-SD socket Table 3 Memory and Storage

Feature Specifications

Debug Console RS232 + JTAG Interface

Indicators 2 Bicolor USER LEDS

USB 2.0 LS/FS/HS OTG 1 Mini AB USB socket connector (dual slave and host role)

USB 2.0 HS HOST 1 Type A USB socket connector (standard USB host)

Audio stereo in/out 3.5mm standard stereo audio jack

microSD microSD connector (SD and SDHC cards supported)

DVI video output DVI-D using HDMI connector. (video and TS lines are available in expansion connector also).

Ethernet 10/100 MB BaseT (RJ45 connector with led link/activity)

Expansion connector Power 5V and 1.8V, UART, McBSP, McSPI, I2C, GPIO, RS485 with transceiver, Keyboard.

Table 4 On-board connectors and devices

Feature Specifications

Wifi IEEE 802.11b/g 2,4GHz

Bluetooth 2.0

Antenna WiFi/Bluetooth 1 shared internal antenna (integrated on PCB), optional external antenna. 1 x HIROSE UL connector Table 5 Wireless connectivity

DOCUMENT FROM ISEE 2007 S.L. Ref: MAN-PR-IGEP0020-RCx 9

IGEPTM v2 Hardware Reference Manual

Feature Specifications

Power 5Vcc / 1A (Without USB) – 5Vcc / 1.3A (With USB) 3.5mm socket connector for wall plug or JST Connector

Power from expansion Supply Voltage from 5V and 1.8V connectors

Power Management TPS65950

Table 6 Power

Feature Specifications

Temperature Range Commercial ( 0 to 70 Cº) and Industrial range (-40 to +85 Cº Degrees) are available (Contact ISEE sales)

PCB size 93 x 64 x 1.6 mm

Table 7 Mechanical and environmental

WARNING: IGEP™ v2 BOARD CAN ONLY BE POWERED WITH +5Vdc POWER SUPPLY, OTHERWISE THE BOARD WILL BE PERMANENT DAMAGED!

DOCUMENT FROM ISEE 2007 S.L. Ref: MAN-PR-IGEP0020-RCx 10

IGEPTM v2 Hardware Reference Manual

4.4 IGEP™ v2 BLOCK DIAGRAM

Figure 3 IGEP™ v2 revision C Block Diagram

DOCUMENT FROM ISEE 2007 S.L. Ref: MAN-PR-IGEP0020-RCx 11

IGEPTM v2 Hardware Reference Manual

4.5 GENERAL VIEW

Figure 4 IGEP™ v2 revision C board top side components

DOCUMENT FROM ISEE 2007 S.L. Ref: MAN-PR-IGEP0020-RCx 12

IGEPTM v2 Hardware Reference Manual

Figure 5 IGEP™ v2 revision C board bottom side components

DOCUMENT FROM ISEE 2007 S.L. Ref: MAN-PR-IGEP0020-RCx 13

IGEPTM v2 Hardware Reference Manual

5 ON-BOARD DEVICES & INTERFACES

5.1 SUMMARY DEVICE CONNECTOR TYPE REF: INTERFACE/COMMENTS OMAP PROCESSOR - - http://focus.ti.com MEMORY POP TECHNIQUE - NAND Flash 512 MB 512 MB LPDDR SDRAM 200 MHz POWER Management p/n: TPS65950 - http://focus.ti.com WIFI 802.11b/g SMD COAXIAL JD22(*) OPTIONAL EXTERNAL ANTENNA p/n: U.FL-R-SMT-1 (coaxial co nne cto r) BLUETOOTH SMD COAXIAL JD22(*) OPTIONAL EXTERNAL ANTENNA p/n: U.FL-R-SMT-1 (coaxial co nne cto r) MAIN POWER p/n: RASM722BK J200/J940(*) +5Vdc / 1A JTAG DEBUG TSM-2x7; 2.54mm pitch J400(*) JTAG / DEBUG RS485 HEADER 5 PIN 2mm pitch J940(*) UART1 + TRANSCEIVER p/n:S5B-PH-SM3-TB SERIAL DEBUG HEADER 2x5; 2,54mm pitch J960 UART3 + UART1 + TRANSCEIVER KEYBOARD MATRIX 8 pin; 2.54mm pitch J970(*) Keyboard matrix 4x4 TFT INTERFACE 2x14pin; 1,27mm pitch JA41(*) DSS_DATA0:23 TFT INTERFACE-II 2x10pin; 1,27mm pitch JA42(*) LCD SYNC, TOUCHSCREEN, ETC ANALOG to DIGITAL JC20: U.FL-R-SMT-1; JC20(*)/JC21(*) OPTIONAL ANALOG INPUT TO CONVERTER (*) JC21: 2pin 2,54mm pitch ADC. CAMERA INTERFACE 2x14pin; 1,27mm pitch JC30(*) CAM_D0:D11 + others S-VIDEO TEST POINTS TP400 / TP401 S-VIDEO RTC Battery Back Up p/n: VL1220 BT741(*)/C741(*) OPTIONAL RTC BACKUP BATTERY USB 2.0 OTG USB mini AB J830 HSUSB USB 2.0 HOST USB Type A socket J800 USB1HS ETHERNET RJ45 JB01 GPMC_D0:D15 AUDIO 3.5mm Jack J650 / J640 HSO/AUX DVI-D INTERFACE DVI-D JA01 DSS_DATA0:23 MICRO SD Micro SD Socket J900 MMC1_DAT0:3 LED INDICATORS 2Xbicolor LED D440/D240 GPIO26, GPIO27, GPIO28 EXPANSION 2x14pin; 2,54mm pitch J990(*) Multiplexed: GPIOs, UART2, CONNECTOR MMC2, McBSP3, McSPI, I2C) Table 8 IGEP™ v2 Interface summary (*) THESE DEVICES and/or CONNECTORS ARE NOT POPULATED BY DEFAULT

DOCUMENT FROM ISEE 2007 S.L. Ref: MAN-PR-IGEP0020-RCx 14

IGEPTM v2 Hardware Reference Manual

5.2 IGEP™ v2 CONNECTORS MAP

Figure 6 IGEP™ v2 revision C CONNECTORS MAP

DOCUMENT FROM ISEE 2007 S.L. Ref: MAN-PR-IGEP0020-RCx 15

IGEPTM v2 Hardware Reference Manual

5.3 OMAP PROCESSOR IGEP™ v2 BOARD uses OMAP3530 (version ES3.1) or DM3730 as core processor and comes in a 0.4mm pitch memory POP package on it.

POP (Package on Package) is a technique where the memory, NAND and SDRAM, are mounted on top of the OMAP3530 or DM3730. For this reason, when looking at the IGEP™ v2 BOARD, you will not find an actual part labeled OMAP3530 or DM3730.

Figure 7 POP Package For accurate information on this processor, revise OMAP DATA MANUAL official document from Texas Instruments official site http://focus.ti.com

5.4 MEMORY The memory is mounted on top of the processor as mentioned. The key function of the POP memory is to provide:

4Gb (Giga Bits) NAND x 16 (512 Mega Bytes)

4Gb (Giga Bits) LP-DDR SDRAM x32 (512 Mega Bytes @ 200MHz)

5.5 POWER MANAGEMENT The TPS65950 is used to provide power to the IGEP™ v2 Board with the exception of the 3.3V regulator which is used to provide power to the DVI-D encoder and RS232 driver. In addition to the power it also provides:

Stereo Line Audio Out

Stereo Line Audio in

Power on reset

USB OTG PHY

Status LED

DOCUMENT FROM ISEE 2007 S.L. Ref: MAN-PR-IGEP0020-RCx 16

IGEPTM v2 Hardware Reference Manual

For accurate information on this chip, revise TPS65950 DATA MANUAL official document from Texas Instruments official site http://focus.ti.com

5.6 WIFI/BLUETOOTH INTERFACE IEEE802.11b/g compliant.

WLAN: Chipset based on Marvell 88W8686. The 88W8686 integrates a RF transceiver operating at 2.4GHz, a physical layer, a media access controller, and an ARM processor into a single die.

BLUETOOTH: Chipset based on CSR BC4ROM/21e. Bluetooth 2.0 compliant.

Class 2, 2.5 mW (4 dBm) ~10 meters. Version 2.0 + EDR 3 Mbit/s

5.6.1 BLOCK DIAGRAM

Figure 8 Wi-Fi/Bluetooth Combo module block Diagram 5.6.2 INTERFACES

Terminal Type System Description Name RST_N_B I BT Reset (active low). It must be low for >5ms. PCM_OUT O BT Synchronous data output CMOS output, tri-statable with weak internal pull-down

PCM_SYNC I/O BT Synchronous data sync, Bi Directional with weak internal pull-down. PCM_IN I BT Synchronous data input, CMOS input, with weak pull-down PCM_CLK I/O BT Synchronous data clock ,Bi Directional with weak internal pull-down. UART_TX O BT UART data output active high. CMOS output, tri-statable with weak internal pull-up. UART_CTS I BT UART clear to send active low. CMOS input with weak internal pull-down.

UART_RX I BT UART data input active high. CMOS input, with weak internal pull up

DOCUMENT FROM ISEE 2007 S.L. Ref: MAN-PR-IGEP0020-RCx 17

IGEPTM v2 Hardware Reference Manual

UART_RTS O BT UART request to send active low. CMOS input with weak internal pull-down.

SD_D3 I/O WLAN SDIO 4-bit Mode: SD_DAT[3] Data Line Bit [3] SDIO 1-bit Mode: SD_DAT[3] Reserved SDIO SPI Model: SD_DAT[3] Card Select (active low) SD_D2 I/O WLAN G-SPI Mode: SPI_SINTn G-SPI interrupt Output (active low) SDIO 4-bit Mode: SD_DAT[2] SPI_SINTn Data Line Bit [2] or Read Wait (optional) SDIO 1-bit Mode: SD_DAT[2] Read Wait (optional) SDIO SPI Model: SD_DAT[2] Reserved SD_D1 I/O WLAN G-SPI Mode: SPI_SDO SPI_SDO G-SPI Data Output SDIO 4-bit Mode: SD_DAT[1] Data Line Bit [1] SDIO 1 -bit Mode: SD_DAT[1] Interrupt SDIO SPI Model: SD_DAT[1] Reserved SD_D0 I/O WLAN G-SPI Mode: SPI_SCSn G-SPI Chip Select input SDIO 4-bit Mode: SD_DAT[0] Data Line Bit SPI_SCSn [0] SDIO 1-bit Mode: SD_DAT[0] Data Line SDIO SPI Model: SD_DAT[0] Data Output SD_CMD I/O WLAN G-SPI Mode: SPI_SDI G-SPI Data Input SDIO 4-bit Mode: SD_CMD Command/Response SPI_SDI SDIO 1-bit Mode: SD_CMD Comma nd Line SDIO SPI Model: SD_CMD Da ta Input SD_CLK I/O WLAN G-SPI Mode: SPI_CLK G-SPI Clock Input SDIO 4-bit Mode: SD_CLK Clock Input SDIO 1-bit SPI_CLK Mode: SD_CLK Clock Input SDIO SPI Model: SD_CLK Clock Input RESET_N_W I WLAN Internal pull-up. Reset (active low)

PDn I WLAN Full Power Down (active low) 0 = full power down mode 1 = normal mode

Table 9 Wi-Fi/Bluetooth Interface summary

Bluetooth UART uses the UART 2 from OMAP3530/DM3730.

Bluetooth Digital Audio uses MCBSP3 from OMAP3530/DM3730.

Wi-Fi uses MMC2 interface from OMAP3530/DM3730.

[MMC2_CLK0, MMC2_CMD, MMC2_DAT0, MMC2_DAT1, MMC2_DAT2, MMC2_DAT3].

UART2 and McBSP3 can be used in boards without Wi-Fi/Bluetooth or if the Bluetooth is in reset and TPS65950 PCM VSP it’s disabled.

5.6.3 POWER-ON RESET SEQUENCE FOR WLAN

PDn / RESET_N_W tied together

PDn pin separated from RESET_N_W. Host cannot pulse RESET_N_W pin.

DOCUMENT FROM ISEE 2007 S.L. Ref: MAN-PR-IGEP0020-RCx 18

IGEPTM v2 Hardware Reference Manual

PDn pin separated from RESET_N_W. Host controls pulsing of RESET_N_W pin.

5.6.4 WLAN RESET/PDN PINS Reset can be done by using GPIO_94 or GPIO_138. See your IGEP™ v2 model to know default assembly option (See FAQ in http://labs.igep.es)

Power down can be done by using GPIO_95 or GPIO_139. See your IGEP™ v2 model to know default assembly option (See FAQ in http://labs.igep.es).

5.6.5 BLUETOOTH RESET PINS Reset can be done by using GPIO_182 or GPIO_137. See your IGEP™ v2 model to know default assembly option (See FAQ in http://labs.igep.es)

DOCUMENT FROM ISEE 2007 S.L. Ref: MAN-PR-IGEP0020-RCx 19

IGEPTM v2 Hardware Reference Manual

5.6.6 PCM INTERFACE

5.6.6.1 TPS65950 SIDE

5.6.6.2 WI-FI MODULE SIDE PCM_OUT –Output- Synchronous data output CMOS output, tri-state with weak internal pull- down

PCM_SYNC -I/O- Synchronous data sync Bi Directional with weak internal pull-down.

PCM_IN – Input - Synchronous data input CMOS input, with weak pull-down

PCM_CLK - I/O - Synchronous data clock Bi Directional with weak internal pull-down.

McBSP3 it’s connected to OMAP3530/DM3730 and TPS65950 (PCM VSP).

5.6.7 IGEP™ v2 ANTENNAS (INTERNAL/EXTERNAL - UD11, JD21, JD22) For the cable you will find cable assemblies if you look for CABLE ASSEMBLY RF GSM MURATA to SMA MALE.

JD21 and JD22 are U.FL series HIROSE connector for the external WIFI/BLUETOOTH antenna (Part number U.FL-R-SMT-1).

DOCUMENT FROM ISEE 2007 S.L. Ref: MAN-PR-IGEP0020-RCx 20

IGEPTM v2 Hardware Reference Manual

Figure 9 U.FL series receptacle connector specification

Figure 10 U.FL series Mated connector

PERMANENT DAMAGE CAN BE CAUSED IF ANY VOLTAGE IS APPLIED TO JD21 AND JD22 CONNECTORS. ENSURE CORRECT INSERTION ON COAXIAL CONNECTOR IN ORDER TO DO NOT LOSE RF PERFORMANCE

There are several ways to configure wifi/bluetooth antennas for IGEP™ v2 revision C board series.

DOCUMENT FROM ISEE 2007 S.L. Ref: MAN-PR-IGEP0020-RCx 21

IGEPTM v2 Hardware Reference Manual

Figure 11 IGEP™ v2 revision C antenna layout

OPTION 1: An internal shared antenna for both BT and WIFI interfaces

This is default factory configuration for IGEP™ v2 revision C

UD11, LD30=1.8nH, LD31=1.5nH, CD31=15pF are populated.

JD21, JD22, CD32 and CD33 are not populated.

OPTION 2: An external shared antenna for both BT and WIFI interfaces

JD22 is populated.

JD21, UD11, LD30, LD31, CD31, CD32, and CD33 are not populated.

NOTE: Contact ISEE sales for custom assembly boards.

Figure 12 IGEP™ v2 revision C antenna schematic

DOCUMENT FROM ISEE 2007 S.L. Ref: MAN-PR-IGEP0020-RCx 22

IGEPTM v2 Hardware Reference Manual

Figure 13 IGEP™ v2 revision C JD21, JD22 location

JD22 on yellow box (up) JD21 on blue box (down)

Figure 14 IGEP™ v2 revision C JD21, JD22 detail

DOCUMENT FROM ISEE 2007 S.L. Ref: MAN-PR-IGEP0020-RCx 23

IGEPTM v2 Hardware Reference Manual

5.7 MAIN 5Vdc POWER: J200 The J200 connector is a power jack for main 5 VDC power.

Verify that you use a 5V DC (4.8-5.2V max values) power supply.

Suggestion: 5V-DC / 1 A (Without HOST USB) – 5V-DC / 1.4 A (With USB HOST) J200 is a SWITCHCRAFT connector ref. RASM722BK, Plug/Mating Plug Diameter 2.1mm ID, 5.5mm OD or any other compatible.

Figure 15 J200 POWER JACK CONNECTOR VIEW & DIMENSIONS

J940 can also be used to power the board, please refer to this connector section 5.9 (RS485).

IGEP™ v2 MUST BE POWERED THROUGH J200 or J940 ONLY WITH +5Vdc. PERMANENT DAMAGE IF ANY OTHER VOLTAGE IS APPLIED. ENSURE TOTAL CURRENT DRAIN IS LOWER THAN 1A. DO NOT POWER WITH THE TWO CONNECTORS AT THE SAME TIME, USE ONLY ONE OF THEM.

5.8 JTAG DEBUG: J400 A 14 pin JTAG header is provided on board to facilitate the SW development and debugging of the board by using various JTAG emulators. The interface is at 1.8V on all signals. Only 1.8V CMOS levels are supported. DO NOT expose the JTAG header to 3.3V.

The J400 connector is a 14 pins 2x7 dual row 2.54mm.

DOCUMENT FROM ISEE 2007 S.L. Ref: MAN-PR-IGEP0020-RCx 24

IGEPTM v2 Hardware Reference Manual

Figure 16 J400 detail

Pins 1, 2, 13 and 14 are labeled on the PCB. The connector is located as shows the figure below.

Figure 17 J400 location

The schematic below illustrate the pin out of the connector.

Figure 18 Schematic J400

WARNING: JTAG signals go directly to OMAP processor. Improper use of this connector could result in permanent damage of the processor.

ISEE Suggested JTAG:

a) ISEE recommend JTAG Debugger XDS510+ USB from Spectrum Digital with Code Composer Studio 3.3 or higher.

DOCUMENT FROM ISEE 2007 S.L. Ref: MAN-PR-IGEP0020-RCx 25

IGEPTM v2 Hardware Reference Manual

b) ISEE recommend JTAG Debugger XD100v2 USB from Spectrum Digital with Code Composer Studio 4 or higher.

5.9 RS485: J940 The J940 connector is a HEADER CONNECTOR PH SIDE 5POS 2MM SMD from JST (Part Number: S5B-PH-SM3-TB).

It matches to JST CONNECTOR HOUSING PH 5POS 2MM WHITE (Part Number: JST PHR-5) and JST TERMINALS CRIMP PH 24-30AWG (Part Number: JST SPH-002T-P0.5S). IGEP™ v2 don’t include cable neither plug connector.

Pin 1 is labeled on the PCB. The connector is located as shown in the figure below.

Figure 19 J940 location

Figure 20 J940 detail pin 1

The schematic below illustrate the pinout of the connector.

DOCUMENT FROM ISEE 2007 S.L. Ref: MAN-PR-IGEP0020-RCx 26

IGEPTM v2 Hardware Reference Manual

Figure 21 Schematic J940

User can use this connector to power the board with 5VDC. Use only 5V regulated DC.

IGEP™ v2 BOARD does not use this 9v power supply. Only on IGEP™ v2 revision B, the PWR_9V input is directly routed to JC01 and J970 connectors. On IGEP™ v2 revision C is not available.

There is also a RS485 transceiver on the connector.

Figure 22 - Schematic RS485 driver

Figure 23 Schematic level-shifters for RS485 driver

[Contact ISEE sales for custom assembly boards for RS485 features (always listener, independent receive/transmit, termination value,…)].

DOCUMENT FROM ISEE 2007 S.L. Ref: MAN-PR-IGEP0020-RCx 27

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5.10 SERIAL PORT DEBUG (+ EXTRA RS232) J960 The J960 connector is a 5x2 pins double row 2.54mm.

Pin1

Figure 24 J960 detail

The connector is located as showed in the figure below.

Figure 25 J960 location

Figure 26 IDC-10 to DB9 cable

The 5x2 Header follow the IDC-10 (AT-Everex) configuration. So, it is needed null modem configuration (connection between two computers). RX and TX lines are crossed in this null modem configuration between two equipments (TX1->RX2 / TX2->RX1).

The next table shows the pin out of J960 connector (pins not listed are not connected):

DOCUMENT FROM ISEE 2007 S.L. Ref: MAN-PR-IGEP0020-RCx 28

IGEPTM v2 Hardware Reference Manual

Signal Name Pin # Description RS232_RX2 J960:2 UART3_RX (R966) (optionally UART2_RX (R952)) RS232_TX2 J960:3 UART3_TX (R965) (optionally UART2_TX (R947)) GND J960:5 GND J960:6 RS232_TX1 J960:8 UART1_TX (R961) (optionally UART3_TX (R940)) RS232_RX1 J960:9 UART1_RX (R962) (optionally UART3_RX (R942)) Table 10 IGEP™ v2 revision C RS232 signals in J960 connector

WARNING: IF YOU HAVE AN IGEPTM v2 BOARD REVISION B YOU MUST BE AWARE YOU ONLY HAVE ONE RS232 DEBUG INTERFACE (WITH TRANSCEIVER)

ON IGEPTM v2 BOARD REVISION C YOU MAY NEED TO MODIFY YOUR SERIAL DEBUG CABLE IN ORDER TO AVOID POSSIBLE MALFUNCTIONNING.

5.10.1 DEBUG CABLE MODIFICATIONS (ONLY REV C) Only on IGEPTM v2 BOARD REVISION C you may require to make some modifications ONLY in case you connect your IGEPTM v2 with an old device that needs RTS and/or RTC signals. Due to some pins of J960 connector are connected to ground you may be experiencing some troubles with such kind of devices. ONLY if this is your case here we give you a hardware solution consisting on cutting some of the wires of debug connector:

1-With a cutter separate carefully the group of last 4 wires from the group of the first 5.

2-Cut the group of the last 4 wires (6, 7, 8 and 9) with a scissor.

3-Your debug cable has now these 4 wires disabled.

4-You are now ready to connect your device.

4 2 1

Figure 27 DEBUG CABLE MODIFICATIONS (ONLY REV. C)

DOCUMENT FROM ISEE 2007 S.L. Ref: MAN-PR-IGEP0020-RCx 29

IGEPTM v2 Hardware Reference Manual

5.10.2 NEW FEATURES ON REV C On IGEP™ v2 revision C several features have been added:

NOTE: Contact ISEE sales for custom assembly boards.

Additional RS232 port (UART1) on same J960 connector. It is only needed to rotate 180º the IDC-10 (AT-Everex) to DB9 cable.

It has been added resistors for alternative UART1, UART2 and UART3 hardware selection.

Also, IGEP™ v2 revision C series have debug RS232 interface with transceiver (UART3) like IGEP™ v2 revision B series.

The schematic below illustrate IGEP™ v2 revision C pin out of the connector.

Figure 28 IGEP™ v2 revision C Schematic J960 First RS232 is located on J960 pins 2 and 3, and the second one on pins 8 and 9.

Next resistors enable hardware UART select to assign them on each connector.

DOCUMENT FROM ISEE 2007 S.L. Ref: MAN-PR-IGEP0020-RCx 30

IGEPTM v2 Hardware Reference Manual

Figure 29 IGEP™ v2 revision C resistors for UART hardware selection

5.10.3 HOW TO USE UART 1 On IGEP™ v2 revision C, UART1 is shared with RS485 driver.

In order to use UART1 as RS232 port instead of RS485 you need configure to UART1_RTS and UART1_CTS pins in safe mode. To do that you have two options:

1. Modify your kernel: a. On file board-igep0020.c b. On function static void __init igep2_init(void) c. After line omap3_mux_init(board_mux, OMAP_PACKAGE_CBB) d. Place this two lines: i. omap_mux_init_signal("uart1_rts.safe_mode", 0); ii. omap_mux_init_signal("uart1_cts.safe_mode", 0); 2. From kernel space: a. $ mount -t debugfs none /sys/kernel/debug b. $ echo 0x007 > /sys/kernel/debug/omap_mux/uart1_rts c. $ echo 0x007 > /sys/kernel/debug/omap_mux/uart1_cts

Take care that next two options are enabled on your kernel:

1. CONFIG_OMAP_MUX=y 2. CONFIG_OMAP_MUX_DEBUG=y

DOCUMENT FROM ISEE 2007 S.L. Ref: MAN-PR-IGEP0020-RCx 31

IGEPTM v2 Hardware Reference Manual

5.11 KEYBOARD MATRIX 4x4: J970 The J970 connector is an 8 pins single row 2.54mm (It is not populated by default on IGEP™ v2 boards).

Figure 30 J970 detail

It can be used to connect

a 4x4 keyboard matrix.

Figure 31 Keyboard matrix 4x4 and schematic example

Pin 1 is labeled on the PCB. The connector is located as shows the figure below.

DOCUMENT FROM ISEE 2007 S.L. Ref: MAN-PR-IGEP0020-RCx 32

IGEPTM v2 Hardware Reference Manual

Figure 32 J970 location

The schematic below illustrate the pin out of the connector.

Figure 33 Schematic J971 KPD_Cx: columns

KPD_Rx: rows

When a key button of the keyboard matrix is pressed the corresponding row and column lines are shorted together. To allow key press detection, all input pins (KBR) are pulled up to VCC and all output pins (KBC) driven to a low level.

Any action on a button generates an interrupt to the sequencer.

The decoding sequence is written to allow detection of simultaneous press actions on several key buttons.

DOCUMENT FROM ISEE 2007 S.L. Ref: MAN-PR-IGEP0020-RCx 33

IGEPTM v2 Hardware Reference Manual

5.12 TFT INTERFACE CONNECTORS: JA41 & JA42 There are two 1.27mm Double Row Terminal Strip for the TFT interface. Both are from SAMTEC manufacturer (Part Number FTS-114-01-L-D & FTS-110-01-L-D).

5.12.1 CONNECTOR JA41

Figure 34 IGEP™ v2 revision C JA41 location

Figure 35 IGEP™ v2 revision C JA41 and JA42 detail

Figure 36 IGEP™ v2 revision C JA41-JA42 pin out detail

DOCUMENT FROM ISEE 2007 S.L. Ref: MAN-PR-IGEP0020-RCx 34

IGEPTM v2 Hardware Reference Manual

These connectors allow the access to the LCD signals. Next table shows the signals that are on the JA41 connector (pins 21 to 28 are not available on IGEP™ v2 revision B series), with functionalities that you can configure. Each table has several columns:

Pin #: (JJ:PP format) where JJ means JA41 connector and PP means pin number.

TYPE: What kind of pin and origin silicon chip :

OMAP: processor; PMIC: power management chip; PWR: Power and ground lines

MODE 0, MODE 1, MODE 2, MODE 3, MODE 4, MODE 5, MODE 6, MODE 7: OMAP3x pin could be configured up to 7 different modes. Complexity of configuration could be solved at “Pin Mux Utility for ARM(R) Microprocessors” on http://www.ti.com/tool/pinmuxtool

“gray shading” marked function names denote the function is already being used on board by DVI device interface (see section 5.21 DVI-D INTERFACE: JA01).

“green shading” marked function names denote this function is ONLY available on OMAP3530 (not present on DM3730).

“blue shading” marked function names denote this function is ONLY available on DM3730 (not present on OMAP3530).

Functions within [] brackets on column “MODE 0” denote board pin function.

For additional details, please refer to “OMAP3530/25 Applications Processor” (www.TI.com)

Pin # TYPE MODE 0 MODE 2 MODE 3 MODE 4 MODE 5 MODE 7 JA41:1 PWR 3V3 JA41:2 PWR GND JA41:3 OMAP dss_data0 [DVI_DATA0] uart1_cts dssvenc656_d0 gpio_70 safe_mode JA41:4 OMAP dss_data1 [DVI_DATA1] uart1_rts dssvenc656_d1 gpio_71 safe_mode JA41:5 OMAP dss_data2 [DVI_DATA2] dssvenc656_d2 gpio_72 safe_mode JA41:6 OMAP dss_data3 [DVI_DATA3] dssvenc656_d3 gpio_73 safe_mode JA41:7 OMAP dss_data4 [DVI_DATA4] uart3_rx_irrx dssvenc656_d4 gpio_74 safe_mode JA41:8 OMAP dss_data5 [DVI_DATA5] uart3_tx_irtx dssvenc656_d5 gpio_75 safe_mode JA41:9 OMAP dss_data6 [DVI_DATA6] uart1_tx dssvenc656_d6 gpio_76 hw_dbg14 safe_mode JA41:10 OMAP dss_data7 [DVI_DATA7] uart1_rx dssvenc656_d7 gpio_77 hw_dbg15 safe_mode JA41:11 OMAP dss_data8 [DVI_DATA8] gpio_78 hw_dbg16 safe_mode JA41:12 OMAP dss_data9 [DVI_DATA9] gpio_79 hw_dbg17 safe_mode JA41:13 OMAP dss_data10 [DVI_DATA10] gpio_80 safe_mode JA41:14 OMAP dss_data11 [DVI_DATA11] gpio_81 safe_mode JA41:15 OMAP dss_data12 [DVI_DATA12] gpio_82 safe_mode JA41:16 OMAP dss_data13 [DVI_DATA13] gpio_83 safe_mode JA41:17 OMAP dss_data14 [DVI_DATA14] gpio_84 safe_mode JA41:18 OMAP dss_data15 [DVI_DATA15] gpio_85 safe_mode JA41:19 OMAP dss_data16 [DVI_DATA16] gpio_86 safe_mode JA41:20 OMAP dss_data17 [DVI_DATA17] gpio_87 safe_mode JA41:21 OMAP dss_data18 [DVI_DATA18] mcspi3_clk dss_data0 gpio_88 safe_mode JA41:22 OMAP dss_data19 [DVI_DATA19] mcspi3_simo dss_data1 gpio_89 safe_mode JA41:23 OMAP dss_data20 [DVI_DATA20] mcspi3_somi dss_data2 gpio_90 safe_mode JA41:24 OMAP dss_data21 [DVI_DATA21] mcspi3_cs0 dss_data3 gpio_91 safe_mode JA41:25 OMAP dss_data22 [DVI_DATA22] mcspi3_cs1 dss_data4 gpio_92 safe_mode JA41:26 OMAP dss_data23 [DVI_DATA23] dss_data5 gpio_93 safe_mode

DOCUMENT FROM ISEE 2007 S.L. Ref: MAN-PR-IGEP0020-RCx 35

IGEPTM v2 Hardware Reference Manual

JA41:27 OMAP I2C3_SCL gpio_184 safe_mode JA41:28 OMAP I2C3_SDA gpio_185 safe_mode Table 11 JA41 Connector signals

The schematic below illustrates the pin out of the connector:

Figure 37 IGEP™ v2 rev C Schematic of JA41 connector

All IGEP™ v2 boards (Revisions B and C) are mechanical, electrical and logical compatible.

This allows for the creation of LCD boards to support different LCD panels.

Be aware all OMAP type pins are 1V8 level. If you need to work with 3V3 level you can easily build a level shifter by using 3V3 voltage on pin 1.

DOCUMENT FROM ISEE 2007 S.L. Ref: MAN-PR-IGEP0020-RCx 36

IGEPTM v2 Hardware Reference Manual

5.12.2 CONNECTOR JA42

Figure 38 IGEP™ v2 JA42 location

Following the same notation than in previous connector JA41, the next table show the pin out and multiplexing functions capabilities of the connector JA42:

Pin # TYPE MODE 0 MODE 1 MODE 3 MODE 4 MODE 5 MODE 6 MODE 7 JA42:1 PWR VIO_1V8 JA42:2 OMAP SYS_BOOT5 -pull up- mmc2_dir_d3 dss_data22 gpio_7 safe_mode JA42:3 PWR DC_5V JA42:4 PWR GND JA42:5 OMAP SYS_BOOT0 -pull up- dss_data18 gpio_2 safe_mode JA42:6 OMAP SYS_BOOT1 -pull up- dss_data19 gpio_3 safe_mode JA42:7 OMAP dss_vsync [DVI_VSYNC] gpio_68 safe_mode JA42:8 OMAP dss_hsync [DVI_HSYNC] gpio_67 hw_dbg13 safe_mode JA42:9 OMAP dss_acbias [DVI_ACBIAS] gpio_69 safe_mode JA42:10 OMAP hdq_sio [DVI_PUP] gpio_170 safe_mode JA42:11 OMAP dss_pclk [DVI_PCLK] gpio_66 hw_dbg12 safe_mode JA42:12 OMAP mcspi1_cs1 [TS_nPEN_IRQ] mmc3_cmd gpio_175 safe_mode JA42:13 OMAP mcbsp4_dx gpio_154 hsusb3_tll_d2 mm3_txdat safe_mode [LCD_QVGA/nVGA] JA42:14 OMAP mcbsp4_dr [LCD_ENVDD] gpio_153 hsusb3_tll_d0 mm3_rxrcv safe_mode JA42:15 OMAP mcbsp4_fsx [LCD_RESB] gpio_155 hsusb3_tll_d3 mm3_txenn safe_mode JA42:16 OMAP mcbsp4_clkx [LCD_INI] gpio_152 hsusb3_tll_d1 mm3_txse0 safe_mode JA42:17 OMAP MCSPI1_CLK mmc2_d4 gpio_171 safe_mode JA42:18 OMAP MCSPI1_SIMO mmc2_d5 gpio_172 safe_mode JA42:19 OMAP MCSPI1_CS0 mmc2_d7 gpio_174 safe_mode JA42:20 OMAP MCSPI1_SOMI mmc2_d6 gpio_173 safe_mode Table 12 JA42 connector pin out

The electrical current available on DC_5V rail is limited to the available current remaining from the DC supply that is connected to the DC power jack on the board. Keep in mind that some of that power is needed by the USB Host power rail and if more power is needed for the expansion board, the main DC power supply current capability may need to be increased. All signals are 1.8V except the DVI_PUP which is a 3.3V signal.

The 1.8V rail is for level translation only and should not be used to power circuitry on the board. The 3.3V rail also has limited capacity on the power as well.

It is suggested that the 5V rail be used to generate the required voltages for an adapter card.

DOCUMENT FROM ISEE 2007 S.L. Ref: MAN-PR-IGEP0020-RCx 37

IGEPTM v2 Hardware Reference Manual

Figure 39 IGEP™ v2 revision B and C Schematic JA42

DVI_PUP is a control signal for the DVI controller. When High, DVI is enabled. Can be used to activate circuitry on adapter board if desired.

NOTE: JA41 and JA42 connectors are NOT Beagle Board compatible.

WARNING: TFT signals go directly to OMAP processor. Improper use of this connector could result on permanent damage to this processor.

5.12.3 CONNECTORs JA41-JA42 COUNTERPARTs

JA41 and JA42 mates with SFMC SAMTEC Series:

SAMTEC HLE Serie BOTTOM ENTRY

SAMTEC SAMTEC SFMC erie SFMC Serie

SAMTEC SAMTEC SAMTEC TSW Serie FTS Serie FTS Serie

Figure 40 IGEP™ v2 revision C JA41-JA42 counterparts

DOCUMENT FROM ISEE 2007 S.L. Ref: MAN-PR-IGEP0020-RCx 38

IGEPTM v2 Hardware Reference Manual

5.13 ANALOG TO DIGITAL CONVERTER: JC20 & JC21

JC20 is a U.FL series HIROSE connector to input analog signals to the analog to digital converter (Connector Part number is U.FL-R-SMT-1 or any other compatible). There is also connector JC21 (2pin 2,54mm pitch Header) in parallel for this feature.

On IGEP™ v2 Revision C, analog to digital converter device, JC20 and JC21 are not populated by default. [Contact ISEE sales for custom assembly boards for this feature].

Figure 41 IGEP™ v2 revision C JC20 location

Figure 42 IGEP™ v2 revision C JC20 detail

DOCUMENT FROM ISEE 2007 S.L. Ref: MAN-PR-IGEP0020-RCx 39

IGEPTM v2 Hardware Reference Manual

Several ADC devices can be populated. For example:

ADC-SPI 3MSps 3V3 (LTC2366)

ADC-SPI 1MSps 5VDC (ADC121S101)

Figure 43 IGEP™ v2 revision C schematic A/D

Figure 44 IGEP™ v2 revision C schematic A/D SPI interface

DOCUMENT FROM ISEE 2007 S.L. Ref: MAN-PR-IGEP0020-RCx 40

IGEPTM v2 Hardware Reference Manual

5.14 CAMERA INTERFACE: JC30 There is one 1.27mm Double Row Terminal Strip for the Camera interface from SAMTEC manufacturer (Part Number FTS-114-01-L-D).

This JC30 connector is only available on IGEP™ v2 revision C series.

Figure 45 IGEP™ v2 revision C JC30 location

Figure 46 IGEP™ v2 revision C JC30 detail

Figure 47 IGEP™ v2 revision C JC30 pin out detail

These connectors allow the access to the Camera interface signals.

DOCUMENT FROM ISEE 2007 S.L. Ref: MAN-PR-IGEP0020-RCx 41

IGEPTM v2 Hardware Reference Manual

Below pin table show you pin out of IGEP™ v2 camera connector JC30, with functionalities that you can configure. Each table has several columns:

Pin #: (JJ:PP format) where JJ means JC30 connector and PP means pin number.

TYPE: What kind of pin and origin silicon chip :

OMAP: processor; PMIC: power management chip; PWR: Power and ground lines

“gray shading” marked function names denote the function is already being used on board and should not be used.

Functions within [] brackets on column “MODE 0” denote board pin function.

For additional details, please refer to “OMAP3530/25 Applications Processor” (www.TI.com)

Pin # TYPE MODE 0 MODE 2 MODE 4 MODE 5 MODE 7 JC30:1 OMAP CAM_HS [Power Down WiFi] gpio_94 hw_dbg0 safe_mode JC30:2 OMAP CAM_VS [Reset WiFi] gpio_95 hw_dbg1 safe_mode JC30:3 OMAP CAM_XCLKA gpio_96 safe_mode JC30:4 PWR GND JC30:5 OMAP CAM_PCLK gpio_97 hw_dbg2 safe_mode JC30:6 PWR GND JC30:7 OMAP CAM_D0 gpio_99 safe_mode JC30:8 OMAP CAM_FLD cam_global_rst gpio_98 hw_dbg3 safe_mode JC30:9 OMAP CAM_D2 gpio_101 hw_dbg4 safe_mode JC30:10 OMAP CAM_D1 gpio_100 safe_mode JC30:11 OMAP CAM_D4 gpio_103 hw_dbg6 safe_mode JC30:12 OMAP CAM_D3 gpio_102 hw_dbg5 safe_mode JC30:13 OMAP CAM_D6 gpio_105 safe_mode JC30:14 OMAP CAM_D5 gpio_104 hw_dbg7 safe_mode JC30:15 OMAP CAM_D8 gpio_107 safe_mode JC30:16 OMAP CAM_D7 gpio_106 safe_mode JC30:17 OMAP CAM_D10 gpio_109 hw_dbg8 safe_mode JC30:18 OMAP CAM_D9 gpio_108 safe_mode JC30:19 OMAP CAM_XCLKB gpio_111 safe_mode JC30:20 OMAP CAM_D11 gpio_110 hw_dbg9 safe_mode JC30:21 OMAP (GPIO_112) -optional I2C2_SCL- gpio_112 safe_mode JC30:22 OMAP (GPIO_113) -optional I2C2_SDA- gpio_113 safe_mode JC30:23 OMAP (GPIO_114) [cam_res et] gpio_114 safe_mode JC30:24 OMAP (GPIO_115) [cam_pdn] gpio_115 safe_mode JC30:25 OMAP CAM_STROBE gpio_126 hw_dbg11 safe_mode JC30:26 OMAP CAM_WEN cam_shutter gpio_167 hw_dbg10 safe_mode JC30:27 PWR 3V3 JC30:28 PWR 3V3 Table 13 Camera Connector signals

DOCUMENT FROM ISEE 2007 S.L. Ref: MAN-PR-IGEP0020-RCx 42

IGEPTM v2 Hardware Reference Manual

All signals are 1.8V.

It is suggested that the 3V3 rail be used to generate the required voltages for an adapter card.

The schematic below illustrate the pin out of the connectors.

Figure 48 IGEP™ v2 revision C JC30 schematic

WARNING: CAMERA signals go directly to OMAP processor. Improper use of this connector could result on permanent damage to this processor.

5.15 S-VIDEO SIGNALS: TP400 & TP401 S-video signals are available on TP400 and TP401 test points.

Figure 49 TP400 and TP401 schematic

DOCUMENT FROM ISEE 2007 S.L. Ref: MAN-PR-IGEP0020-RCx 43

IGEPTM v2 Hardware Reference Manual

Figure 50 TP400 and TP401 location

WARNING: DM3730 use different component values on S-Video output lines.

WARNING: VIDEO signals go directly to OMAP processor. Improper use of this connector could result on permanent damage to this processor.

5.16 RTC BACKUP BATTERY The TPS65950 implements a backup mode, in which the backup battery keeps the RTC running. A rechargeable backup battery can be recharged from the main battery.

This RTC feature is only available on IGEP™ v2 revision C series.

When the main battery is below 2.7 V or is removed, the backup battery powers the backup if the backup battery voltage is greater than 1.8 V. The backup domain powers up the following:

• Internal 32.768-kHz oscillator and RTC

• Hash table (20 registers of 8 bits each) and Eight GP storage registers

TPS65950 battery backup is available by using BT741 or C741.

Figure 51 IGEP™ v2 revision C TPS65950 battery backup schematic

DOCUMENT FROM ISEE 2007 S.L. Ref: MAN-PR-IGEP0020-RCx 44

IGEPTM v2 Hardware Reference Manual

BT741: is Lithium Coin Battery (VL Series) from Panasonic

Figure 52 BT741 specification

C741: is an Electric Double Layer Capacitors from PANASONIC (EN Series)

Figure 53 C741 specification

DOCUMENT FROM ISEE 2007 S.L. Ref: MAN-PR-IGEP0020-RCx 45

IGEPTM v2 Hardware Reference Manual

Figure 54 IGEP™ v2 revision C: BT741 location

Figure 55 IGEP™ v2 revision C: C741 location

ATTENTION: If battery is needed, resistor R741 MUST BE REMOVED:

Figure 56 R741 location

DOCUMENT FROM ISEE 2007 S.L. Ref: MAN-PR-IGEP0020-RCx 46

IGEPTM v2 Hardware Reference Manual

5.17 USB 2.0 OTG: J830 IGEP™ v2 includes a single USB 2.0 LS/FS/HS OTG Port (J830) directly connected to the USB OTG pins of the OMAP processor.

Figure 57 J830 USB OTG CONNECTOR SIZE & PIN OUT

The USB 2.0 OTG interface is implemented with the OMAP35xx USB 2.0 OTG controller:

Operates either as the function controller of a high/full speed USB peripheral or as host in point-to-point or multipoint communications Complies with the USB 2.0 standard for high-speed (480 Mbps) function and with on- the-go (OTG) supplement. Supports USB 2.0 peripheral at High Speed (480 Mbps) and Full Speed (12 Mbps) Supports USB 2.0 host at High (480 Mbps), Full (12 Mbps) and Low Speed (1.5 Mbps)

J830 is an USB Type mini AB Socket Connector with Part Number FCI 10033527-N3212MLF or any other compatible.

The USB OTG signals are available through next connector pins:

Signal Name Pin # Description HSUSB_DP J830:3 USB OTG positive data (D+) HSUSB_DN J830:2 USB OTG negative data (D-) HSUSB_ID J830:4 USB OTG ID VBUS_5V J830:1 USB OTG VBUS (+5VDC) Table 14 USB OTG signals in J830 connector

For additional details, please refer to section 23.1 of the “OMAP35x Technical Reference Manual”

DOCUMENT FROM ISEE 2007 S.L. Ref: MAN-PR-IGEP0020-RCx 47

IGEPTM v2 Hardware Reference Manual

DO NOT USE USB OTG CONNECTOR (PIN J830:1) TO POWER IGEP™ v2. PERMANENT DAMAGE CAN BE CAUSED DUE TO EXCESSIVE CURRENT DRAIN (Maximum Current in Host configuration is 100mA)

5.18 USB 2.0 HOST: J800 IGEP™ v2 includes an USB 2.0 HS HOST port available through Type A socket, J800. Hardware provides power on/off switch control and up to 500mA of current limit at 5V. When using USB power is mandatory you check the maximum current consumption is lower than 500mA.

USB HOST Port supports only high speed devices (USB 2.0 HS devices). In order to support low speed devices (USB 1.0 LS devices) or full speed devices (USB 1.1 FS devices), external self powered USB 2.0 HUB must be used.

J800 is RECEPTACLE USB TYPE A CONNECTOR with Part Number ASSMAN USB-1A or any other compatible:

Figure 58 J800 USB HOST CONNECTOR VIEW & PIN OUT

WHEN USING POWER FROM USB PORT YOU MUST ENSURE THE CURRENT DRAIN IS LOWER THAN 500mA.

The USB HOST signals are available through next connector pins:

Signal Name Pin # Description HOST_D+ J800:3 USB positive data (D+) HOST_D- J800:2 USB negative data (D-) GND J800:4 USB GROUND HOST_VBUS J800:1 USB OTG VBUS (+5VDC) Table 15 USB HOST signals in J800 connector

DOCUMENT FROM ISEE 2007 S.L. Ref: MAN-PR-IGEP0020-RCx 48

IGEPTM v2 Hardware Reference Manual

5.19 ETHERNET: JB01

IGEP™ v2 includes one RJ45 connector, JB01, provided for Ethernet Auto-MDIX Full Duplex 10/100 Base T interface. This port is supported by a High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O for each of the ports implemented with the SMSC LAN9221i. There is an optional EEPROM memory (UB30) for MAC configuration (not populated).

NOTE: Contact ISEE sales for custom assembly boards.

Figure 59 J1001, J1101 & J3 ETHERNET CONNECTORS VIEW & SIZE

The Ethernet interface supports the following features:

Fully compliant with IEEEE 802.3/802.3u standards 10BASE-T and 100BASE-TX support Full-and Half-duplex support Full-duplex flow control Backpressure for half-duplex flow control Link Activity Status LED

DOCUMENT FROM ISEE 2007 S.L. Ref: MAN-PR-IGEP0020-RCx 49

IGEPTM v2 Hardware Reference Manual

The JB01 RJ45 connector is Part Number HALO HFJ11-RPE26E-S1L12RL or any other compatible. The next figure shows the signals on each pin:

Figure 60 JB01 ETHERNET CONNECTOR SCHEMATIC

5.20 AUDIO: J650 & J640 3.5mm standard stereo input and output audio jacks (J650 & J640) are provided to access the stereo input and output of the audio CODEC included on TPS65950 device of processor board.

The audio codec in the TPS65950 device includes five DACs and two ADCs to provide multiple voice channels and stereo downlink channels. The audio output stages on the device include stereo headset amplifiers, two integrated class-D amplifiers providing stereo differential outputs, pre-drivers for line outputs, and an earpiece amplifier. The input audio stages include three differential microphone inputs and stereo line inputs. Automatic and programmable gain control is available with all necessary digital filtering, side-tone functions, and pop-noise reduction. Please check TPS65950 user manual on official www.ti.com website for more detailed information.

Figure 61 J650 & J640 AUDIO INTERFACE

DOCUMENT FROM ISEE 2007 S.L. Ref: MAN-PR-IGEP0020-RCx 50

IGEPTM v2 Hardware Reference Manual

J650 & J640 are 3.5mm Jack Stereo Audio SMT Connectors (In & Out respectively) with Part Number SWITCHCRAFT 35RASMT2BHNTR or any other compatible.

Figure 62 J602 & J601 AUDIO CONNECTORS SCHEMATIC & SIZE

J601 & J602 are linked to the expansion connector J1:

Signal Name Pin # Description HSOL J640:4 Differential/single-ended headset Left Output HSOR J640:1 Differential/single-ended headset Right Output GND J640:5 Ground AUXL J650:4 Left stereo audio input AUXR J650:1 Right stereo audio input GND J650:5 Ground Table 16 J1 links to J640 & J650 audio interface connectors

DOCUMENT FROM ISEE 2007 S.L. Ref: MAN-PR-IGEP0020-RCx 51

IGEPTM v2 Hardware Reference Manual

Stereo Audio Output Connector J640

A 3.5mm standard stereo output audio jack is provided to access the stereo output of the onboard audio CODEC. The Audio CODEC is provided by the TPS65950.

Figure 63 Stereo Output J640 connector location

Stereo Audio In connector J650

A 3.5mm standard stereo audio input jack is provided to access the stereo input of the onboard audio CODEC.

Figure 64 Stereo Input J650 connector location

DOCUMENT FROM ISEE 2007 S.L. Ref: MAN-PR-IGEP0020-RCx 52

IGEPTM v2 Hardware Reference Manual

5.21 DVI-D INTERFACE: JA01 IGEP™ v2 BOARD can drive an LCD panel equipped with a DVI-D digital input. This is the standard LCD panel interface of the OMAP3530/DM3730.

DDC2B (Display Data Channel) or EDID (Enhanced Display ID) support over I2C is provided in order to allow the identification of the LCD monitor type and settings.

IGEP™ v2 BOARD does not support the full HDMI interface and is used to provide the DVI-D interface portion only. The user must use a HDMI to DVI-D cable or adapter to connect to a LCD monitor. A standard HDMI cable can be used when connecting to a monitor with and HDMI connector.

Figure 65 HDMI STANDARD CONNECTOR VIEW

JA01 is an HDMI TYPE A RECEPTACLE CONNECTOR with Part Number FCI 10029449-001RLF or any other compatible.

Figure 66 JA01 DVI-D INTERFACE HDMI TYPE CONNECTOR SIZE & PIN OUT

DOCUMENT FROM ISEE 2007 S.L. Ref: MAN-PR-IGEP0020-RCx 53

IGEPTM v2 Hardware Reference Manual

5.22 MICRO-SD: J900 A micro-SD connector is provided for micro-SD cards form factor.

The micro-SD memory card is the smallest memory card available commercially, with the lowest price per capacity and the highest capacity. At 15 mm × 11 mm × 1 mm (about the size of a fingernail), it is about a quarter the size of an SD card.

The micro-SD connector supports SD and SDHC cards. SDHC (Secure Digital High Capacity, SD 2.0) is an extension of the SD standard which increases card's storage capacity up to 32GB. SDHC cards shares the same physical and electrical form factor as older (SD 1.x) cards, allowing SDHC-devices to support both newer SDHC cards and older SD-cards.

5.23 LED INDICATORS: D240 & D440 There are two bicolor LED provided with IGEP™ v2 that can be controlled by the user. In total are like 4 individual LED and 16 color schemes

Three LED are controlled via GPIO pins on the OMAP3530/DM3730 Processor

One is programmed via the I2C interface on the TPS65950

Figure 67 D440 & D244 DOUBLE LED INDICATORS LOCATION & SCHEMATIC

Signal Name LED:COLOR Description LED0 D440:RED User Application GPIO_27 LED1 D440:GREEN User Application GPIO_26 LED_POWER D240:RED Controlled by GPIO_28 LED_PMU_STAT D240:GREEN Controlled by TPS65950

DOCUMENT FROM ISEE 2007 S.L. Ref: MAN-PR-IGEP0020-RCx 54

IGEPTM v2 Hardware Reference Manual

Table 17 LED signals

6 EXPANSION CONNECTOR J990: GPIO

An option for a single 28 pin header is provided on board to allow connection of various expansion cards that could be developed by users or other sources. Due to multiplexing, different signals can be provided on each pin providing more than 24 real signal accesses

The J990 connector is a 28 pin 2x14 (dual row) 2.54mm.

Figure 68 J990 detail Pins 1, 2, 27 and 28 are labeled on PCB.

Figure 69 J990 location

DOCUMENT FROM ISEE 2007 S.L. Ref: MAN-PR-IGEP0020-RCx 55

IGEPTM v2 Hardware Reference Manual

The next schematic illustrates the pin out of the connector.

Figure 70 J990 Schematic

Using this expansion connector you have access to McBSP1, McBSP3, I2C2, MMC2 (8 bits), nReset and REGEN signals from OMAP Processor.

WARNING: J990 interface is at 1.8V on all signals. Only 1.8V CMOS levels are supported. DO NOT expose the header to higher values.

J990 connector is BeagleBoard compatible expansion connector (http://beagleboard.org), except for pins J990:4, J990:6 and J990:10 that aren’t the same signals.

Note that only IGEP™ v2 – NO WIFI board has all J990 available, other IGEP™ v2 board versions need software configuration to disable wifi interface and others because of shared hardware lines.

MMC2 interface is used by wifi module MCBSP3 interface is used by PCM TPS65950 interface.

DOCUMENT FROM ISEE 2007 S.L. Ref: MAN-PR-IGEP0020-RCx 56

IGEPTM v2 Hardware Reference Manual

If you use these signals in their respective groups and that is the only function you use, all of the signals are available. Whether or not the signals you need are all available, depends on the multiplexed function on a per-pin basis. Only one signal per pin i s available at once.

WARNING: J990 signals go directly to OMAP processor. Improper use of this connector could result on permanent damage to this processor.

J990 mates with SAMTEC HLE series for bottom entry connection:

SAMTEC HLE Serie BOTTOM ENTRY

SAMTEC SAMTEC SFMC Serie SFMC Serie

SAMTEC SAMTEC SAMTEC TSW Serie FTS Serie FTS Serie

SAMTEC HLE Serie BOTTOM ENTRY

SAMTEC SAMTEC SFMC Serie SFMC Serie SAMTEC SAMTEC SAMTEC TSW Serie FTS Serie FTS Serie

Figure 71 J990 counterparts

DOCUMENT FROM ISEE 2007 S.L. Ref: MAN-PR-IGEP0020-RCx 57

IGEPTM v2 Hardware Reference Manual

6.1 PINOUT TABLE OF EXPANSION CONNECTOR Below pin table show you pin out of IGEP™ v2 expansion connector J990, with functionalities that you can configure. Each table has several columns:

Pin #: (JJ:PP format) where JJ means J990 connector and PP means pin number.

TYPE: What kind of pin and origin silicon chip :

OMAP: processor; PMIC: power management chip; PWR: Power and ground lines

“gray shading” marked function names denote the function is already being used on board and should not be used.

“green shading” function denote is ONLY available on OMAP3530 (not on DM3730).

Functions within [] brackets on column “MODE 0” denote board pin function.

For additional details, please refer to “OMAP3530/25 Applications Processor” (www.TI.com)

Pin # TYPE MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 MODE 6 MODE 7 J990:1 PWR VIO_1 V8 J990:2 PWR DC_5V J990:3 OMAP mmc2_d at7 [Reset WiFi] mmc2_ clkin mmc3_d at3 gpio_139 hsusb3_tll_nxt mm3_rxdm safe_mode J990:4 OMAP mcbsp3_dx [TPS65950] uart2_cts gpio_140 hsusb3_tll_d4 safe_mode J990:5 OMAP mmc2_d at6 [P_Dn WiFi] mmc2_dir_c md cam_shutter mmc3_d at2 gpio_138 hsusb3_tll_dir safe_mode J990:6 OMAP mcbsp3_clkx [TPS65950] uart2_tx gpio_142 hsusb3_tll_d6 safe_mode J990:7 OMAP mmc2_d at5 [Reset BT] mmc2_ dir_d1 cam_global_rst mmc3_d at1 gpio_137 hsusb3_tll_stp mm3_rxdp safe_mode J990:8 OMAP mcbsp3_fsx [TPS65950] uart2_rx gpio_143 hsusb3_tll_d7 safe_mode J990:9 OMAP mmc2_d at4 mmc2_ dir_d0 mmc3_d at0 gpio_136 safe_mode J990:10 OMAP mcbsp3_dr [TPS65950] uart2_rts gpio_141 hsusb3_tll_d5 safe_mode J990:11 OMAP mmc2_d at3 [WiFi d ata] mcspi3_cs0 gpio_135 safe_mode J990:12 OMAP mcbsp1_dx mcspi4_simo mcbsp3_dx gpio_158 safe_mode J990:13 OMAP mmc2_d at2 [WiFi d ata] mcspi3_cs1 gpio_134 safe_mode J990:14 OMAP mcbsp1_clkx mcbsp3_clkx gpio_162 safe_mode J990:15 OMAP mmc2_d at1 [WiFi d ata] gpio_133 safe_mode J990:16 OMAP mcbsp1_fsx mcspi4_cs0 mcbsp3_fsx gpio_161 safe_mode J990:17 OMAP mmc2_d at0 [WiFi d ata] mcspi3_somi gpio_132 safe_mode J990:18 OMAP mcbsp1_dr mcspi4_somi mcbsp3_dr gpio_159 safe_mode J990:19 OMAP mmc2_c md [WiFi data] mcspi3_simo gpio_131 safe_mode J990:20 OMAP mcbsp1_clkr mcspi4_clk gpio_156 safe_mode J990:21 OMAP mmc2_clk [WiFi data] mcspi3_clk gpio_130 safe_mode J990:22 OMAP mcbsp1_fsr cam_global_reset gpio_157 safe_mode J990:23 OMAP i2c2_sda gpio_183 safe_mode J990:24 OMAP i2c2_scl gpio_168 safe_mode J990:25 PMIC pmic_regen J990:26 PMIC sys_nrespwron J990:27 PWR GND J990:28 PWR GND Table 18 Expansion Connector signals

DOCUMENT FROM ISEE 2007 S.L. Ref: MAN-PR-IGEP0020-RCx 58

IGEPTM v2 Hardware Reference Manual

7 EXPANDING IGEP™ v2 CAPABILITIES

OMAP processor functionalities can be still more expanded than in IGEP™ v2 are.

This section gives you some ideas and examples of expansion boards that you can use to expand your IGEP™ v2 possibilities. Anyway, you can use expansion connectors of your IGEP™ v2 to build your own compatible expansion boards.

7.1 IGEP™ v2 EXPANSION BOARD

ISEE offers you the possibility to use IGEP™ v2 EXPANSION board to increase the functionalities of your IGEP™ v2. This board has been designed for simplicity and is the best way to expand functionalities of your IGEP™ v2 by adding enhanced ports and additional hardware. It can be plugged easily into your board without having to engineer the components yourself. It is the perfect complement to experience with many extra features made simple and quick.

Here some of the capabilities you can add:

USB GSM/GPRS Modem for mobile communications SIM card reader VGA and DVI interface on D-SUB connector CAN bus interface with 4 pin connectors LCD and Touch Screen interface for 7" and 4" TFT displays. It can be connected directly to the Expansion Board. Serial port on DB9 connector Stereo Audio inputs and outputs RCA Analog Video inputs Digital inputs and outputs External GSM cable antenna Camera interface

We invite you to take a look to this product on our website: http://www.igep.es

DOCUMENT FROM ISEE 2007 S.L. Ref: MAN-PR-IGEP0020-RCx 59

IGEPTM v2 Hardware Reference Manual

Figure 72 IGEP™ v2 EXPANSION BOARD GENERAL VIEW

7.2 IGEP™ RADAR LAMBDA This is an example of what can be developed with your IGEP™ v2. Complex data processing needed on radars can be done in quasi real time thanks to the OMAP processor capabilities. The only interface between sensor and processor boards is EXPANSION CONNECTOR J990.

We invite you to take a look to this product on our website: http://www.igep.es

Figure 73 IGEP™ v2 RADAR LAMBDA GENERAL VIEW

DOCUMENT FROM ISEE 2007 S.L. Ref: MAN-PR-IGEP0020-RCx 60

IGEPTM v2 Hardware Reference Manual

8 MECHANICAL SPECIFICATIONS

Figure 74 IGEP™ v2 -RC Top view mechanical specification

Get Mechanical drawings on:

http://www.igep.es  User Menu  Download  01-Products  IGEPv2  HW_Mechanical

1. All dimensions are in millimeters 2. Board size is 93 x 64 mm 3. 3 mounting holes on the corners (3.6mm diameter) 4. 1,6mm pcb width 5. FR4 substrate, 8 layers

DOCUMENT FROM ISEE 2007 S.L. Ref: MAN-PR-IGEP0020-RCx 61

IGEPTM v2 Hardware Reference Manual

9 ELECTRICAL CHARACTERISTICS

Specification Min Typ Max Unit POWER SUPPLY Input Voltage DC POWER_IN 4,8 5 5,2 V Current DC (1) 600 1000 mA OMAP TYPE pins (2) Input/output High-Level DC voltage 1.2 1.8 2.1 V Input/output Low-Level DC voltage -0.3 0 0.65 V PMIC TYPE pins (3) Input/output High-Level DC voltage 1.2 1.8 2.1 V Input/output Low-Level DC voltage -0.3 0 0.65 V USB 2.0 OTG High Speed Mode (HS) 480 Mb/s Full Speed Mode (FS) 12.5 Mb/s Low Speed Mode (LS) 1.5 Mb/s PMIC_USB_OTG_VBUS & ID 0 5 5,2 V PMIC_USB_OTG_DP & DN 0 1.8 1.9 V USB 2.0 Host High Speed Mode (HS) 480 Mb/s Voltage on USB Host pins 0 5 V Output Voltage supply on USB Host pins 4,7 5 5,2 V Output Current supply on USB Hos t pins 500 mA RS485 Driver Input High Voltage 2 V Input Low Voltage 0.8 V Maximum Data Rate 250 Kbps Receiver Output Voltage High 2.8 V Output Voltage Low 0.4 V Input Resistance 12 15 KOhms JTAG Realview ICE Tool 30 MHz XDS560 30 MHz XDS510 30 MHz Lauterbach(tm) 30 MHz microSD Voltage Mode 1.8V 1.71 1.8 1.89 Voltage Mode 3.3V 3.2 3.3 Current 220 mA Clock 48 MHz DVI-D Pixel Clock Frequency 25 75 MHZ High level output voltage 3.3 V Swing output voltage 400 600 mVp-p Maximum resolution 67.5 75 82.5 Ohms Audio-In Peak-to -peak single-ended input voltage (0 dBFs) 1.5 Vpp Total harmonic distortion (sine wave @ 1.02 kHz @ -1 dBFs) -80 -75 dB Total harmonic distortion (sine wave @ 1.02 kHz) 20 Hz to 20 -85 -78 dB kHz, A-weighted audio, Gain = 0 dB Audio-Out Load Impedance @100 pF 14 16 Ohms Maximum Output Power (At 0.53 Vrms differential output 17.56 mW voltage and load impedance = 16 Ohms) Peak-to -Peak output voltage 1.5 Vpp Total Harmonic Distortion @ 0 dBFs -80 -75 dB

DOCUMENT FROM ISEE 2007 S.L. Ref: MAN-PR-IGEP0020-RCx 62

IGEPTM v2 Hardware Reference Manual

Idle channel noise (20Hz to 20KHz) -90 -85 dB Ethernet Fully compliant with IEEE 802.3/802.3u 10BASE-T and 100BASE-TX support Power supply 3.3 V Wifi IEEE802.11b Specification IEEE802.11b Frequency 2400 - 2500MHz 2400 2500 MHz Da ta ra te 1, 2, 5.5, 11 Mbps Power Levels 15.5 17.5 19.5 dBm Minimum Input Level Sensitivity 11Mbps (FER < 8%) - -87 -81 dBm Maximum Input Level -10 -5 - dBm Wifi IEEE802.11g Specification IEEE802.11g Frequency 2400 - 2500MHz 2400 2483.5 MHz Da ta ra te 6, 9, 12, 18, 24, 36, Mbps 48, 54 Power Levels 13 14.8 17.0 dBm Minimum Input Level Sensitivity 11Mbps (FER < 8%) - -71 -65 dBm Maximum Input Level -20 -15 - dBm Bluetooth 2.0 Bluetooth specification 2.0 Channel spacing 1 MHz Output Power -4 0 +4 dBm Frequency range (Rx/Tx) 2400 2483.5 MHz Sensitivity (BER≦0.1%) 1) 2402MHz - -81 -73 dBm - -81 -73 dBm 2) 2441MHz - -81 -73 dBm 3) 2480MHz - -79.5 -73 dBm C/I Performance (BER≦0.1%) 1) co-channel ratio (-60dBm input) - 7.6 11 dBm 2) 1MHz ratio (-60dBm input) - -2.5 0 dBm 3) 2MHz ratio (-60dBm input) - -42.6 -30 dBm

(1) Current Consumption with standard software. Current Consumption is highly dependent on the peripherals used. Ensure total maximum Current Consumption is lower than 1A

(2) The electrical specification depends on the configured mode. For accurate information of each pin, revise OMAP3530/25 Applications Processor official document from Texas Instruments official site http://focus.ti.com.

(3) For accurate information of each pin, revise TPS65950 DATA MANUAL official document from Texas Instruments official site http://focus.ti.com

Table 19 Electrical Characteristics

Pins with a dc power available in some connectors (VIO_1V8, DC_5V, 3V3, etc) can only drive a maximum dc current of 100mA

DOCUMENT FROM ISEE 2007 S.L. Ref: MAN-PR-IGEP0020-RCx 63

IGEPTM v2 Hardware Reference Manual

10 LIST OF TABLES Table 1 Ordering information ...... 5 Table 2 Processor ...... 8 Table 3 Memory and Storage ...... 9 Table 4 On-board connectors and devices...... 9 Table 5 Wireless connectivity ...... 9 Table 6 Power ...... 10 Table 7 Mechanical and environmental ...... 10 Table 8 IGEP™ v2 Interface summary ...... 14 Table 9 Wi-Fi/Bluetooth Interface summary...... 18 Table 10 IGEP™ v2 revision C RS232 signals in J960 connector...... 29 Table 11 JA41 Connector signals...... 36 Table 12 JA42 connector pin out ...... 37 Table 13 Camera Connector signals ...... 42 Table 14 USB OTG signals in J830 connector...... 47 Table 15 USB HOST signals in J800 connector ...... 48 Table 16 J1 links to J640 & J650 audio interface connectors ...... 51 Table 17 LED signals ...... 55 Table 18 Expansion Connector signals...... 58 Table 19 Electrical Characteristics...... 63

11 LIST OF FIGURES Figure 1 IGEP™ v2 View ...... 7 Figure 2 IGEP™ v2 GENERAL VIEW ...... 8 Figure 3 IGEP™ v2 revision C Block Diagram ...... 11 Figure 4 IGEP™ v2 revision C board top side components ...... 12 Figure 5 IGEP™ v2 revision C board bottom side components ...... 13 Figure 6 IGEP™ v2 revision C CONNECTORS MAP...... 15 Figure 7 POP Package ...... 16 Figure 8 Wi-Fi/Bluetooth Combo module block Diagram...... 17 Figure 9 U.FL series receptacle connector specification...... 21 Figure 10 U.FL series Mated connector ...... 21 Figure 11 IGEP™ v2 revision C antenna layout ...... 22 Figure 12 IGEP™ v2 revision C antenna schematic ...... 22 Figure 13 IGEP™ v2 revision C JD21, JD22 location...... 23 Figure 14 IGEP™ v2 revision C JD21, JD22 detail ...... 23 Figure 15 J200 POWER JACK CONNECTOR VIEW & DIMENSIONS ...... 24 Figure 16 J400 detail ...... 25 Figure 17 J400 location ...... 25 Figure 18 Schematic J400 ...... 25 Figure 19 J940 location ...... 26 Figure 20 J940 detail pin 1 ...... 26

DOCUMENT FROM ISEE 2007 S.L. Ref: MAN-PR-IGEP0020-RCx 64

IGEPTM v2 Hardware Reference Manual

Figure 21 Schematic J940 ...... 27 Figure 22 - Schematic RS485 driver...... 27 Figure 23 Schematic level-shifters for RS485 driver ...... 27 Figure 24 J960 detail...... 28 Figure 25 J960 location ...... 28 Figure 26 IDC-10 to DB9 cable ...... 28 Figure 27 DEBUG CABLE MODIFICATIONS (ONLY REV. C) ...... 29 Figure 28 IGEP™ v2 revision C Schematic J960...... 30 Figure 29 IGEP™ v2 revision C resistors for UART hardware selection ...... 31 Figure 30 J970 detail...... 32 Figure 31 Keyboard matrix 4x4 and schematic example ...... 32 Figure 32 J970 location ...... 33 Figure 33 Schematic J971 ...... 33 Figure 34 IGEP™ v2 revision C JA41 location ...... 34 Figure 35 IGEP™ v2 revision C JA41 and JA42 detail ...... 34 Figure 36 IGEP™ v2 revision C JA41-JA42 pin out detail ...... 34 Figure 37 IGEP™ v2 rev C Schematic of JA41 connector...... 36 Figure 38 IGEP™ v2 JA42 location ...... 37 Figure 39 IGEP™ v2 revision B and C Schematic JA42 ...... 38 Figure 40 IGEP™ v2 revision C JA41-JA42 counterparts ...... 38 Figure 41 IGEP™ v2 revision C JC20 location ...... 39 Figure 42 IGEP™ v2 revision C JC20 detail...... 39 Figure 43 IGEP™ v2 revision C schematic A/D ...... 40 Figure 44 IGEP™ v2 revision C schematic A/D SPI interface ...... 40 Figure 45 IGEP™ v2 revision C JC30 location ...... 41 Figure 46 IGEP™ v2 revision C JC30 detail...... 41 Figure 47 IGEP™ v2 revision C JC30 pin out detail ...... 41 Figure 48 IGEP™ v2 revision C JC30 schematic ...... 43 Figure 49 TP400 and TP401 schematic ...... 43 Figure 50 TP400 and TP401 location ...... 44 Figure 51 IGEP™ v2 revision C TPS65950 battery backup schematic...... 44 Figure 52 BT741 specification...... 45 Figure 53 C741 specification...... 45 Figure 54 IGEP™ v2 revision C: BT741 location...... 46 Figure 55 IGEP™ v2 revision C: C741 location ...... 46 Figure 56 R741 location ...... 46 Figure 57 J830 USB OTG CONNECTOR SIZE & PIN OUT ...... 47 Figure 58 J800 USB HOST CONNECTOR VIEW & PIN OUT...... 48 Figure 59 J1001, J1101 & J3 ETHERNET CONNECTORS VIEW & SIZE ...... 49 Figure 60 JB01 ETHERNET CONNECTOR SCHEMATIC ...... 50 Figure 61 J650 & J640 AUDIO INTERFACE ...... 50 Figure 62 J602 & J601 AUDIO CONNECTORS SCHEMATIC & SIZE ...... 51 Figure 63 Stereo Output J640 connector location ...... 52 Figure 64 Stereo Input J650 connector location ...... 52

DOCUMENT FROM ISEE 2007 S.L. Ref: MAN-PR-IGEP0020-RCx 65

IGEPTM v2 Hardware Reference Manual

Figure 65 HDMI STANDARD CONNECTOR VIEW ...... 53 Figure 66 JA01 DVI-D INTERFACE HDMI TYPE CONNECTOR SIZE & PIN OUT ...... 53 Figure 67 D440 & D244 DOUBLE LED INDICATORS LOCATION & SCHEMATIC ...... 54 Figure 68 J990 detail...... 55 Figure 69 J990 location ...... 55 Figure 70 J990 Schematic ...... 56 Figure 71 J990 counterparts ...... 57 Figure 72 IGEP™ v2 EXPANSION BOARD GENERAL VIEW ...... 60 Figure 73 IGEP™ v2 RADAR LAMBDA GENERAL VIEW ...... 60 Figure 74 IGEP™ v2 -RC Top view mechanical specification ...... 61

12 KNOWN ISSUES

13 TROUBLESHOOTING

14 CHANGE HISTORY

Revision Date Description 1.0 2012/02/15 Initial version 2.0 2013/02/06 http://bug.isee.biz/roadmap_page.php?version_id=26 0000084: [bug] Typographical mistake, industrial grade temperature is wrong in some hardware reference manuals 0000089: [bug] Typographical mistakes: J971 doesn't exist. It should be J970

Please check for a newer revision of this manual at ISEE 2007 SL web site

http://www.isee.biz

DOCUMENT FROM ISEE 2007 S.L. Ref: MAN-PR-IGEP0020-RCx 66