DM3730, DM3725 Digital Media Processors Datasheet (Rev. D)
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DM3730, DM3725 www.ti.com SPRS685D–AUGUST 2010–REVISED JULY 2011 DM3730, DM3725 Digital Media Processors Check for Samples: DM3730, DM3725 1 DM3730, DM3725 Digital Media Processors 1.1 Features 123456 • DM3730/25 Digital Media Processors: • Load-Store Architecture With – Compatible with OMAP™ 3 Architecture Non-Aligned Support – ARM® Microprocessor (MPU) Subsystem • 64 32-Bit General-Purpose Registers • Up to 1-GHz ARM® Cortex™-A8 Core • Instruction Packing Reduces Code Size Also supports 300, 600, and 800-MHz • All Instructions Conditional operation • Additional C64x+TM Enhancements • NEON™ SIMD Coprocessor – Protected Mode Operation – High Performance Image, Video, Audio – Expectations Support for Error (IVA2.2TM) Accelerator Subsystem Detection and Program Redirection • Up to 800-MHz TMS320C64x+TM DSP Core – Hardware Support for Modulo Loop Also supports 260, 520, and 660-MHz Operation operation – C64x+TM L1/L2 Memory Architecture • Enhanced Direct Memory Access (EDMA) • 32K-Byte L1P Program RAM/Cache Controller (128 Independent Channels) (Direct Mapped) • Video Hardware Accelerators • 80K-Byte L1D Data RAM/Cache (2-Way – POWERVR SGX™ Graphics Accelerator Set- Associative) (DM3730 only) • 64K-Byte L2 Unified Mapped RAM/Cache • Tile Based Architecture Delivering up to (4- Way Set-Associative) 20 MPoly/sec • 32K-Byte L2 Shared SRAM and 16K-Byte • Universal Scalable Shader Engine: L2 ROM Multi-threaded Engine Incorporating Pixel – C64x+TM Instruction Set Features and Vertex Shader Functionality • Byte-Addressable (8-/16-/32-/64-Bit Data) • Industry Standard API Support: • 8-Bit Overflow Protection OpenGLES 1.1 and 2.0, OpenVG1.0 • Bit-Field Extract, Set, Clear • Fine Grained Task Switching, Load • Normalization, Saturation, Bit-Counting Balancing, and Power Management • Compact 16-Bit Instructions • Programmable High Quality Image Anti-Aliasing • Additional Instructions to Support Complex Multiplies – Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+TM DSP Core – External Memory Interfaces: • Eight Highly Independent Functional • SDRAM Controller (SDRC) Units – 16, 32-bit Memory Controller With • Six ALUs (32-/40-Bit); Each Supports 1G-Byte Total Address Space Single 32- bit, Dual 16-bit, or Quad 8-bit, – Interfaces to Low-Power SDRAM Arithmetic per Clock Cycle – SDRAM Memory Scheduler (SMS) and • Two Multipliers Support Four 16 x 16-Bit Rotation Engine Multiplies (32-Bit Results) per Clock • General Purpose Memory Controller Cycle or Eight 8 x 8-Bit Multiplies (16-Bit (GPMC) Results) per Clock Cycle – 16-bit Wide Multiplexed Address/Data 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2POWERVR SGX is a trademark of Imagination Technologies Ltd. 3OMAP is a trademark of Texas Instruments. 4Cortex, NEON are trademarks of ARM Limited. 5ARM is a registered trademark of ARM Ltd. 6All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright © 2010–2011, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. DM3730, DM3725 SPRS685D–AUGUST 2010–REVISED JULY 2011 www.ti.com Bus • Glueless Interface to Common Video – Up to 8 Chip Select Pins With Decoders 128M-Byte Address Space per Chip • Resize Engine Select Pin – Resize Images From 1/4x to 4x – Glueless Interface to NOR Flash, – Separate Horizontal/Vertical Control NAND Flash (With ECC Hamming – System Direct Memory Access (SDMA) Code Calculation), SRAM and Controller (32 Logical Channels With Pseudo-SRAM Configurable Priority) – Flexible Asynchronous Protocol – Comprehensive Power, Reset, and Clock Control for Interface to Custom Logic Management (FPGA, CPLD, ASICs, etc.) • SmartReflexTM Technology – Nonmultiplexed Address/Data Mode • Dynamic Voltage and Frequency Scaling (Limited 2K-Byte Address Space) (DVFS) – 1.8-V I/O and 3.0-V (MMC1 only), – ARM® Cortex™-A8 Core 0.9-V to 1.2-V Adaptive Processor Core Voltage • ARMv7 Architecture ® 0.9-V to 1.1-V Adaptive Core Logic Voltage – TrustZone Note: These are default Operating – Thumb®-2 Performance Point (OPP) voltages and could – MMU Enhancements be optimized to lower values using • In-Order, Dual-Issue, Superscalar SmartReflex AVS. Microprocessor Core – Commercial, Industrial, and Extended • NEON Multimedia Architecture Temperature Grades • Over 2x Performance of ARMv6 SIMD – Serial Communication • Supports Both Integer and Floating Point • 5 Multichannel Buffered Serial Ports SIMD (McBSPs) • Jazelle® RCT Execution Environment – 512 Byte Transmit/Receive Buffer Architecture (McBSP1/3/4/5) • Dynamic Branch Prediction with Branch – 5K-Byte Transmit/Receive Buffer Target Address Cache, Global History (McBSP2) Buffer, and 8-Entry Return Stack – SIDETONE Core Support (McBSP2 and • Embedded Trace Macrocell (ETM) 3 Only) For Filter, Gain, and Mix Support for Non-Invasive Debug Operations – ARM Cortex-A8 Memory Architecture: – Direct Interface to I2S and PCM Device • 32K-Byte Instruction Cache (4-Way and T Buses Set-Associative) – 128 Channel Transmit/Receive Mode • 32K-Byte Data Cache (4-Way • Four Master/Slave Multichannel Serial Set-Associative) Port Interface (McSPI) Ports • 256K-Byte L2 Cache • High-Speed/Full-Speed/Low-Speed USB – 32K-Byte ROM OTG Subsystem (12-/8-Pin ULPI Interface) – 64K-Byte Shared SRAM • High-Speed/Full-Speed/Low-Speed Multiport USB Host Subsystem – Endianess: – 12-/8-Pin ULPI Interface or 6-/4-/3-Pin • ARM Instructions - Little Endian Serial Interface • ARM Data – Configurable • One HDQ/1-Wire Interface • DSP Instructions/Data - Little Endian • Four UARTs (One with Infrared Data • Removable Media Interfaces: Association [IrDA] and Consumer Infrared – Three Multimedia Card (MMC)/ Secure Digital [CIR] Modes) (SD) With Secure Data I/O (SDIO) • Three Master/Slave High-Speed • Test Interfaces Inter-Integrated Circuit (I2C) Controllers – IEEE-1149.1 (JTAG) Boundary-Scan – Camera Image Signal Processing (ISP) Compatible • CCD and CMOS Imager Interface – Embedded Trace Macro Interface (ETM) • Memory Data Input – Serial Data Transport Interface (SDTI) • BT.601/BT.656 Digital YCbCr 4:2:2 • 12 32-bit General Purpose Timers (8-/10-Bit) Interface • 2 32-bit Watchdog Timers 2 DM3730, DM3725 Digital Media Processors Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): DM3730 DM3725 DM3730, DM3725 www.ti.com SPRS685D–AUGUST 2010–REVISED JULY 2011 • 1 32-bit Secure Watchdog Timer • Packages: • 1 32-bit 32-kHz Sync Timer – 515-pin s-PBGA package (CBP Suffix), .5mm • Up to 188 General-Purpose I/O (GPIO) Pins Ball Pitch (Top), .4mm Ball Pitch (Bottom) (Multiplexed With Other Device Functions) – 515-pin s-PBGA package (CBC • 45-nm CMOS Technology Suffix), .65mm Ball Pitch (Top), .5mm Ball • Package-On-Package (POP) Implementation for Pitch (Bottom) Memory Stacking (Not Available in CUS – 423-pin s-PBGA package (CUS Package) Suffix), .65mm Ball Pitch Copyright © 2010–2011, Texas Instruments Incorporated DM3730, DM3725 Digital Media Processors 3 Submit Documentation Feedback Product Folder Link(s): DM3730 DM3725 DM3730, DM3725 SPRS685D–AUGUST 2010–REVISED JULY 2011 www.ti.com 1.2 Description The DM37x generation of high-performance, digital media processors are based on the enhanced device architecture and are integrated on TI's advanced 45-nm process technology. This architecture is designed to provide best in class ARM and Graphics performance while delivering low power consumption. This balance of performance and power allow the device to support the following example applications: • Portable Data Terminals • Navigation • Auto Infotainment • Gaming • Medical Imaging • Home Automation • Human Interface • Industrial Control • Test and Measurement • Single board Computers The device can support numerous HLOS and RTOS solutions including Linux and Windows Embedded CE which are available directly from TI. Additionally, the device is fully backward compatible with previous Cortex™-A8 processors and OMAP™ processors. This DM3730/25 Digital Media Processor data manual presents the electrical and mechanical specifications for the DM3730/25 Digital Media Processor. The information contained in this data manual applies to the commercial, industrial, and extended temperature versions of the DM3730/25 Digital Media Processor unless otherwise indicated. It consists of the following sections: • A description of the DM3730/25 terminals: assignment, electrical characteristics, multiplexing, and functional description • A presentation of the electrical characteristics requirements: power domains, operating conditions, power consumption, and dc characteristics • The clock specifications: input and output clocks, DPLL and DLL • A description of thermal characteristics, device nomenclature, and mechanical data about the available packaging 4 DM3730, DM3725 Digital Media Processors Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): DM3730 DM3725 DM3730, DM3725 www.ti.com SPRS685D–AUGUST 2010–REVISED JULY 2011 1.3 Functional Block Diagram The functional block diagram of the DM3730/25 Digital Media Processor is shown below. CVBS or LCD Panel S-Video Camera (Parallel) MPU IVA 2.2 Subsystem Subsystem Amp TMS320DM64x+ DSP ® ARM Imaging Video