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An Intelligent CPIB Controller

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An Intelligent CPIB Controller */oaeoooof* UNIVERSITY OF OSLD An Intelligent GPIB Control lar by J.C. Wikne Department of Physics, University of Oslo, Box 1048 Blindern, 0316 Oslo 3, Norway Report 87-42 Received 1987 - 12-23 IS3N-0332-5571 DEPARTMENT OF PHYSICS REPORT SERIES oup-%i-k% An Intelligent 6PIB Controller by J.C. Wikne Department of Physics. University of Oslo, Box 1048 Blindern. 0316 Oslo 3, Norway Report 87-42 Received 1987 - 12-23 ISSN-0332-5571 An Intelligent 6PIB Controller by J.C. Wikne Department of Physics, University of Oslo, Box 1048 Blindern, 0316 Oslo 3, Norway Report 87-42 Received 1987 - 12-23 1SSN-0332-5571 An Inttlligent GPIB Control Itr J. C. Wikne Department of Physics. University of Oslo Box 1043 Blindern, 031é Oslo 3, Norway Abstract: An intelligent. GPIB (General Purpose Interface Bus> controller is described. It employs an autonomous slaye CPU together with a dedicated control1 er/talker/1 istener chip to handle the GPIB bus protocol, thus freeing the host computer from this time-consuming task. Distributing a large part of the necessary software to the slaye side, assures that the system can be implemented on virtually any computer with a minimum of effort. Content»! »*9* 1. Introduction to the Intelligent GPIB Controller 3 2. Functional Dtscription 3 3. The High-Level Command Set 5 4. Electronic Circuit Description ? 4.1. Th* G-64 Based GPIB Controller 7 4.1.1. The Master / Slave Interface ? 4.1.2. The GPIB Controller Hardware 9 4.1.3. The Slave CPU 9 4.1.4. The PC Bus Parallel I/O Adapter * 4.2. The PC Bus GPIB Controller II 4.3. The Status Display il 5. The Slave rirmware 11 6. Host Software Interfacing 12 7. A High-Level Programming Example 13 3. Concluding Remarks 14 Reference List IS Appendix 16 A.l. Intelligent GPIB Controller Technical Specifications 17 A.2. Schematic Diagrams 18 A.3. Component Position Diagrams 26 A.4. Intelligent GPIB Controller Error Codes 30 A.5. Address Mapping of Individual Chips <Slave side) 31 A.6. Address Mapping of Master Port 31 H.7. FIFO Buffer Section Address Decoding PROM Contents 32 A.8. Controller Chip Section Address Decoding PROM Contents ... 32 A.?. PC Bus GPIB Controller Main Memory Address Decoding PROM Contents 33 A.10. Ribbon Cable I/O Bus Pinout (Tiki bus) 34 A.ll. GESMPU-5A Strap Settings 35 A. 12. G-64 Based GPIB Controller Components List 36 A.13. PC Bus GPIB Controller Components List 3? A. 14. GPIB Controller Slave CPU Program 40 A.15. MS-DOS Device Driver for GPIB Controller 65 A. 16. GPIB Address Map 73 page 2 I. Introduction to the Intelligent GPIB Controller. The Intelligent GPIB l1' Controller was originalIv developed for us* •n the Solar Energy Project at the Department of Physics. The need to preserve software investments through system upgrading from an old microcomputer to a newer one, together with problems concerning availability and high cost of commercially obtainable GPIB controllers, prompted the design of a controller that was as computer independent as possible with respect to both hardware 2nd software. The original concept resulted in a universal controller cons 1st1ng of three cards in a sub-chassis conforming to the G-64 industrial standard ,2'. plus one verv simple adapter card for the actual host computer. This system became operative on microcomputers of the Tiki 100 type |JI and on IBM PC compatibles during 1985 and 198a. The de facto dominance of micros of the latter kind that has emerged since the development started, gave rise to a "condensed" version of the controller, contained on one «ingle IBM PC/XT expansion card. £. Functional Description. A block diagram of the controller is given in fig. 1. The most important components from a functional point of view are four VLSI chips: The Z80 ("slave") CPU, the GPIB controller chip, and the two FIFO buffers. Correspondingly, the CPU employs firmware that can be divided into th'ee logical sections: The Control & Monitor program, the GPIB Chip Driver routines, and the Host Communications routines (the former and latter are contained in one physical block in the diagram). The firmware is largely interrupt-dri ven, to assure maximum speed and flexibility. All functions directly related to the GPIB bus are performed by the slave CPU, thus relieving the host of these tasks. The slave's operation is controlled by the host through simple, high-level commands. Moreover, with only minor firmware modifications these commands can be made to mimic those of any commercially available GPIB control ler. The controller communicates asynchronously with the host computer through a parallel I/O-port or optionally a serial RS-232 link. The serial port can also be connected to a dumb terminal, in which case the Monitor firmware facilitates interactive use. The parallel 2/0 port is a standard 230 PIO, which is interfaced physically to almost any host CPU-bus by means of hardware (Host Adapter block) ranging in complexity from simple cables/connectors to a circuit board containing typically 5 SSI/MSI chips. The FIFOs of up to 2k depth assure that both the host computer and the slave CPU to a large extent can run at their own pace. The GPIB controller chip and transceivers handle the actual, physical interfacing to the GPIB bus, including all necessary protocols to conform to the IEEE-483/2 standard. page 3 Intelligent GPIB Controller Block Diagram « C If) G-64 OERSION ONLY 3. The High-Level Command Set. The present -firmware (Rev. 1 .01 > for the GPIB controller ha* been designed to mimic the instruction set of the ABC80 microcomputer •«,«>. These instructions are sent to the controller via either the parallel or the serial port, have a maximum length <including parameters) of 32 characters, and are terminated by CR-LF. The instruction set is given in the table below. Angular brackets denote parameter fields, and are NOT part oi th* parameter itself. OPEN tt Initializes controller and opens communication. CLOSE It Stops communication. CMD <*1>,<*2>. It Sends the strings SI, *2.... on the GPIB bus. tt The strings are sent al ternat i ngl y as bus tt commands <ATN active) and bus data (ATM tt passive) CI). Strings can be specified either tt as ASCII characters enclosed in quoting signs, tt or as sequences of decimal ASCII values, tt Examples: "WXYZ", "!*•&", CHR*(1,2,3,255). IEC*(<N>) tt Reads N characters on the GPIB, as transmitted tt by an instrument in TAD mode (1). N € CI,323. tt After reading, the characters are transferred tt to the host. T<N> tt Sets the timeout for response from instruments tt on the GPIB. N is a decimal number, N i Cl.91. tt THe actual timeout is T % N-4ms. TO Sets timeout to none. S? tt Serial polls all instruments. The response is tt a string of the format MTA=A STB=XXXXXXXX &*. tt Here A is the talk address of ths instrument # whose status is returned (the first one with tt RQS active, if any), XXXXXXXX is the status tt byte in binary, & (if present) is an explicit tt indication of RGS active, and * (if present) tt indicates that 3RQ is still active after the tt poll. S<A> tt Serial polls instrument with talk address A. # Response as for the previous command. Sa # Enables automatic SRQ handling. This means # that the command S? is executed automatically tt when a SRQ is asserted by an instrument. Sm Disables automatic SRQ handlino. P? tt Executes a parallel poll. The response is a # string of format PPR=XXXXXXXX, where XXXXXXXX tt is the status byte. <Esc> H CONSOLE (serial port) INSTRUCTION ONLY' tt Escape character. Instructs the Control & tt Monitor program to receive further instructions tt from the console. When this command is given, page 5 » the Noni tor displays • heading on tn* ccnmU W terminal, and then the command prompt GH6'. M The controller ic now in • mode .«here it can e>« l» operated interactively, for instance 'or debug N purposes. OUIT * CONSOLE (serial port) INSTRUCTION ONLY tt Instructs the Control & Monitor program to U receive further instructions from the parallel # por t. The controller notifies the host of anv error conditions detected through ths error codes given in appendix A.4. pacie 6 4. Electronic Circuit Description. For th* following discussion, ptea.se rtftr to the detailed diagrams figs. 3-*, given in appendix A.S. 4.1. The G-64 Based GPIB Controller. A block, diagram showing the three-card structure of thii version ot the controller is given in fig. 2. 4.1.1. The Master / Slave Interface. The schematic diagram of the G-64 bus compatible Master / SI»"* interface card is given in fig. 3. It employs a Z80 PIO, U005, as a parallel interface port to the adapted host bus. The PROM U017 is the address decoder for the port as seen from the host (master) side. For the possible address mappings available through jumper settings, please refer to appendix A.6. For information concerning the interface connector POS, see section 4.1.4 and appendix A.10. The 512 bvte deep FIFO buffers that separate the master from the slave and assure largely independent data flow rates, U004 and UO11, are of type IDT720! from Integrated Device Technology <«>. Pin compatible devices with depths of up to 2k are available. The COST (COntrol -and STatus) buffer U00S provides a "mailbox" function for passing special messages from the host PIO's B-port and the FIFOs' full/empty .flags onto the G-64 bus.
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