DOCSLIB.ORG

Speculative Symbolic Execution for Cache Timing Leak Detection

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Speculative Symbolic Execution for Cache Timing Leak Detection SpecuSym: Speculative Symbolic Execution for Cache Timing Leak Detection Shengjian Guo∗ Yueqi Chen∗ Peng Li, Yueqiang Cheng Baidu Security Penn State University Baidu Security [email protected] [email protected] {lipeng28,chengyueqiang}@baidu. com Huibo Wang Meng Wu Zhiqiang Zuo Baidu Security Ant Financial Services Group State Key Lab. for Novel Software [email protected] [email protected] Technology, Nanjing University [email protected] ABSTRACT leverage the distinct cache physical symptoms, i.e., the cache visit- CPU cache is a limited but crucial storage component in modern ing latencies of various program executions, to penetrate the con- processors, whereas the cache timing side-channel may inadver- fidentiality of the victims. On exploiting the vulnerable software tently leak information through the physically measurable timing implementations, adversaries can extract the application secrets variance. Speculative execution, an essential processor optimiza- [16, 36, 60, 69], infer the neural network structure [30, 40, 41, 79], tion, and a source of such variances, can cause severe detriment or even dump the kernel data [42, 46, 52, 75]. on deliberate branch mispredictions. Despite static analysis could A timing side-channel generally serves as the intermediate car- qualitatively verify the timing-leakage-free property under specula- rier through which private data could inadvertently disclose to tive execution, it is incapable of producing endorsements including observers who can elaborately measure the timing information inputs and speculated flows to diagnose leaks in depth. This work of certain operations. One particular instance is the cache timing proposes a new symbolic execution based method, SpecuSym, for side-channel, which leaks data by the variance of the cache visit- precisely detecting cache timing leaks introduced by speculative ing latency. State-of-the-art program repair method [77] mitigates execution. Given a program (leakage-free in non-speculative exe- cache timing leaks by enforcing constant execution time for all cution), SpecuSym systematically explores the program state space, secret relevant operations. However, this strong mitigation may models speculative behavior at conditional branches, and accumu- still get compromised by the thread-level concurrency [38] or the lates the cache side effects along with subsequent path explorations. instruction-level parallelism like speculative execution [44]. During the dynamic execution, SpecuSym constructs leak predi- Speculative execution [44] is a microarchitectural optimization cates for memory visits according to the specified cache model in modern processors. It primarily increases the CPU instruction and conducts a constraint-solving based cache behavior analysis to pipeline throughput by beforehand scheduling instructions under inspect the new cache behaviors. We have implemented SpecuSym predicted branches, which prevents control hazards from stalling atop KLEE and evaluated it against 15 open-source benchmarks. the pipeline. Despite its essential importance, the cache side ef- Experimental results show that SpecuSym successfully detected fects caused by prediction errors could engender severe detriment from 2 to 61 leaks in 6 programs under 3 different cache settings through the cache timing side-channel [15, 43, 46, 75]. and identified false positives in 2 programs reported by recent work. Program analysis for speculative execution is by no means a new research domain. Previous efforts mainly researched safe and effi- cient execution [22, 35, 64], worst-case execution time estimation 1 INTRODUCTION [50, 51], concurrency bug prediction [21, 49], and Spectre vulner- CPU cache is a limited but crucial storage area on modern processor ability detection [35, 58, 71]. Wu et al. [78] recently proposed a chips. It primarily relieves the speed disparity between the rapid dedicated static analysis of timing-leakage-free property under processors and the slow main memory, by buffering recently used speculative execution. However, this abstract interpretation based arXiv:1911.00507v2 [cs.CR] 14 Feb 2020 data for faster reuse. Cache timing side-channel attacks [26, 47] method [78] qualitatively answers the yes or no question — it is incapable of generating input and speculative flows to diagnose leaks in depth. Moreover, the over-approximation nature inevitably ∗Both authors contributed equally to this research. Yueqi Chen worked on this project while he interned at Baidu USA. results in false positives, which desires a more precise method. To this end, we propose a new symbolic execution based method, SpecuSym, for detecting cache timing leaks caused by speculative Permission to make digital or hard copies of all or part of this work for personal or execution. Figure 1 displays the overall flow of SpecuSym. Given a classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation program P, which is timing-leakage-free in non-speculative execu- on the first page. Copyrights for components of this work owned by others than ACM tion, the sensitive input presented in symbol, and the insensitive must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, input, SpecuSym leverages symbolic execution to explore P’s state to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]. space systematically. Meanwhile, it models speculative execution ICSE ’20, May 23–29, 2020, Seoul, Republic of Korea at conditional branches (cf. 1 ) and accumulates cache side effects © 2020 Association for Computing Machinery. along with subsequent executions (cf. 2 ). Based on a cache model, ACM ISBN 978-1-4503-7121-6/20/05...$15.00 https://doi.org/10.1145/3377811.3380428 ICSE ’20, May 23–29, 2020, Seoul, Republic of Korea Guo et al. 1 Section 4 states the core contributions and optimizations. Then we Speculative Symbolic Execution Modeling conduct experiments in Section 5 and discuss the related work in Sensitive Input Section 6. Finally, we conclude our work in Section 7. 3 4 Leakage-free Symbolic Cache New Timing Program P Execution Behavior Analysis Leak Witnesses 2 MOTIVATION This section motivates our work with an example. By studying its Insensitive 2 leakage-free cache behavior under non-speculative execution and Plain Input Cache the new leaks caused by speculative execution, we position how State Modeling SpecuSym should facilitate leak detection. P Figure 1: Overall flow of SpecuSym. 2.1 Program and the Cache Mapping Figure 2(a) shows a program snippet P whose execution time re- mains stationary in non-speculative execution but varies in terms SpecuSym constructs leak predicates for memory visits and con- of the sensitive input when running under speculative execution. ducts a constraint-solving based cache behavior analysis (cf. 3 ) to Listed at line 2, P has 4 local variables as S, x, v1, and v2. Op- generate the leak witnesses (cf. 4 ). erating these variables, e.g., the implicit memory read of x (line Our new method has three significant challenges. The first chal- 6) and the explicit store to v1 (line 7), may lead to memory access. lenge comes from the modeling of speculative behaviors. Classic The remaining variable i (line 3) is a register variable that incurs symbolic executors [17, 62] neither support speculative execution no memory access. Also, variable x is the sensitive input, and any nor are cache-aware since they primarily concentrate on the func- form of revealing its value turns to be a leak. tional correctness rather than reasoning the implicit program prop- We leverage a fully associative cache C for the analysis purpose erties. The second challenge derives from the cache state mainte- of P, as shown in Figure 2(b). It is an extreme case of the N-way nance. Due to the symbolic nature, a symbolic memory address associative cache where the memory address of a variable in P may correspond to multiple concrete addresses. Updating the cache may map to any cache line of C, subjecting to the line availability status after each memory operation unquestionably leads to an and the replacement policy. Here we assume C adopts the Least explosive number of different cache states. The last challenge stems Recently Used (LRU) policy, which always evicts the least used line from the analysis cost. Processors may trigger multiple branch mis- once C has been entirely occupied. predictions during program execution. Indiscriminately covering Cache C consists of 256 cache lines, and each line has exactly 1- all possibilities introduces not only tremendous constraint solving byte size. Local variables are mapped to C according to the program overhead but also many unnecessary cases. execution order and their sizes; e.g., in Figure 2(b) array S maps To overcome the first challenge, we design a new modeling al- from cache lines #1 to #254 because of the array traverse in the while gorithm in symbolic execution, which satisfies both feasibility and loop (lines 4-5), and each 1-byte array item successively occupies a high-fidelity. In essence, it utilizes the stateful exploration tomimic full cache line. Then variable x associates with line #255. Next, v1 the speculative behaviors and isolates memory changes in auxil- fills the last available line (line #256) if x>128 satisfies; thus, the iary states from the normal symbolic states. To tackle the second
Load more

Recommended publications
  • Computer Science 246 Computer Architecture Spring 2010 Harvard University
    Computer Science 246 Computer Architecture Spring 2010 Harvard University Instructor: Prof. David Brooks [email protected] Dynamic Branch Prediction, Speculation, and Multiple Issue Computer Science 246 David Brooks Lecture Outline • Tomasulo’s Algorithm Review (3.1-3.3) • Pointer-Based Renaming (MIPS R10000) • Dynamic Branch Prediction (3.4) • Other Front-end Optimizations (3.5) – Branch Target Buffers/Return Address Stack Computer Science 246 David Brooks Tomasulo Review • Reservation Stations – Distribute RAW hazard detection – Renaming eliminates WAW hazards – Buffering values in Reservation Stations removes WARs – Tag match in CDB requires many associative compares • Common Data Bus – Achilles heal of Tomasulo – Multiple writebacks (multiple CDBs) expensive • Load/Store reordering – Load address compared with store address in store buffer Computer Science 246 David Brooks Tomasulo Organization From Mem FP Op FP Registers Queue Load Buffers Load1 Load2 Load3 Load4 Load5 Store Load6 Buffers Add1 Add2 Mult1 Add3 Mult2 Reservation To Mem Stations FP adders FP multipliers Common Data Bus (CDB) Tomasulo Review 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 LD F0, 0(R1) Iss M1 M2 M3 M4 M5 M6 M7 M8 Wb MUL F4, F0, F2 Iss Iss Iss Iss Iss Iss Iss Iss Iss Ex Ex Ex Ex Wb SD 0(R1), F0 Iss Iss Iss Iss Iss Iss Iss Iss Iss Iss Iss Iss Iss M1 M2 M3 Wb SUBI R1, R1, 8 Iss Ex Wb BNEZ R1, Loop Iss Ex Wb LD F0, 0(R1) Iss Iss Iss Iss M Wb MUL F4, F0, F2 Iss Iss Iss Iss Iss Ex Ex Ex Ex Wb SD 0(R1), F0 Iss Iss Iss Iss Iss Iss Iss Iss Iss M1 M2
    [Show full text]
  • OS and Compiler Considerations in the Design of the IA-64 Architecture
    OS and Compiler Considerations in the Design of the IA-64 Architecture Rumi Zahir (Intel Corporation) Dale Morris, Jonathan Ross (Hewlett-Packard Company) Drew Hess (Lucasfilm Ltd.) This is an electronic reproduction of “OS and Compiler Considerations in the Design of the IA-64 Architecture” originally published in ASPLOS-IX (the Ninth International Conference on Architectural Support for Programming Languages and Operating Systems) held in Cambridge, MA in November 2000. Copyright © A.C.M. 2000 1-58113-317-0/00/0011...$5.00 Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full cita- tion on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, to republish, to post on servers, or to redistribute to lists, requires prior specific permis- sion and/or a fee. Request permissions from Publications Dept, ACM Inc., fax +1 (212) 869-0481, or [email protected]. ASPLOS 2000 Cambridge, MA Nov. 12-15 , 2000 212 OS and Compiler Considerations in the Design of the IA-64 Architecture Rumi Zahir Jonathan Ross Dale Morris Drew Hess Intel Corporation Hewlett-Packard Company Lucas Digital Ltd. 2200 Mission College Blvd. 19447 Pruneridge Ave. P.O. Box 2459 Santa Clara, CA 95054 Cupertino, CA 95014 San Rafael, CA 94912 [email protected] [email protected] [email protected] [email protected] ABSTRACT system collaborate to deliver higher-performance systems.
    [Show full text]
  • Selective Eager Execution on the Polypath Architecture
    Selective Eager Execution on the PolyPath Architecture Artur Klauser, Abhijit Paithankar, Dirk Grunwald [klauser,pvega,grunwald]@cs.colorado.edu University of Colorado, Department of Computer Science Boulder, CO 80309-0430 Abstract average misprediction latency is the sum of the architected latency (pipeline depth) and a variable latency, which depends on data de- Control-flow misprediction penalties are a major impediment pendencies of the branch instruction. The overall cycles lost due to high performance in wide-issue superscalar processors. In this to branch mispredictions are the product of the total number of paper we present Selective Eager Execution (SEE), an execution mispredictions incurred during program execution and the average model to overcome mis-speculation penalties by executing both misprediction latency. Thus, reduction of either component helps paths after diffident branches. We present the micro-architecture decrease performance loss due to control mis-speculation. of the PolyPath processor, which is an extension of an aggressive In this paper we propose Selective Eager Execution (SEE) and superscalar, out-of-order architecture. The PolyPath architecture the PolyPath architecture model, which help to overcome branch uses a novel instruction tagging and register renaming mechanism misprediction latency. SEE recognizes the fact that some branches to execute instructions from multiple paths simultaneously in the are predicted more accurately than others, where it draws from re- same processor pipeline, while retaining maximum resource avail- search in branch confidence estimation [4, 6]. SEE behaves like ability for single-path code sequences. a normal monopath speculative execution architecture for highly Results of our execution-driven, pipeline-level simulations predictable branches; it predicts the most likely successor path of a show that SEE can improve performance by as much as 36% for branch, and evaluates instructions only along this path.
    [Show full text]
  • Igpu: Exception Support and Speculative Execution on Gpus
    Appears in the 39th International Symposium on Computer Architecture, 2012 iGPU: Exception Support and Speculative Execution on GPUs Jaikrishnan Menon, Marc de Kruijf, Karthikeyan Sankaralingam Department of Computer Sciences University of Wisconsin-Madison {menon, dekruijf, karu}@cs.wisc.edu Abstract the evolution of traditional CPUs to illuminate why this pro- gression appears natural and imminent. Since the introduction of fully programmable vertex Just as CPU programmers were forced to explicitly man- shader hardware, GPU computing has made tremendous age CPU memories in the days before virtual memory, for advances. Exception support and speculative execution are almost a decade, GPU programmers directly and explicitly the next steps to expand the scope and improve the usabil- managed the GPU memory hierarchy. The recent release ity of GPUs. However, traditional mechanisms to support of NVIDIA’s Fermi architecture and AMD’s Fusion archi- exceptions and speculative execution are highly intrusive to tecture, however, has brought GPUs to an inflection point: GPU hardware design. This paper builds on two related in- both architectures implement a unified address space that sights to provide a unified lightweight mechanism for sup- eliminates the need for explicit memory movement to and porting exceptions and speculation on GPUs. from GPU memory structures. Yet, without demand pag- First, we observe that GPU programs can be broken into ing, something taken for granted in the CPU space, pro- code regions that contain little or no live register state at grammers must still explicitly reason about available mem- their entry point. We then also recognize that it is simple to ory. The drawbacks of exposing physical memory size to generate these regions in such a way that they are idempo- programmers are well known.
    [Show full text]
  • A Survey of Published Attacks on Intel
    1 A Survey of Published Attacks on Intel SGX Alexander Nilsson∗y, Pegah Nikbakht Bideh∗, Joakim Brorsson∗zx falexander.nilsson,pegah.nikbakht_bideh,[email protected] ∗Lund University, Department of Electrical and Information Technology, Sweden yAdvenica AB, Sweden zCombitech AB, Sweden xHyker Security AB, Sweden Abstract—Intel Software Guard Extensions (SGX) provides a Unfortunately, a relatively large number of flaws and attacks trusted execution environment (TEE) to run code and operate against SGX have been published by researchers over the last sensitive data. SGX provides runtime hardware protection where few years. both code and data are protected even if other code components are malicious. However, recently many attacks targeting SGX have been identified and introduced that can thwart the hardware A. Contribution defence provided by SGX. In this paper we present a survey of all attacks specifically targeting Intel SGX that are known In this paper, we present the first comprehensive review to the authors, to date. We categorized the attacks based on that includes all known attacks specific to SGX, including their implementation details into 7 different categories. We also controlled channel attacks, cache-attacks, speculative execu- look into the available defence mechanisms against identified tion attacks, branch prediction attacks, rogue data cache loads, attacks and categorize the available types of mitigations for each presented attack. microarchitectural data sampling and software-based fault in- jection attacks. For most of the presented attacks, there are countermeasures and mitigations that have been deployed as microcode patches by Intel or that can be employed by the I. INTRODUCTION application developer herself to make the attack more difficult (or impossible) to exploit.
    [Show full text]
  • SUPPORT for SPECULATIVE EXECUTION in HIGH- PERFORMANCE PROCESSORS Michael David Smith Technical Report: CSL-TR-93456 November 1992
    SUPPORT FOR SPECULATIVE EXECUTION IN HIGH- PERFORMANCE PROCESSORS Michael David Smith Technical Report: CSL-TR-93456 November 1992 Computer Systems Laboratory Departments of Electrical Engineering and Computer Science Stanford University Stanford, California 94305-4055 Abstract Superscalar and superpipelining techniques increase the overlap between the instructions in a pipelined processor, and thus these techniques have the potential to improve processor performance by decreasing the average number of cycles between the execution of adjacent instructions. Yet, to obtain this potential performance benefit, an instruction scheduler for this high-performance processor must find the independent instructions within the instruction stream of an application to execute in parallel. For non-numerical applications, there is an insufficient number of independent instructions within a basic block, and consequently the instruction scheduler must search across the basic block boundaries for the extra instruction-level parallelism required by the superscalar and superpipelining techniques. To exploit instruction-level parallelism across a conditional branch, the instruction scheduler must support the movement of instructions above a conditional branch, and the processor must support the speculative execution of these instructions. We define boosting, an architectural mechanism for speculative execution, that allows us to uncover the instruction-level parallelism across conditional branches without adversely affecting the instruction count of the application
    [Show full text]
  • High Performance Architecture Using Speculative Threads and Dynamic Memory Management Hardware
    HIGH PERFORMANCE ARCHITECTURE USING SPECULATIVE THREADS AND DYNAMIC MEMORY MANAGEMENT HARDWARE Wentong Li Dissertation Prepared for the Degree of DOCTOR OF PHILOSOPHY UNIVERSITY OF NORTH TEXAS December 2007 APPROVED: Krishna Kavi, Major Professor and Chair of the Department of Computer Science and Engineering Phil Sweany, Minor Professor Robert Brazile, Committee Member Saraju P. Mohanty, Committee Member Armin R. Mikler, Departmental Graduate Coordinator Oscar Garcia, Dean of College of Engineering Sandra L. Terrell, Dean of the Robert B. Toulouse School of Graduate Studies Li, Wentong, High Performance Architecture using Speculative Threads and Dynamic Memory Management Hardware. Doctor of Philosophy (Computer Science), December 2007, 114 pp., 28 tables, 27 illustrations, bibliography, 82 titles. With the advances in very large scale integration (VLSI) technology, hundreds of billions of transistors can be packed into a single chip. With the increased hardware budget, how to take advantage of available hardware resources becomes an important research area. Some researchers have shifted from control flow Von-Neumann architecture back to dataflow architecture again in order to explore scalable architectures leading to multi-core systems with several hundreds of processing elements. In this dissertation, I address how the performance of modern processing systems can be improved, while attempting to reduce hardware complexity and energy consumptions. My research described here tackles both central processing unit (CPU) performance and memory subsystem performance. More specifically I will describe my research related to the design of an innovative decoupled multithreaded architecture that can be used in multi-core processor implementations. I also address how memory management functions can be off-loaded from processing pipelines to further improve system performance and eliminate cache pollution caused by runtime management functions.
    [Show full text]
  • Whitepaper Cache Speculation Side-Channels Author: Richard Grisenthwaite Date: January 2018 Version 1.1
    Whitepaper Cache Speculation Side-channels Author: Richard Grisenthwaite Date: January 2018 Version 1.1 Introduction This whitepaper looks at the susceptibility of Arm implementations following recent research findings from security researchers at Google on new potential cache timing side-channels exploiting processor speculation. This paper also outlines possible mitigations that can be employed for software designed to run on existing Arm processors. Overview of speculation-based cache timing side-channels Cache timing side-channels are a well understood concept in the area of security research. As such, this whitepaper will provide a simple conceptual overview rather than an in-depth explanation. The basic principle behind cache timing side-channels is that the pattern of allocations into the cache, and, in particular, which cache sets have been used for the allocation, can be determined by measuring the time taken to access entries that were previously in the cache, or by measuring the time to access the entries that have been allocated. This then can be used to determine which addresses have been allocated into the cache. The novelty of speculation-based cache timing side-channels is their use of speculative memory reads. Speculative memory reads are typical of advanced micro-processors and part of the overall functionality which enables very high performance. By performing speculative memory reads to cacheable locations beyond an architecturally unresolved branch (or other change in program flow), and, further, the result of those reads can themselves be used to form the addresses of further speculative memory reads. These speculative reads cause allocations of entries into the cache whose addresses are indicative of the values of the first speculative read.
    [Show full text]
  • Invisispec: Making Speculative Execution Invisible in the Cache Hierarchy
    InvisiSpec: Making Speculative Execution Invisible in the Cache Hierarchy Mengjia Yany, Jiho Choiy, Dimitrios Skarlatos, Adam Morrison∗, Christopher W. Fletcher, and Josep Torrellas University of Illinois at Urbana-Champaign ∗Tel Aviv University fmyan8, jchoi42, [email protected], [email protected], fcwfletch, [email protected] yAuthors contributed equally to this work. Abstract— Hardware speculation offers a major surface for the attacker’s choosing. Different types of attacks are possible, micro-architectural covert and side channel attacks. Unfortu- such as the victim code reading arbitrary memory locations nately, defending against speculative execution attacks is chal- by speculating that an array bounds check succeeds—allowing lenging. The reason is that speculations destined to be squashed execute incorrect instructions, outside the scope of what pro- the attacker to glean information through a cache-based side grammers and compilers reason about. Further, any change to channel, as shown in Figure 1. In this case, unlike in Meltdown, micro-architectural state made by speculative execution can leak there is no exception-inducing load. information. In this paper, we propose InvisiSpec, a novel strategy to 1 // cache line size is 64 bytes defend against hardware speculation attacks in multiprocessors 2 // secret value V is 1 byte 3 // victim code begins here: Fig. 1: Spectre variant 1 at- by making speculation invisible in the data cache hierarchy. 4 uint8 A[10]; tack example, where the at- InvisiSpec blocks micro-architectural covert and side channels 5 uint8 B[256∗64]; tacker obtains secret value V through the multiprocessor data cache hierarchy due to specula- 6 // B size : possible V values ∗ line size 7 void victim ( size t a) f stored at address X.
    [Show full text]
  • A State of the Art Investigation
    Report Type Deliverable D1.1 Report Name A State-of-the-Art Investigation Dissemination Level Public Status Final Version Number 1.0 Date of Preparation 16th October 2019 CyReV (Dnr 2018-05013) Deliverable D1.2 - A State-of-the-Art Investigation ©2019 The CyReV Consortium ii Executive Summary This deliverable (D1.1 State-of-the-Art Investigation) presents the results and achieve- ments of sub-work package WP1.1 (State of the art) of the CyReV project. The goal of this deliverable is to provide insight into the state of current research frontiers in security and resiliency for vehicles and vehicular security. It also serves as an introduction to the issues faced in the automotive domain with an extensive reference list for more detailed studies. Finally, it can be used as background on which to base further investigations. The FFI HOLIstic Approach to Improve Data SECurity (HoliSec) project produced the deliverable “D1.2 State of the art”, CyReV uses this deliverable as a baseline and extends the current state of the art in regards to resiliency. The report includes discussions about hardware and operating system level secur- ity, internal and external communication security, intrusion detection systems, secure software development, and related research projects. Many topics are discussed very briefly, since an exhaustive treatment of each would certainly be out of the scope of this deliverable. iii CyReV (Dnr 2018-05013) Deliverable D1.2 - A State-of-the-Art Investigation ©2019 The CyReV Consortium iv Contributors Editor(s) Affiliation Email
    [Show full text]
  • Speculative Execution and Instruction-Level Parallelism
    M A R C H 1 9 9 4 WRL Technical Note TN-42 Speculative Execution and Instruction-Level Parallelism David W. Wall d i g i t a l Western Research Laboratory 250 University Avenue Palo Alto, California 94301 USA The Western Research Laboratory (WRL) is a computer systems research group that was founded by Digital Equipment Corporation in 1982. Our focus is computer science research relevant to the design and application of high performance scientific computers. We test our ideas by designing, building, and using real systems. The systems we build are research prototypes; they are not intended to become products. There is a second research laboratory located in Palo Alto, the Systems Research Cen- ter (SRC). Other Digital research groups are located in Paris (PRL) and in Cambridge, Massachusetts (CRL). Our research is directed towards mainstream high-performance computer systems. Our prototypes are intended to foreshadow the future computing environments used by many Digital customers. The long-term goal of WRL is to aid and accelerate the development of high-performance uni- and multi-processors. The research projects within WRL will address various aspects of high-performance computing. We believe that significant advances in computer systems do not come from any single technological advance. Technologies, both hardware and software, do not all advance at the same pace. System design is the art of composing systems which use each level of technology in an appropriate balance. A major advance in overall system performance will require reexamination of all aspects of the system. We do work in the design, fabrication and packaging of hardware; language processing and scaling issues in system software design; and the exploration of new applications areas that are opening up with the advent of higher performance systems.
    [Show full text]
  • PA-RISC 8X00 Family of Microprocessors with Focus on PA-8700
    PA-RISC 8x00 Family of Microprocessors with Focus on PA-8700 Technical White Paper April 2000 1 Preliminary PA-8700 circuit information — production system specifications may differ Table of Contents 1. PA-RISC: Betting the House and Winning...............................................3 2. RISC Philosophy ........................................................................................4 Clock Frequency ............................................................................................................................................................4 VLSI Integration..............................................................................................................................................................4 Architectural Enhancements ........................................................................................................................................5 3. Evolution of the PA-RISC Family ..............................................................6 4. Key Highlights from PA-8000 to PA-8600.................................................7 5. PA-8700 Feature Set Highlights ................................................................8 Large Robust Primary Caches.....................................................................................................................................9 Data Integrity - Error Detection and Error Correction Capabilities ........................................................................10 Static and Dynamic Branch Prediction - Faster Program
    [Show full text]