DOCSLIB.ORG

Igpu: Exception Support and Speculative Execution on Gpus

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Igpu: Exception Support and Speculative Execution on Gpus Appears in the 39th International Symposium on Computer Architecture, 2012 iGPU: Exception Support and Speculative Execution on GPUs Jaikrishnan Menon, Marc de Kruijf, Karthikeyan Sankaralingam Department of Computer Sciences University of Wisconsin-Madison {menon, dekruijf, karu}@cs.wisc.edu Abstract the evolution of traditional CPUs to illuminate why this pro- gression appears natural and imminent. Since the introduction of fully programmable vertex Just as CPU programmers were forced to explicitly man- shader hardware, GPU computing has made tremendous age CPU memories in the days before virtual memory, for advances. Exception support and speculative execution are almost a decade, GPU programmers directly and explicitly the next steps to expand the scope and improve the usabil- managed the GPU memory hierarchy. The recent release ity of GPUs. However, traditional mechanisms to support of NVIDIA’s Fermi architecture and AMD’s Fusion archi- exceptions and speculative execution are highly intrusive to tecture, however, has brought GPUs to an inflection point: GPU hardware design. This paper builds on two related in- both architectures implement a unified address space that sights to provide a unified lightweight mechanism for sup- eliminates the need for explicit memory movement to and porting exceptions and speculation on GPUs. from GPU memory structures. Yet, without demand pag- First, we observe that GPU programs can be broken into ing, something taken for granted in the CPU space, pro- code regions that contain little or no live register state at grammers must still explicitly reason about available mem- their entry point. We then also recognize that it is simple to ory. The drawbacks of exposing physical memory size to generate these regions in such a way that they are idempo- programmers are well known. Other issues like debugging tent, allowing their entry points to function as program re- and supporting arithmetic exceptions are likely to emerge as covery points and enabling support for exception handling, problems for future GPUs as well. Exception support is a fast context switches, and speculation, all with very low fundamental pillar of modern CPUs and is used to provide overhead. We call the architecture of GPUs executing these all of the above features. To make the leap to becoming idempotent regions the iGPU architecture. The hardware a truly general-purpose programming platform, we believe extensions required are minimal and the construction of future GPUs will require robust exception support to enable idempotent code regions is fully transparent under the typ- virtual memory, and will significantly benefit from this sup- ical dynamic compilation framework of GPUs. We demon- port in other areas as well. strate how iGPU exception support enables virtual memory Modern GPUs are also positioned to benefit from spec- paging with very low overhead (1% to 4%), and how spec- ulation support in the near future. Shortly after the devel- ulation support enables circuit-speculation techniques that opment of exception support in CPUs, speculation was de- can provide over 25% reduction in energy. veloped as a mechanism to transparently handle “difficult” code, and a recent study claims that GPUs must similarly 1 Introduction begin incorporating techniques like speculation to expand the domains they can target [6]. Speculation support has Since the introduction of fully programmable vertex also increasingly been proposed for handling recovery from shader hardware [23], GPU computing has made enormous hardware reliability problems in CPUs [4, 17, 30]. Such strides. Modern GPUs incorporate sophisticated architec- problems, which include variability, noise, and excessive ture and microarchitecture techniques such as predication, guard-banding, are also emerging problems for GPUs [7]. caching, and prefetching, while abstracting the details away However, recent work on GPU solutions to overcome these from programmers through their software stack and dy- problems still has at least 40% overheads [35]. As with namic compilation approach. To improve the effectiveness CPUs, efficient speculation support in GPUs can serve as of GPUs as general-purpose computing devices, GPU pro- a fundamental primitive that enables support for a more di- gramming models and architectures continue to evolve, and verse range of application programs and handling of hard- we foresee exception support and speculative execution as ware reliability issues. the next key steps in their evolution. Below, we reflect on 1 1.1 Key Challenges respect to the program’s execution. On CPUs, this problem is handled simply by incorporating large hardware check- Exception support and speculative execution can expand pointing or buffering structures to manage speculative state. the scope and improve the usability of GPUs. However, The MIPS R10K for example, implements checkpointing implementing them efficiently on GPUs presents key chal- by maintaining four copies of the register rename table [41]. lenges. Below, we discuss exception and speculation sup- However, the amount of register state on GPUs is simply too port in CPUs and why CPU mechanisms are problematic to vast to consider this option. Hence, a third key challenge apply directly to GPUs. The three key challenges we iden- is supporting speculative writes: finding a way to manage tify are: consistent exception state, efficient context switch- large amounts of speculative program state. ing, and speculative writes. For CPUs, the problem of exception support was solved 1.2 Paper Overview at a relatively early stage [36, 38]. This support was a key enabler to their success, and instrumental in this success In this paper, we develop a low-overhead technique to was the definition of precise exception handling, where an support exceptions and speculative execution on GPUs. exception is handled precisely if, with respect to the except- Fundamentally, we observe that the three key challenges ing instruction, the exception is handled and the process re- of enabling precise exception and speculation recovery on sumed at a point consistent with the sequential architectural GPUs ultimately distill down to just two core problems: (i) model [36]. With support for precise exceptions, all types of minimizing the amount of program state that needs to be exceptions could be handled using a universal mechanism preserved and (ii) enabling restart from a consistent pro- such as the re-order buffer. However, precise exception sup- gram state. While previous work has explored optimiza- port has historically been difficult to implement for archi- tions to each of these pieces individually, the iGPU archi- tectures that execute parallel SIMD or vector instructions, tecture developed in this work synergistically enables both. where precise state with respect to an individual instruction In terms of preserving minimal program state, we ob- is not natural to the hardware. High fan-out control sig- serve that preserving live state alone is sufficient. Others nals to maintain sequential ordering in a vector pipeline are have made this observation as well [28, 29, 34]. However, challenging to implement, and while buffering and register they have assumed either a checkpoint was available, or renaming approaches have been proposed [14, 36], they are restarting from the same program state as at the site of a costly in terms of power, area, and/or performance. Hence, mis-speculation or exception was necessary. The architec- a key challenge is supporting consistent exception state: tural state on CPUs is also typically small (tens of registers) exposing sequentially-ordered program state to an excep- and hence the optimization of furthermore minimizing this tion handler and also enabling program restart from a self- live state has historically been relatively insignificant. For consistent point in the program. GPUs, however, minimizing the amount of state that must A second reason for the widespread adoption of precise be managed to handle context switching is valuable. exception support in CPUs was that it enabled support for Second, in terms of restarting the program from a con- demand paging in virtual memory systems: to overlap pro- sistent state, we observe that it is not always necessary to cessor execution with the long latency of paging I/O, the restart the program from the site of an exception or mis- state of a faulting process could be cleanly saved away speculation, even without checkpoints, and that restarting and another process restored in its place. Simply borrow- from consistent live state, as opposed to architectural state, ing techniques from the CPU space to implement context is in most cases sufficient. Again, others have made this switching on GPUs, however, is difficult. In particular, sav- observation as well [9, 18, 22]. However, they largely ig- ing GPU state and then context switching to another process nore live-state minimization and/or do not provide general while a page fault is handled imposes a monumental under- exception and speculation support. Other shortcomings that taking: while on a conventional CPU core a context switch preclude their use for GPUs are discussed in Section 6. requires little more than saving and restoring a few tens of This paper builds upon previous work and delivers a sim- registers, for a GPU it can require saving and restoring hun- ple, elegant, and efficient solution to the problems of ex- dreds of thousands of registers. Thus, a second key chal- ception and speculation on GPUs. The iGPU architecture
Load more

Recommended publications
  • Computer Science 246 Computer Architecture Spring 2010 Harvard University
    Computer Science 246 Computer Architecture Spring 2010 Harvard University Instructor: Prof. David Brooks [email protected] Dynamic Branch Prediction, Speculation, and Multiple Issue Computer Science 246 David Brooks Lecture Outline • Tomasulo’s Algorithm Review (3.1-3.3) • Pointer-Based Renaming (MIPS R10000) • Dynamic Branch Prediction (3.4) • Other Front-end Optimizations (3.5) – Branch Target Buffers/Return Address Stack Computer Science 246 David Brooks Tomasulo Review • Reservation Stations – Distribute RAW hazard detection – Renaming eliminates WAW hazards – Buffering values in Reservation Stations removes WARs – Tag match in CDB requires many associative compares • Common Data Bus – Achilles heal of Tomasulo – Multiple writebacks (multiple CDBs) expensive • Load/Store reordering – Load address compared with store address in store buffer Computer Science 246 David Brooks Tomasulo Organization From Mem FP Op FP Registers Queue Load Buffers Load1 Load2 Load3 Load4 Load5 Store Load6 Buffers Add1 Add2 Mult1 Add3 Mult2 Reservation To Mem Stations FP adders FP multipliers Common Data Bus (CDB) Tomasulo Review 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 LD F0, 0(R1) Iss M1 M2 M3 M4 M5 M6 M7 M8 Wb MUL F4, F0, F2 Iss Iss Iss Iss Iss Iss Iss Iss Iss Ex Ex Ex Ex Wb SD 0(R1), F0 Iss Iss Iss Iss Iss Iss Iss Iss Iss Iss Iss Iss Iss M1 M2 M3 Wb SUBI R1, R1, 8 Iss Ex Wb BNEZ R1, Loop Iss Ex Wb LD F0, 0(R1) Iss Iss Iss Iss M Wb MUL F4, F0, F2 Iss Iss Iss Iss Iss Ex Ex Ex Ex Wb SD 0(R1), F0 Iss Iss Iss Iss Iss Iss Iss Iss Iss M1 M2
    [Show full text]
  • OS and Compiler Considerations in the Design of the IA-64 Architecture
    OS and Compiler Considerations in the Design of the IA-64 Architecture Rumi Zahir (Intel Corporation) Dale Morris, Jonathan Ross (Hewlett-Packard Company) Drew Hess (Lucasfilm Ltd.) This is an electronic reproduction of “OS and Compiler Considerations in the Design of the IA-64 Architecture” originally published in ASPLOS-IX (the Ninth International Conference on Architectural Support for Programming Languages and Operating Systems) held in Cambridge, MA in November 2000. Copyright © A.C.M. 2000 1-58113-317-0/00/0011...$5.00 Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full cita- tion on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, to republish, to post on servers, or to redistribute to lists, requires prior specific permis- sion and/or a fee. Request permissions from Publications Dept, ACM Inc., fax +1 (212) 869-0481, or [email protected]. ASPLOS 2000 Cambridge, MA Nov. 12-15 , 2000 212 OS and Compiler Considerations in the Design of the IA-64 Architecture Rumi Zahir Jonathan Ross Dale Morris Drew Hess Intel Corporation Hewlett-Packard Company Lucas Digital Ltd. 2200 Mission College Blvd. 19447 Pruneridge Ave. P.O. Box 2459 Santa Clara, CA 95054 Cupertino, CA 95014 San Rafael, CA 94912 [email protected] [email protected] [email protected] [email protected] ABSTRACT system collaborate to deliver higher-performance systems.
    [Show full text]
  • Selective Eager Execution on the Polypath Architecture
    Selective Eager Execution on the PolyPath Architecture Artur Klauser, Abhijit Paithankar, Dirk Grunwald [klauser,pvega,grunwald]@cs.colorado.edu University of Colorado, Department of Computer Science Boulder, CO 80309-0430 Abstract average misprediction latency is the sum of the architected latency (pipeline depth) and a variable latency, which depends on data de- Control-flow misprediction penalties are a major impediment pendencies of the branch instruction. The overall cycles lost due to high performance in wide-issue superscalar processors. In this to branch mispredictions are the product of the total number of paper we present Selective Eager Execution (SEE), an execution mispredictions incurred during program execution and the average model to overcome mis-speculation penalties by executing both misprediction latency. Thus, reduction of either component helps paths after diffident branches. We present the micro-architecture decrease performance loss due to control mis-speculation. of the PolyPath processor, which is an extension of an aggressive In this paper we propose Selective Eager Execution (SEE) and superscalar, out-of-order architecture. The PolyPath architecture the PolyPath architecture model, which help to overcome branch uses a novel instruction tagging and register renaming mechanism misprediction latency. SEE recognizes the fact that some branches to execute instructions from multiple paths simultaneously in the are predicted more accurately than others, where it draws from re- same processor pipeline, while retaining maximum resource avail- search in branch confidence estimation [4, 6]. SEE behaves like ability for single-path code sequences. a normal monopath speculative execution architecture for highly Results of our execution-driven, pipeline-level simulations predictable branches; it predicts the most likely successor path of a show that SEE can improve performance by as much as 36% for branch, and evaluates instructions only along this path.
    [Show full text]
  • A Survey of Published Attacks on Intel
    1 A Survey of Published Attacks on Intel SGX Alexander Nilsson∗y, Pegah Nikbakht Bideh∗, Joakim Brorsson∗zx falexander.nilsson,pegah.nikbakht_bideh,[email protected] ∗Lund University, Department of Electrical and Information Technology, Sweden yAdvenica AB, Sweden zCombitech AB, Sweden xHyker Security AB, Sweden Abstract—Intel Software Guard Extensions (SGX) provides a Unfortunately, a relatively large number of flaws and attacks trusted execution environment (TEE) to run code and operate against SGX have been published by researchers over the last sensitive data. SGX provides runtime hardware protection where few years. both code and data are protected even if other code components are malicious. However, recently many attacks targeting SGX have been identified and introduced that can thwart the hardware A. Contribution defence provided by SGX. In this paper we present a survey of all attacks specifically targeting Intel SGX that are known In this paper, we present the first comprehensive review to the authors, to date. We categorized the attacks based on that includes all known attacks specific to SGX, including their implementation details into 7 different categories. We also controlled channel attacks, cache-attacks, speculative execu- look into the available defence mechanisms against identified tion attacks, branch prediction attacks, rogue data cache loads, attacks and categorize the available types of mitigations for each presented attack. microarchitectural data sampling and software-based fault in- jection attacks. For most of the presented attacks, there are countermeasures and mitigations that have been deployed as microcode patches by Intel or that can be employed by the I. INTRODUCTION application developer herself to make the attack more difficult (or impossible) to exploit.
    [Show full text]
  • SUPPORT for SPECULATIVE EXECUTION in HIGH- PERFORMANCE PROCESSORS Michael David Smith Technical Report: CSL-TR-93456 November 1992
    SUPPORT FOR SPECULATIVE EXECUTION IN HIGH- PERFORMANCE PROCESSORS Michael David Smith Technical Report: CSL-TR-93456 November 1992 Computer Systems Laboratory Departments of Electrical Engineering and Computer Science Stanford University Stanford, California 94305-4055 Abstract Superscalar and superpipelining techniques increase the overlap between the instructions in a pipelined processor, and thus these techniques have the potential to improve processor performance by decreasing the average number of cycles between the execution of adjacent instructions. Yet, to obtain this potential performance benefit, an instruction scheduler for this high-performance processor must find the independent instructions within the instruction stream of an application to execute in parallel. For non-numerical applications, there is an insufficient number of independent instructions within a basic block, and consequently the instruction scheduler must search across the basic block boundaries for the extra instruction-level parallelism required by the superscalar and superpipelining techniques. To exploit instruction-level parallelism across a conditional branch, the instruction scheduler must support the movement of instructions above a conditional branch, and the processor must support the speculative execution of these instructions. We define boosting, an architectural mechanism for speculative execution, that allows us to uncover the instruction-level parallelism across conditional branches without adversely affecting the instruction count of the application
    [Show full text]
  • High Performance Architecture Using Speculative Threads and Dynamic Memory Management Hardware
    HIGH PERFORMANCE ARCHITECTURE USING SPECULATIVE THREADS AND DYNAMIC MEMORY MANAGEMENT HARDWARE Wentong Li Dissertation Prepared for the Degree of DOCTOR OF PHILOSOPHY UNIVERSITY OF NORTH TEXAS December 2007 APPROVED: Krishna Kavi, Major Professor and Chair of the Department of Computer Science and Engineering Phil Sweany, Minor Professor Robert Brazile, Committee Member Saraju P. Mohanty, Committee Member Armin R. Mikler, Departmental Graduate Coordinator Oscar Garcia, Dean of College of Engineering Sandra L. Terrell, Dean of the Robert B. Toulouse School of Graduate Studies Li, Wentong, High Performance Architecture using Speculative Threads and Dynamic Memory Management Hardware. Doctor of Philosophy (Computer Science), December 2007, 114 pp., 28 tables, 27 illustrations, bibliography, 82 titles. With the advances in very large scale integration (VLSI) technology, hundreds of billions of transistors can be packed into a single chip. With the increased hardware budget, how to take advantage of available hardware resources becomes an important research area. Some researchers have shifted from control flow Von-Neumann architecture back to dataflow architecture again in order to explore scalable architectures leading to multi-core systems with several hundreds of processing elements. In this dissertation, I address how the performance of modern processing systems can be improved, while attempting to reduce hardware complexity and energy consumptions. My research described here tackles both central processing unit (CPU) performance and memory subsystem performance. More specifically I will describe my research related to the design of an innovative decoupled multithreaded architecture that can be used in multi-core processor implementations. I also address how memory management functions can be off-loaded from processing pipelines to further improve system performance and eliminate cache pollution caused by runtime management functions.
    [Show full text]
  • Whitepaper Cache Speculation Side-Channels Author: Richard Grisenthwaite Date: January 2018 Version 1.1
    Whitepaper Cache Speculation Side-channels Author: Richard Grisenthwaite Date: January 2018 Version 1.1 Introduction This whitepaper looks at the susceptibility of Arm implementations following recent research findings from security researchers at Google on new potential cache timing side-channels exploiting processor speculation. This paper also outlines possible mitigations that can be employed for software designed to run on existing Arm processors. Overview of speculation-based cache timing side-channels Cache timing side-channels are a well understood concept in the area of security research. As such, this whitepaper will provide a simple conceptual overview rather than an in-depth explanation. The basic principle behind cache timing side-channels is that the pattern of allocations into the cache, and, in particular, which cache sets have been used for the allocation, can be determined by measuring the time taken to access entries that were previously in the cache, or by measuring the time to access the entries that have been allocated. This then can be used to determine which addresses have been allocated into the cache. The novelty of speculation-based cache timing side-channels is their use of speculative memory reads. Speculative memory reads are typical of advanced micro-processors and part of the overall functionality which enables very high performance. By performing speculative memory reads to cacheable locations beyond an architecturally unresolved branch (or other change in program flow), and, further, the result of those reads can themselves be used to form the addresses of further speculative memory reads. These speculative reads cause allocations of entries into the cache whose addresses are indicative of the values of the first speculative read.
    [Show full text]
  • Invisispec: Making Speculative Execution Invisible in the Cache Hierarchy
    InvisiSpec: Making Speculative Execution Invisible in the Cache Hierarchy Mengjia Yany, Jiho Choiy, Dimitrios Skarlatos, Adam Morrison∗, Christopher W. Fletcher, and Josep Torrellas University of Illinois at Urbana-Champaign ∗Tel Aviv University fmyan8, jchoi42, [email protected], [email protected], fcwfletch, [email protected] yAuthors contributed equally to this work. Abstract— Hardware speculation offers a major surface for the attacker’s choosing. Different types of attacks are possible, micro-architectural covert and side channel attacks. Unfortu- such as the victim code reading arbitrary memory locations nately, defending against speculative execution attacks is chal- by speculating that an array bounds check succeeds—allowing lenging. The reason is that speculations destined to be squashed execute incorrect instructions, outside the scope of what pro- the attacker to glean information through a cache-based side grammers and compilers reason about. Further, any change to channel, as shown in Figure 1. In this case, unlike in Meltdown, micro-architectural state made by speculative execution can leak there is no exception-inducing load. information. In this paper, we propose InvisiSpec, a novel strategy to 1 // cache line size is 64 bytes defend against hardware speculation attacks in multiprocessors 2 // secret value V is 1 byte 3 // victim code begins here: Fig. 1: Spectre variant 1 at- by making speculation invisible in the data cache hierarchy. 4 uint8 A[10]; tack example, where the at- InvisiSpec blocks micro-architectural covert and side channels 5 uint8 B[256∗64]; tacker obtains secret value V through the multiprocessor data cache hierarchy due to specula- 6 // B size : possible V values ∗ line size 7 void victim ( size t a) f stored at address X.
    [Show full text]
  • A State of the Art Investigation
    Report Type Deliverable D1.1 Report Name A State-of-the-Art Investigation Dissemination Level Public Status Final Version Number 1.0 Date of Preparation 16th October 2019 CyReV (Dnr 2018-05013) Deliverable D1.2 - A State-of-the-Art Investigation ©2019 The CyReV Consortium ii Executive Summary This deliverable (D1.1 State-of-the-Art Investigation) presents the results and achieve- ments of sub-work package WP1.1 (State of the art) of the CyReV project. The goal of this deliverable is to provide insight into the state of current research frontiers in security and resiliency for vehicles and vehicular security. It also serves as an introduction to the issues faced in the automotive domain with an extensive reference list for more detailed studies. Finally, it can be used as background on which to base further investigations. The FFI HOLIstic Approach to Improve Data SECurity (HoliSec) project produced the deliverable “D1.2 State of the art”, CyReV uses this deliverable as a baseline and extends the current state of the art in regards to resiliency. The report includes discussions about hardware and operating system level secur- ity, internal and external communication security, intrusion detection systems, secure software development, and related research projects. Many topics are discussed very briefly, since an exhaustive treatment of each would certainly be out of the scope of this deliverable. iii CyReV (Dnr 2018-05013) Deliverable D1.2 - A State-of-the-Art Investigation ©2019 The CyReV Consortium iv Contributors Editor(s) Affiliation Email
    [Show full text]
  • Speculative Execution and Instruction-Level Parallelism
    M A R C H 1 9 9 4 WRL Technical Note TN-42 Speculative Execution and Instruction-Level Parallelism David W. Wall d i g i t a l Western Research Laboratory 250 University Avenue Palo Alto, California 94301 USA The Western Research Laboratory (WRL) is a computer systems research group that was founded by Digital Equipment Corporation in 1982. Our focus is computer science research relevant to the design and application of high performance scientific computers. We test our ideas by designing, building, and using real systems. The systems we build are research prototypes; they are not intended to become products. There is a second research laboratory located in Palo Alto, the Systems Research Cen- ter (SRC). Other Digital research groups are located in Paris (PRL) and in Cambridge, Massachusetts (CRL). Our research is directed towards mainstream high-performance computer systems. Our prototypes are intended to foreshadow the future computing environments used by many Digital customers. The long-term goal of WRL is to aid and accelerate the development of high-performance uni- and multi-processors. The research projects within WRL will address various aspects of high-performance computing. We believe that significant advances in computer systems do not come from any single technological advance. Technologies, both hardware and software, do not all advance at the same pace. System design is the art of composing systems which use each level of technology in an appropriate balance. A major advance in overall system performance will require reexamination of all aspects of the system. We do work in the design, fabrication and packaging of hardware; language processing and scaling issues in system software design; and the exploration of new applications areas that are opening up with the advent of higher performance systems.
    [Show full text]
  • PA-RISC 8X00 Family of Microprocessors with Focus on PA-8700
    PA-RISC 8x00 Family of Microprocessors with Focus on PA-8700 Technical White Paper April 2000 1 Preliminary PA-8700 circuit information — production system specifications may differ Table of Contents 1. PA-RISC: Betting the House and Winning...............................................3 2. RISC Philosophy ........................................................................................4 Clock Frequency ............................................................................................................................................................4 VLSI Integration..............................................................................................................................................................4 Architectural Enhancements ........................................................................................................................................5 3. Evolution of the PA-RISC Family ..............................................................6 4. Key Highlights from PA-8000 to PA-8600.................................................7 5. PA-8700 Feature Set Highlights ................................................................8 Large Robust Primary Caches.....................................................................................................................................9 Data Integrity - Error Detection and Error Correction Capabilities ........................................................................10 Static and Dynamic Branch Prediction - Faster Program
    [Show full text]
  • Itanium Processor Microarchitecture
    ITANIUM PROCESSOR MICROARCHITECTURE THE ITANIUM PROCESSOR EMPLOYS THE EPIC DESIGN STYLE TO EXPLOIT INSTRUCTION-LEVEL PARALLELISM. ITS HARDWARE AND SOFTWARE WORK IN CONCERT TO DELIVER HIGHER PERFORMANCE THROUGH A SIMPLER, MORE EFFICIENT DESIGN. The Itanium processor is the first ic runtime optimizations to enable the com- implementation of the IA-64 instruction set piled code schedule to flow through at high architecture (ISA). The design team opti- throughput. This strategy increases the syn- mized the processor to meet a wide range of ergy between hardware and software, and requirements: high performance on Internet leads to higher overall performance. servers and workstations, support for 64-bit The processor provides a six-wide and 10- addressing, reliability for mission-critical stage deep pipeline, running at 800 MHz on applications, full IA-32 instruction set com- a 0.18-micron process. This combines both patibility in hardware, and scalability across a abundant resources to exploit ILP and high range of operating systems and platforms. frequency for minimizing the latency of each The processor employs EPIC (explicitly instruction. The resources consist of four inte- parallel instruction computing) design con- ger units, four multimedia units, two Harsh Sharangpani cepts for a tighter coupling between hardware load/store units, three branch units, two and software. In this design style the hard- extended-precision floating-point units, and Ken Arora ware-software interface lets the software two additional single-precision floating-point exploit all available compilation time infor- units (FPUs). The hardware employs dynam- Intel mation and efficiently deliver this informa- ic prefetch, branch prediction, nonblocking tion to the hardware.
    [Show full text]