Msc THESIS Communication-Centric Debugging of Systems on Chip Using Networks on Chip
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Computer Engineering 2007 Mekelweg 4, 2628 CD Delft The Netherlands http://ce.et.tudelft.nl/ MSc THESIS Communication-centric Debugging of Systems on Chip using Networks on Chip Siddharth Umrani Abstract The rapid technology scaling i.e. shrinking feature size means that a large number of components can be integrated on a single Integrated Chip (IC). This increased complexity translates into an increase in design e®ort and also potentially more design errors. Thus changes are required in the system-on-chip development which will reduce both design e®ort and design errors. To reduce design e®ort, a mod- ular design methodology which promotes reuse of already designed IP cores rather than the design of IP cores themselves is used. Thus the complexity of such a chip is resident in communication between these cores rather than in the computation taking place in them. The shriking feature size also introduces Deep Sub-Micron (DSM) e®ects in on-chip interconnect wires. Networks on chip have since evolved as a promising new type of interconnect which have the potential to alleviate these shortcomings. E®ective debug aids in fast and accurate detection of majority of the CE-MS-2007-11 errors that may be present in the design thus reducing the number of iterations in the design cycle (and e®ectively the time to market). Traditional debug is core-based, where each of the IP cores in a SoC are the locus of debug actions. Communication-centric debug has been proposed as a complementary debug solution that uses the in- terconnect to debug the chip. Combination of these debug strategies might help speed up accurate error localization during debug and thus signi¯cant gains possible in reducing time to market. This thesis report presents a debug infrastructure that facilitates Communication-Centric Debug of System on Chip using Network on Chip. Faculty of Electrical Engineering, Mathematics and Computer Science Communication-centric Debugging of Systems on Chip using Networks on Chip A Debug Infrastructure THESIS submitted in partial ful¯llment of the requirements for the degree of MASTER OF SCIENCE in COMPUTER ENGINEERING by Siddharth Umrani born in Thane, INDIA Computer Engineering Department of Electrical Engineering Faculty of Electrical Engineering, Mathematics and Computer Science Delft University of Technology Communication-centric Debugging of Systems on Chip using Networks on Chip by Siddharth Umrani Abstract he rapid technology scaling i.e. shrinking feature size means that a large number of com- ponents can be integrated on a single Integrated Chip (IC). This increased complexity T translates into an increase in design e®ort and also potentially more design errors. Thus changes are required in the system-on-chip development which will reduce both design e®ort and design errors. To reduce design e®ort, a modular design methodology which promotes reuse of already designed IP cores rather than the design of IP cores themselves is used. Thus the complexity of such a chip is resident in communication between these cores rather than in the computation taking place in them. The shriking feature size also introduces Deep Sub-Micron (DSM) e®ects in on-chip interconnect wires. Networks on chip have since evolved as a promising new type of interconnect which have the potential to alleviate these shortcomings. E®ective debug aids in fast and accurate detection of majority of the errors that may be present in the design thus reducing the number of iterations in the design cycle (and e®ectively the time to market). Traditional debug is core-based, where each of the IP cores in a SoC are the locus of debug actions. Communication-centric debug has been proposed as a complementary debug solution that uses the interconnect to debug the chip. Combination of these debug strategies might help speed up accurate error localization during debug and thus signi¯cant gains possible in reducing time to market. This thesis report presents a debug infrastructure that facilitates Communication-Centric Debug of System on Chip using Network on Chip. Laboratory : Computer Engineering Codenumber : CE-MS-2007-11 Committee Members : Advisor: Kees Goossens, CE, TU Delft and NXP Semiconductors Advisor: Georgi Gaydadjiev, CE, TU Delft Member: Zaid Al-Ars, CE, TU Delft Member: Ren¶evan Leuken, CAS, TU Delft i ii Dedicated to my parents and my brother Aditya iii iv Contents List of Figures ix Acknowledgements xi 1 Introduction 1 1.1 Motivation . 1 1.2 Goals . 1 1.3 Previous Work . 1 1.4 Organization of Report . 2 2 Network-on-chip (NoC) 3 2.1 Introduction . 3 2.2 Interconnect Terminology . 3 2.3 Timeline of Interactions . 10 2.4 Æthereal NoC . 12 2.5 Network Interface . 13 3 Debug 17 3.1 Introduction . 17 3.2 Debug Flow . 19 3.3 Debug Granularity . 20 4 Communication Centric Debug 25 4.1 Introduction . 25 4.2 Design choices . 25 4.3 Debug Strategy for SoCs . 26 4.4 Locus of communication-centric debug control . 27 4.5 DTL Protocol . 29 4.6 Debug Control Actions . 29 4.7 Example . 35 5 Debug Hardware Infrastructure 39 5.1 Overview . 39 5.2 Monitors . 39 5.3 Event Distribution Interconnect (EDI) . 41 5.4 Test Point Registers (TPRs) . 46 5.5 Network Interface Shell (NI Shell) . 54 5.6 Test Access Port (TAP) . 62 5.7 Debug Flow Automation . 64 v 6 Debug Software Infrastructure 65 6.1 User programming via the TAP . 65 6.2 Use of Debug Infrastructure . 66 6.3 Debug Flow . 68 7 Results 71 7.1 Programming the TPRs . 71 7.2 EDI stop pulse distribution . 72 7.3 Debug Control Actions in the shells . 73 7.4 Area Cost and Speed . 75 8 Conclusions 79 8.1 Conclusions . 79 8.2 Future Work . 79 Bibliography 85 A Constraints on External Stop Pulse 87 B List of Acronyms 89 vi List of Figures 2.1 IP and its port . 4 2.2 Transactions (Read and Write) . 4 2.3 Messages and Elements . 5 2.4 Signal Handshake . 6 2.5 Signal Groups and Signals . 7 2.6 Connection and Channels . 8 2.7 Communication - (a) Narrowcast (b) Multi-initiator . 9 2.8 Hierarchies . 9 2.9 Master and Slave IPs communicating with NoC as interconnect. 10 2.10 Timeline of Interactions (MNI - Master Network Interface, SNI - Slave Network Interface) . 11 2.11 Æthereal NoC. 13 2.12 Æthereal connection. 14 2.13 Æthereal Network Interface. 15 2.14 Connections / channels in Æthereal. 15 2.15 Visible granularities of Interactions . 16 3.1 Digital design flow(Source: [29])........................ 17 3.2 Real-time debug approach. In this scenario, internal signals are observed in real-time via external on-chip pins. 19 3.3 Scan-based debug approach. In this scenario, everytime the chip reaches a quiescent state, the functional clocks can be stopped and the internal state read out. 20 3.4 Traditional scan-based debug flow (Source: [29]). 21 3.5 Proposed scan-based debug flow . 21 3.6 (a) Granularity of internal NoC control. (b) Granularity of control be- tween IP and NoC. 22 4.1 (a) Computation-centric debug (b) Communication-centric debug (Source: [37])................................... 26 4.2 Debug flow using Communication-centric debug . 27 4.3 Locus of communication-centric debug control. 28 4.4 Debug control action interfaces (MNI-Master Network Interface, SNI- Slave Network Interface). 29 4.5 DTL Signals (Source: [30])........................... 30 4.6 Timeline for a Stop (MNI - Master Network Interface, SNI - Slave Network Interface) . 32 4.7 Timeline for a Continue (MNI - Master Network Interface, SNI - Slave Network Interface) . 33 4.8 Example illustrating the various debug actions over an IP-NoC interface . 34 4.9 Example SoC showing connections setup . 36 vii 5.1 The Debug Infrastructure . 40 5.2 Monitor Interface, where the monitor stop is connected to the EDI, link data to the router link which is to be monitored and monitor config to the monitorcon¯g TPR which speci¯es the breakpoint condition. 41 5.3 Breakpoint Generation logic inside a Monitor . 41 5.4 Monitor gate-level waveforms for breakpoint hit . 42 5.5 Standing wave creation in the EDI . 43 5.6 Sub-sampling of a breakpoint hit pulse . 44 5.7 Stop Module Interfaces, where N is the number of neighboring devices (other Stop Modules and NIs . 44 5.8 Stop Module FSM, where stop in is the logical OR of all N neighbouring input stop signals and stop out the output signal to all N neighbouring devices. 45 5.9 Stop Module waveforms for monitor stop . 46 5.10 Stop Module waveforms for external user stop through TAP . 46 5.11 Programming of the Monitor Con¯g TPR . 47 5.12 The internal structure of the NI-Shell TPR, which is imperative to know during programming in order to be able to programme the right value for the desired control. 48 5.13 Explains the function of Stop Enable ¯eld in the NI-Shell TPR . 49 5.14 Behaviour when Stop Condition ¯eld is de-asserted in the NI-Shell TPR 50 5.15 Behaviour when Stop Condition ¯eld is asserted in the NI-Shell TPR . 51 5.16 Behaviour when Stop Granularity ¯eld is de-asserted in the NI-Shell TPR 52 5.17 Behaviour when Stop Granularity ¯eld is asserted in the NI-Shell TPR 53 5.18 Continue operation . 54 5.19 Explains the function of Continue ¯eld in the NI-Shell TPR . 55 5.20 NI Shell FSM (Mirror State transitions) . 56 5.21 Narrowcast Shell (in the FIFO shown the channel IDs of un¯nished read requests are bu®ered) .