The Impact of Dennard's Scaling Theory Sscs NL0107 1/8/07 9:54 AM Page 2

sscs_NL0107 1/8/07 9:54 AM Page 1 SSCSSSSCSSSSCCSS IEEE SOLID-STATE CIRCUITS SOCIETY NEWS Winter 2007 Vol. 12, No. 1 www.ieee.org/sscs-news

The Impact of Dennard's Scaling Theory sscs_NL0107 1/8/07 9:54 AM Page 2

Editor’s Column

e appre- ed topic, with background articles that address the theme: ciate all (that is, the ‘original sources’) and (1) “A 30 Year Retrospective on Wof your new articles by experts who Dennard's MOSFET Scaling feedback on our describe the current state of affairs Paper,” by Mark Bohr of Intel first issue in Septem- in technology and the impact of the Corporation; ber, 2006 on “The original papers and/or patents. (2) “Device Scaling: The Treadmill Technical Impact of The theme of the Winter 2007 that Fueled Three Decades of Moore's Law.” With the Winter, 2007 issue is “The Impact of Dennard's Semiconductor Industry Growth,” issue, we are continuing our new Scaling Theory.” by Pallab Chatterjee of i2 Tech- policy of mailing a hard copy of the This issue contains one Research nologies; SSCS News to all 11,500 members. Highlights article: “Analog IC Design (3) “Recollections on MOSFET This issue is the first of four that SSCS at the University of Twente,” by Scaling,” by Dale Critchlow, plans to publish annually (one each Bram Nauta, Head of the IC Design the University of Vermont; in Winter, Spring, Summer, and Fall). Group at the University of Twente, (4) “The Business of Scaling,” by The goal of every issue is to be a The Netherlands. The issue also Rakesh Kumar, TCX, Inc. Tech- self-contained resource on a select- contains seven short feature articles nology Connexions; (5) “A Perspective on the Theory of MOSFET Scaling and its IEEE Solid-State Circuits Society AdCom Impact,” by Tak Ning, IBM; President: Newsletter Coeditor: Richard C. Jaeger Mary Y. Lanzerotti (6) “Impact of Scaling and the Alabama Microelectronics Center IBM T.J. Watson Research Center environment in which the Scal- Auburn University, AL myl@us.ibm.com [email protected] Fax: +1 914 945 1358 ing developed Fax: +1 334 844-1888 at that time," by Yoshio Nishi, Stan- Vice President: Elected AdCom Members at Large Terms to 31 Dec. 07: ford University; Willy Sansen K. U. Leuven Bill Bidermann (7) "It's All About Scale," by Hans Leuven, Belgium David Johns Stork, TI. Terri Fiez Secretary: Three original papers by Den- David A. Johns Takayasu Sakurai University of Toronto Mehmet Soyuer nard, from 1972 (IEDM Conference), Toronto, Ontario, Canada Terms to 31 Dec. 08: 1973 (IEDM Conference), and 1974 Wanda K. Gass Treasurer: (IEEE Journal of Solid-State Cir- Rakesh Kumar Ali Hajimiri Technology Connexions Paul J. Hurst cuits), are also reprinted in this Poway, CA Akira Matsuzawa issue. Ian Young Past President: Terms to 31 Dec. 09: Thank you for taking the time to Stephen H. Lewis University of California John J. Corcoran read the SSCS News. We appreciate Davis, CA Kevin Kornegay your comments and feedback! Please Hae-Seung (Harry) Lee Other Representatives: Thomas H. Lee send comments to [email protected]. Representative to Sensors Council Jan Van der Spiegel Darrin Young Representative from CAS to SSCS Chairs of Standing Committees: Domine Leenaerts Awards David Hodges Representative to CAS from SSCS Chapters Jan Van der Spiegel Un-Ku Moon Education CK Ken Yang Newsletter Editor: Meetings Anantha Chandrakasan Lewis Terman Membership Bruce Hecht IBM T. J. Watson Research Center Nominations Stephen H. Lewis [email protected] Publications Bernhard Boser Fax: +1 914 945-4160 For detailed contact information, see the Soci- ety e-News: www.ieee.org/portal/site/sscs

For questions regarding Society business, contact the SSCS Executive Office. Contributions for the Spring 2007 issue of the Newsletter must be received by 8 February 2007 at the SSCS Executive Office. A complete media kit for advertisers is available at www.spectrum.ieee.org/mc_print. Scroll down to find SSCS Anne O’Neill, Executive Director Katherine Olstein, SSCS Administrator IEEE SSCS IEEE SSCS 445 Hoes Lane 445 Hoes Lane, Piscataway, NJ 08854 Piscataway, NJ 08854 Tel: +1 732 981 3400 Tel: +1 732 981 3410 Fax: +1 732 981 3401 Fax: +1 732 981 3401 Email: [email protected] Email: [email protected]

2 IEEE SSCS NEWSLETTER Winter 2007 sscs_NL0107 1/8/07 9:55 AM Page 3

Editor’s Column ...... 2

President’s Message ...... 4

Corrections ...... 4

RESEARCH HIGHLIGHTS Analog IC Design at the University of Twente ...... 5

TECHNICAL LITERATURE A 30 Year Retrospective on Dennard’s MOSFET Scaling Paper . . .11 Device Scaling: The Treadmill that Fueled Three Decades of Semi- conductor Industry Growth ...... 14 Recollections on MOSFET Scaling ...... 19 The Business of Scaling ...... 22 A Perspective on the Theory of MOSFET Scaling and its Impact . .27 The Impact of Scaling and the Scaling Development Environment 31 It’s All About Scale ...... 33 Design of Micron MOS Switching Devices ...... 35 20 Ion Implanted MOSFET’s with Very Short Channel Lengths ...... 36 Design of Ion-Implanted MOSFET’s with Very Small Physical Dimensions 38

PEOPLE An Interview with James Meindl - 2006 IEEE Medal of Honor Recipient 51 Hugo De Man Awarded for Leadership in Integrated Circuit Design . .53 Yannis P. Tsividis to Receive IEEE Kirchhoff Award ...... 56 IEEE Educational Innovation Award to Terri Fiez ...... 58 16 New Speakers Diversify SSCS Distinguished Lecturer Program ...... 61 New Senior Members ...... 67 Tools: How to Write Readable Reports and Winning Proposals ...... 67

CHAPTER NEWS 51 SSCS Awards $35,000 in Chapter Subsidies ...... 69 Far East Chapters Meet in Hangzhou, China ...... 70 V. Oklobdzija Offers IEEE DL Talks in Western Australia ...... 71 Denver Hosts Technical Seminars on Cutting-Edge CMOS Technology .72

CONFERENCES Second A-SSCC Considers Challenges for the e-Life ...... 74 Solid-State Circuits Conference Will Focus on Nano-Era Synergy . .76 Invitation from the ISSCC 2007 Chair ...... 75 AACD Conference Will Convene on 27-29 March 2006 ...... 78

NEWS SSCS AdCom Election for 2007-2009 Term ...... 80 IEEE Design Council Newsletter Completes Inaugural Year ...... 80 IEEE Teaching Awards ...... 81 56 Call for Nominations: SSCS Predoctoral Fellowships ...... 82

Winter 2007 IEEE SSCS NEWSLETTER 3 sscs_NL0107 1/8/07 9:55 AM Page 4

Message from the President

In 2007, look for an unadvertised bonus the recent addition of Tainan (Taiwan) and South with your SSCS membership: A free Brazil. Celebrate our anniversary by browsing your subscription to the brand new quarterly technical articles online. Nanotechnology Magazine. We believe I’ve been active in the last quarter attending many of that circuit experts need to be in touch the conferences that SSCS cosponsors to sample their with this rapidly progressing technolo- quality, focus, and differences, as well as to increase the gy. Some day it will be a fruitful area Society’s visibility and support for these important gath- for circuits development, and opportunities to con- erings of technical experts. ESSCIRC in Montreux, tribute will arise. Switzerland last fall was fully overlapped with the ESS- The minimal subscription cost to the Society for the DERC device conference. One was able to move freely launch year of the new magazine prompted the AdCom between the co-located meetings. The wide variety of to join the Nanotechnology Council. We hope the plenary topics covered by the two meetings was of par- Council’s magazine effort will be of comparable interest ticular interest. Welcoming the Asian-Solid-State Circuits to its Transactions on Nanotechnology, which is just Conference in Hangzhou, China two months later, I was beginning its sixth year and has among the highest rates able to talk with circuit experts from around the world, of citation as measured by the Thompson ISI. I would and by the time this issue reaches you, I will have cel- like to receive feedback from you on how useful a tool ebrated the opening of the 20th International Confer- the new magazine is. Look for the first issue in the ence on VLSI Design in Bangalore. spring of 2007. Thanks to all of our members who voted in our fall 2007 is the Society’s 10th anniversary, having election. Welcome to our new additions to AdCom, evolved from the Solid-State Circuits Council that orig- Kevin Kornegay from Georgia Tech and Harry Lee from inated in 1970. We’ve updated the SSCS logo for this MIT. And welcome back to returning AdCom members year to draw attention to our progress. Since 1997, the John Corcoran from Agilent Laboratories, Tom Lee from Journal of Solid-State Circuits has increased coverage of Stanford, and Jan Van der Spiegel from the University of technical articles by 40%, and the SSCS Newsletter by 2 Pennsylvania. The Society is beginning a review of its 1/2 times. The JSSC continues to be the most read in priorities for 2007 and beyond. As Society members, IEEE Xplore and the most cited in patents. Your SSCS please make your interests known to your AdCom rep- membership provides online access not only to the resentatives. Start a conversation and help the Society Journal but also to the digests of our five major solid- point to the future that you feel is coming. state circuits conferences and most of their historic record. Local chapters have grown from 2 to 59, with Richard C. Jaeger Corrections

In the article entitled “Overview of the caption for Figure 4 should read: and the first commercially-available CMOS Technology Development in Fig. 4 Gate leakage current in integrated circuit in Figs 3 & 4. I am the MIRAI Project,” by Toshiaki MIRAI HfAlON formed by Layer-by- particularly fond of the transistor, Masuhara and Masataka Hirose in Layer Deposition and Annealing since it is one of the very few prod- the September 2006 issue, the last (LL-D&A) 4). ucts that I designed myself that sentence in the Section entitled actually went into production. “New Circuits and System Technolo- (a) Comparison of gate leakage cur- gy - Post-fabrication Adaptive rent in MOSFETs with HfAlON Adjustment” contains an incorrect gate insulator and HfSiON 5). expression, which is corrected as in (b) Cross sectional TEM micrograph

the underlined expression in the fol- of HfAlON/SiO2/Si gate stack lowing sentence: formed by Layer-by-Layer Depo- “As shown in Fig. 3, the devel- sition and Annealing. oped tool successfully extracted the 34 model parameters in 23 hours The following corrections pertain with a PC and resulted in a mean to the reprint of “Lithography and RMS error of 1.83% for benchmark the Future of Moore’s Law” (Moore, MOSFETs.” 1995) in the September 2006 issue: Fig. 3. Photomicrograph of the first In the Section, “New Gate Stack I have reproduced photomicro- commercial planar transistor. Technology with High-k Materials”, graphs of the first planar transistor continued on page 10

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RESEARCH HIGHLIGHTS Analog IC Design at the University of Twente Bram Nauta, IC Design Group, University of Twente, Enschede, The Netherlands, [email protected]

Introduction Figure 1a shows a wide band first amplifier stage, This article describes some recent research results denoted as a common-source feedback amplifier. from the IC Design group of the University of Twente, located in Enschede, The Netherlands. Our research focuses on analog CMOS circuit design with emphasis on high frequency and broad- band circuits. With the trend of system integration in mind, we try to develop new circuit techniques that enable the next steps in system integration in nanometer CMOS technology. Our research funding comes from industry, as well as from governmental organizations. We aim to find fundamental solutions for practical problems of integrated circuits realized in industrial Silicon technologies. CMOS IC technology is dictated by optimal cost and Fig 1a: common source LNA with impedance matching, performance of digital circuits and is certainly not the signals at nodes X and Y have opposite sign. Fig 1b: The noise of M1 generates in-phase noise voltages optimized for nice analog behavior. As analog design- at nodes X and Y. ers, we do not have the illusion of being able to

change CMOS technology, so we have to “live with it” The input impedance is 1/gm of M1, and must be and solve the problems by design. In this article sev- equal to the source impedance Rs, usually 50 Ohms. eral examples will be shown where problematic ana- With this in mind the gm of M1 is fixed by design log behavior, such as noise and distortion, can be tack- resulting in poor noise behavior of the amplifier: The led with new circuit design techniques. These circuit "noise figure" is always larger than 3dB. In order to

techniques are developed in such a way that they do reduce the noise one would like to increase the gm of

benefit from modern technology and thus enable fur- M1 (preferably gm>>1/Rs for minimal noise figure) but ther integration. This way we can improve various then the input impedance does not match anymore. analog building blocks for wireless, wire-line and opti- Conventionally, additional feedback techniques are cal communication. Below some examples are given. used to break this paradox, but at the cost of stability and bandwidth issues. Thermal Noise Cancelling PhD Student Federico Bruccoleri realized, howev- Noise is an important issue; in communication circuits er, that generated noise can be cancelled by proper the sensitivity of the receiver is limited by the noise circuit design. If we take a look at Figure 1b, we can level of the circuits. Especially, the noise of the first see how the noise current of M1 flows in the circuit; amplifier in the receiving chain is of high importance, this is indicated by the red arrow. since after that amplifier the signal is stronger and the The noise current due to M1 flows in a loop, allowable noise levels are higher. For narrowband through Rs. This noise current generates a noise volt- receivers the added noise of the amplifier can be age at nodes X and Y which are of different magni- reduced relatively easily. This is done by using reso- tude but of the same phase. The signals nodes X and nant structures, built with - for example - integrated Y are in anti-phase due to the inverting nature of this spiral inductors and capacitors which provide voltage amplifier. So somehow it should be possible to sepa- gain of the narrowband signals and therefore needing rate the signal from the noise! less gain from “noisy” transistors. For wideband sys- By adding an additional amplifier “A,” as shown in tems, e.g. for TV tuners, UWB (Ultra Wide Band) Figure 2, we can construct an output signal in such a communication and future software defined radio, way the wanted signals at nodes X and Y are added several octaves of bandwidth are needed and simple and that the noise at nodes X and Y are cancelled [1]. resonant structures cannot be used. For these appli- This way we can cancel the noise of M1, which holds cations, low noise gain stages using noisy transistors for both thermal and 1/f noise. Of course amplifier have to be used, which is quite a challenge. Apart “A” will now add additional noise, but this needs not from the gain and noise demands, additional to be a problem. The reason for this is that in contrast demands, such as input impedance matching and to M1, we can choose the gm of the input stage of good linearity, need to be satisfied. amplifier “A” relatively large, and thus make it low-

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RESEARCH HIGHLIGHTS

Fig. 3: MOSFET under constant bias (blue) and switched bias (red) Fig 2: Basic idea of noise cancelling; the noise due to M1 is cancelled. Measurements however showed 6 + 8 = 14 dB reduction for frequencies lower than the switching frequen- noise. So we don't break the laws of physics: we still cy, as illustrated with the red curve in Figure 4. have to burn power (in amplifier “A”) to get a low- This matched to the 8dB reduction of phase noise noise amplifier, but we have created a degree of free- in the inverter ring-oscillator. This reduction takes

dom by decoupling the input matching (gm1=1/Rs) place for frequencies lower than the switching fre-

and allowing a large gm ( gmA>>1/Rs) in the amplifier quency. Later, we discovered that a similar noise phe-

A. The noise of Ibias is cancelled as well. A prototype nomenon had been observed before in physicists' amplifier has been realized on silicon and it worked device experiments[3]; however, we could not find a well: the noise figure was well below 3dB, which citation to this paper. proves the concept of noise canceling. Also the robustness to mismatch in the two noise paths is good [1]. Other topologies are also possible offering “balun” functionality [1,2].

Low Frequency noise reduction in MOSFETS Low frequency (LF) transistor noise, also denoted as 1/f noise, is of great importance in today's circuit design. Especially, baseband circuits suffer from this noise phenomenon which can be dominant well above 10MHz. Also high-frequency oscillators suffer from LF noise, since this noise is up-converted and appears close to the carrier frequency of the oscillator degrading the close-in phase noise. A while ago, a MSc student Gian Hoogzaad did calculations on the phase noise of CMOS inverter- based ring oscillators. These oscillators were free Fig. 4: Measured LF noise of a MOSFET under constant running, and we expected a large close-in phase bias (blue), expected 6 dB reduction under switched bias noise due to the low frequency noise of the MOS- (red dashed curve) and measured behavior with intrinsic FETs in the oscillator. Measurements, however, reduced noise (red) showed a much lower, (8dB less), close-in phase noise than we expected from the LF noise of those So, in fact, all inverter based ring oscillators bene- single transistors. The student and his supervisor fited already from this phenomenon while none of Sander Gierkink were very confident of his calcula- the designers apparently realized this. To a large tions, and we were thus wondering what caused the extent this is because the “switched bias” noise reduc- 8dB lower close-in phase noise. tion is not modeled in today's simulators. Also, the Finally, we suspected that the large signal switch- effect can be masked by the very large spread which ing behavior in the inverters caused the strange effect is normally present in LF noise, especially for small and we carried out measurements on stand-alone area devices. transistors under normal bias and under “switched After a study carried out in the PhD projects by bias”. Figure 3 illustrates these conditions. Arnoud van der Wel and Jay Kolhatkar, the phenom- One would expect 6 dB less noise from the ena could be explained by the bias dependency of switched bias transistors compared to the normal one: the emission and capture time constants which are 3dB reduction due to the 50% duty-cycle of the noise responsible for the trapping and de-trapping of oxide- and another 3dB due to up-conversion of the LF noise. charge in MOSFETs. This trapping and de-trapping

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causes so-called random telegraph signals, which determine the low frequency noise of the transistors. The reduction effect is found to be present in all technologies investigated: from 10μm down to 0.12μm, both N and P MOSFETs and works for switching frequencies up to at least 3GHz. For large-geometry transistors we generally see a significant reduction, whereas for very small-sized modern devices the noise can decrease but also increase. This is due to the very small number of traps in the transistors (sometimes only one trap) Fig. 5: N path poly-phase circuit can cancel up to the N-1th while the phenomenon depends strongly on the harmonic. energy distribution of the traps. Details can be found in [4]. power up-converter. In this up-converter the first Other known techniques to reduce the effect of LF phase shifters are assumed to be implemented in the noise in electronic circuits are chopping and correlat- digital baseband, while in the up-conversion mixers ed double sampling. The LF noise can also be all problematic harmonics due to nonlinearities of the reduced by increasing gate area of the MOSFETS, at N power amplifier stages can be cancelled via the the cost of area and/or power consumption. The poly-phase technique in combination with a 1/3 duty- switched bias technique offers an orthogonal method cycle LO-signal [6]. to reduce the intrinsic LF noise in the transistor itself. A silicon realization, designed by MSc Student It is beneficial especially in circuits where switching already occurs, such as oscillators and discrete time circuits.

Distortion Cancelling using Poly-Phase Technique In deep submicron technology, distortion becomes an increasing problem. Large signals are required for dynamic range reasons or simply because for a given radio standard dictates the output power to be Fig 6: Wide band phase shifters can be implemented with delivered by a power amplifier. The transistors, mixers, resulting in up-converter behavior. however, have less voltage gain and exhibit very non-linear behavior, which makes linear circuit design a challenge. Rameswor Shrestha, is based on the circuit of Fig. 7 We know that in differential circuit the even har- with N=18 [6]. The colors in Figure 7 correspond to monics are cancelled if the signals are in anti-phase. the colors of the functional blocks of Figure 6. With this in mind, MSc student Eisse Mensink investi- Rameswor demonstrated a power up-conversion gated whether it would be possible to use more than mixer, which is driven in compression while all har- 2 paths and multiple phases of the signal (poly-phase) monics and their sidebands, up to the 17th harmonic, and cancel more than 2 harmonics. The basic idea is still remain under -40dBc. Without this poly-phase shown in Figure 5, where the signal path is split in N topology (i.e. for N=1) the harmonics would be below separate parallel paths. only -6dBc, which clearly demonstrates the effective- N=2 equals the well-known differential circuit ness of the technique - 34 dB improvement. The RF topology to cancel even harmonics. If phase shifters frequency could be varied from DC to 2.5GHz and the are available before and after the nonlinear circuit, the final accuracy of the technique was limited by timing structure of Fig. 5 can cancel the harmonics up to N- of the LO phases. 1 [5]. The problem is however that wide-band phase Conventional RF up-converters require expensive shifters are very hard to implement with analog cir- post-filters, dedicated for every RF frequency to filter cuits. For this reason, we choose to use mixers as sec- out the harmonics and sidebands in order to satisfy ond phase shifters, as shown in Figure 6. the radio transmit mask. With this poly-phase up-con- The mixers each have a Local Oscillator (LO) input verter the harmonics can be rejected and the filter with each a different phase, equally divided over demands can be much relaxed. Applications of this 360/N degrees. Since we automatically get up-conver- poly-phase up-converter can probably be found in sion of our input signal with these mixers, we strate- wide band flexible up-converters and software radio gically changed our plan and decided to build an RF transmitters, where the actual RF frequency is a priori

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which has a loss of 33 dB at the Nyquist frequency of 2.5GHz [8] . The eye diagram for various duty-cycles is shown in Figure 9: for this 10m long cable 66% is the optimum duty-cycle. The PWM technique can compensate for higher loss compensation (33 dB in contrast to approximately 20dB for 2 tap symbol-spaced FIR) because the resulting spectrum has a better match to the skin-

Fig 7: Basic circuit of Power up-converter. Fig. 8: Transmitting a “1” using PWM pre-emphasis: tuning the duty-cycle of the 1-0 pattern can compensate for the cable response. not known and is free to be chosen in a given range. effect and dielectric loss of the cable. Still only one Pulse Width Modulation Cable Equalizer tuning “knob” is required to fit the transfer function to For digital data communication over copper cables, the cable. Moreover the technique is insensitive to electronic equalizer circuits are used to compensate slew-rate distortion and requires only two discrete for the losses and reflections over the cables. Thanks amplitudes at the TX output (with a continuously to these electronic circuits, higher data rates can be adjustable duty-cycle), which makes it suitable for achieved over relatively cheap cables. Examples are modern CMOS technologies. The technique was also USB and LAN. successfully applied earlier for very long on-chip RC A well known technique used at the transmitter limited interconnects by Daniel Schinkel and Eisse side is pre/de-emphasis, effectively high-pass filtering Mensink [7]. the transmitted signal. This way the low-pass characteristic of the cable is compensated for. These transmit pre-emphasis filters are generally implemented with Finite Impulse Response (FIR) filters, most often with just a few symbol spaced taps. As an alternative to FIR filters Daniel Schinkel and Jan-Rutger Schrader proposed Pulse Width Modula- tion (PWM) on a digitally coded signal [7,8]: If a ‘1’-bit has to be transmitted, a 1-0 pattern is transmitted in one bit time and if a ‘0’-bit has to be transmitted a 0- 1 pattern is transmitted in one bit time. This is similar to Manchester coding but with adjustable, non-50% duty-cycle. The duty-cycle of the 1-0 and 0-1 pattern is chosen in such a way that it compensates for the cable loss. This is illustrated in Figure 8, where the Fig 9: 5Gb/s eye patterns of transmitted signals (TX) and duty-cycle of a 1-0 pattern is varied and the corre- received signals (RX) for duty-cycle settings of 100% (nor- sponding cable responses are plotted. mal data) , 66% (optimal PWM) and 50% (overcompen- Thus, by changing the duty-cycle, the transmitted sated PWM) over 10m RG-58CU cable. spectrum, in which the lower frequencies are attenuated, is tuned for the high-frequency loss of the cable. Optical Detectors in Standard CMOS In a real application an adaptive loop with return- Traditionally, in optical communication extremely channel communication takes care for this tuning, high data rates have to be achieved over long dis- similar as in a conventional FIR approach. A test chip tances. Therefore optical communication is the achieved 5Gb/s over 25m of RG-58U coaxial cable domain of expensive exotic technologies and the high

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costs associated with it can be shared between many thanks to the low roll off, even +/- 20% spread in users. For optical communication over short distances time constants hardly affects the time pulses. The (meters) or very short distances (optical interconnect), resulting chip achieved 3Gbit/sec in standard 0.18μm cost issues, however, do play a crucial role. There- CMOS, with a BER of 10-11 at an optical input power fore, we started a project to integrate an optical detec- of 25μW [9]. The speed limitation was in the elec- tor in standard CMOS technology; the optical data sig- tronic circuit, and is expected to scale with technolo- nal can now shine directly on a digital CMOS chip. gy. This result enables high speed optical inputs for Due to the availability of low-cost high-speed laser at standard CMOS chips. 850nm wavelength and the compatibility with both inexpensive plastic fibers and with photo-generation Conclusion in silicon, our work mainly uses this 850nm. Several examples of new design methodologies have An essential part of an optical detector in CMOS is been illustrated. These methodologies benefit from the integrated photodiode structure, shown in the left- modern CMOS technology and may be helpful for most inset in Figure 10. future system integration. More work can be found at the URL: http://icd.ewi.utwente.nl

Acknowledgements The work described in this article has been carried out by many students; however, without the supervi- sion or help from Eric Klumperink, Anne Johan Annema, Ed van Tuijl, Ronan van der Zee, Gerard Wienk and Henk de Vries, these results would not have been here. This work has been funded by: STW, FOM and MESA+. Philips and CERN are acknowledged for providing silicon access.

References [1] F. Bruccoleri, E.A.M. Klumperink, B. Nauta, “Wide-Band CMOS Low-Noise Amplifier Exploit- Fig. 10: Transmitting a “1” using PWM pre-emphasis: tuning Thermal-Noise Canceling”, IEEE Journal of ing the duty-cycle of the 1-0 pattern can compensate for Solid-State Circuits, Vol. 39, No. 2, pp. 275 -282, the cable response. February 2004. Incident photons are absorbed in the silicon at tens [2] S. Chehrazi, A. Mirzaei, R. Bagheri, A. A. Abidi; of microns deep, much deeper than any junction in “A 6.5 GHz wideband CMOS low noise amplifi- standard CMOS. In the absorption process, electrons er for multi-band use”, 2005 IEEE Custom Inte- and holes are generated and most of them slowly dif- grated Circuits Conference18, pp. 801 - 804, Sep- fuse to the pn-junctions where the actual detection tember 2005. takes place. The slow diffusion causes the -3dB band- [3] I. Bloom and Y. Nemirovsky, “1/f noise reduc- width of the photodiode to be in the order of 5 MHz, tion of metal-oxide semiconductor transistors by which causes a serious speed problem. In literature cycling from inversion to accumulation”, Applied authors generally modify the technology, e.g. to allow Physics Letters, vol. 58, no. 15, pp. 1664–1666, high voltages and very wide depletion layers to boost Apr. 1991. the speed of the carriers, however this implies that [4] A.P. van der Wel , E.A.M. Klumperink , J. Kol- non-standard CMOS has to be used. The maximal hatkar , E. Hoekstra, M. Snoeij , C. Salm, H. speed reported in standard CMOS so far has been Wallinga and B. Nauta “Low Frequency Noise 700Mbit/sec. Phenomena in Switched MOSFETs”, IEEE Journal Ph.D. student Sasa Radovanovic implemented of Solid State Circuits, Vol. 42, No.3, March 2007. another solution. Although the -3dB frequency is [5] E. Mensink, E.A.M. Klumperink, B.Nauta, “Dis- very low, the roll-off per decade of frequency tortion Cancellation by Polyphase Multipath Cir- appears to be very low as well; only 3 to 4 dB per cuits,” IEEE TCAS-I, pp. 1785-1794, Sept. 2005. decade, up to in the low GHz region. Therefore, Sasa [6] R. Shrestha, E.A.M. Klumperink, E. Mensink, G. used an analog equalizer, with opposite frequency Wienk, B. Nauta, “A Polyphase Multipath Tech- characteristic after the transimpedance amplifier fol- nique for Software Defined Radio Transmitters”, lowing the diode to get a flat overall response up to IEEE Journal of Solid State Circuits, Vol. 41, a few GHz. One might assume that the production No.12, Dec 2006. spread in time constants between the equalizer and [7] D. Schinkel., E. Mensink, E.A.M. Klumperink, the diode itself might ruin the performance, but A.J.M. van Tuijl, B. Nauta, “A 3Gb/s/ch Transceiver

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for 10-mm Uninterrupted RC-Limited Global On- 0.13-μm CMOS”, IEEE Journal of Solid-State Cir- Chip Interconnects”, IEEE Journal of Solid State cuits, Vol. 41, No. 4, pp.990-999, April 2006. Circuits, Vol. 41, No. 1, pp. 297- 306, Jan. 2006. [9] S. Radovanovic, A.J. Annema, B. Nauta, “A 3 [8] J.H.R. Schrader, E.A.M. Klumperink, J.L. Vissch- Gb/s optical detector in standard CMOS for 850 ers, B. Nauta, “Pulse-Width Modulation Pre nm optical communication” IEEE Journal of Emphasis applied in a Wireline Transmitter, Solid-State Circuits, Volume 40, No.8, Pg:1706 - achieving 33dB Loss Compensation at 5-Gb/s in 1717, Aug. 2005.

About the Author CTIT Research Institute. His current research interest Bram Nauta was born in Hengelo, is high-speed analog CMOS circuits. Besides, he is The Netherlands. In 1987 he also part-time consultant in industry and in 2001 he received the M.Sc degree (cum co-founded Chip Design Works. laude) in electrical engineering from His Ph.D. thesis was published as a book: Analog the University of Twente, Enschede, CMOS Filters for Very High Frequencies, (Springer, 1993) The Netherlands. In 1991 he and he received the “Shell Study Tour Award” for his received the Ph.D. degree from the Ph.D. Work. From 1997-1999 he served as Associate Edi- same university on the subject of tor of IEEE Transactions on Circuits and Systems -II; Ana- analog CMOS filters for very high frequencies. log and Digital Signal Processing, and in 1998 he served In 1991 he joined the Mixed-Signal Circuits and as Guest Editor for IEEE Journal of Solid-State Circuits. Systems Department of Philips Research, Eindhoven From 2001 to 2006 he was Associate Editor for IEEE the Netherlands, where he worked on high speed AD Journal of Solid-State Circuits and he is also member of converters and analog key modules. In 1998 he the technical program committees of ISSCC, ESSCIRC, returned to the University of Twente, as full professor and Symposium on VLSI circuits. He is co-recipient of the heading the IC Design group, which is part of the ISSCC 2002 “Van Vessem Outstanding Paper Award.”

Corrections continued from page 4

Interestingly enough at the time It has always bothered me that the the idea for the planar transistor was picture of this important device conceived by Jean Hoerni in the that got preserved was of the ugly early days of Fairchild Semiconduc- chip shown in Fig. 4. The circuit tor, it had to sit untried for a couple had six bonding pads around the of years, because we did not have circumference of a circle for the technology to do four aligned mounting in an 8-leaded version mask layers. In fact, we were devel- of the old TO-5 outline transistor oping the technology to do two can. In this case only six of the aligned oxide-masked diffusions eight possible connections were plus a mesa etching step for transis- required. We did not think we Fig. 4. Photomicrograph of one of the tors. The original step and repeat could make eight wire bonds with first planar integrated circuits produced by Fairchild Semiconductor in camera that Bob Noyce designed reasonable yield, so for these first the early 1960’s. using matched 16mm movie camera integrated circuits we etched a lenses had only three lenses, so it round die that let us utilize blobs The unusual diameter of 764 could only step a three-mask set. of conducting epoxy to make con- microns was chosen because we We had to wait until the first mesa tact to the package pins. For the were working in English units and transistors were in production die in the picture, the etching that is thirty thousandths of an inch, before we could go back and figure clearly got away from the etcher. or 30mils. The minimum feature size out how to make a four mask set to is the three mil metal line making actually try the planar idea. A prior version of “The Mytholo- the circular base contact. Metal-to- The first integrated circuit on the gy of Moore’s Law,” by Tom R. metal spacing is five mils to allow graph is one of the first planar inte- Halfhill in the September 2006 issue the 2.5mil alignment tolerance we grated circuits produced. It includ- was published in Microprocessor needed. ed four transistors and six resistors. Report of December, 2004.

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TECHNICAL ARTICLES A 30 Year Retrospective on Dennard’s MOSFET Scaling Paper Mark Bohr, Intel Corporation, [email protected]

ore than three decades have passed since the Gordon Moore in 1965 and was in effect being fol- team of Robert Dennard, Fritz Gaensslen, lowed by the semiconductor industry since the early MHwa-Nien Yu, V. Leo Rideout, Ernest Bassous 1960’s. (To read reprints of Gordon Moore’s 1965 and and Andre LeBlanc from the IBM T. J. Watson Research 1975 papers along with recent commentaries on Center wrote the seminal paper describing MOSFET Moore’s Law, see the September 2006 issue of the scaling rules for obtaining simultaneous improvements IEEE Solid-State Circuits Society Newsletter.) in transistor density, switching speed and power dissi- The ideas described in Moore’s and Dennard’s pation [1]. At the time of this paper (1974), commercial- papers set our industry on a course of developing new ly available circuits were using MOSFETs with gate integrated circuit process technologies and products on lengths of approximately 5 microns, but devices with a regular pace and providing consistent improvements shorter gate lengths were already being built in labora- in transistor density, performance and power. Each new tories that were demonstrating the benefits of further generation of process technology was expected to scaling. The scaling principles described by Dennard reduce minimum feature size by approximately 0.7x (κ and his team were quickly adopted by the semicon- ~1.4). A 0.7x reduction in linear features size was gen- ductor industry as the roadmap for providing systemat- erally considered to be a worthwhile step to take for a ic and predictable transistor improvements. new process generation as it provided roughly a 2x Table I is reproduced from Dennard’s paper and increase in transistor density. During the 1970’s and summarizes transistor or circuit parameter changes 1980’s the semiconductor industry was introducing new under ideal scaling conditions, where κ is the unitless technology generations approximately every 3 years. scaling constant. The tantalizing benefits of MOSFET This translates to transistor density improvements of ~2x device scaling immediately leap out from this table: as every 3 years, but this was also a period when average transistors get smaller, they can switch faster and use chip sizes were increasing, resulting in transistor count less power. But of course learning exactly how to increases of close to 4x every 3 years (or 2x every 18 make transistors smaller in a way that could be done months). Starting in the mid-1990’s our industry accel- practically in high volume manufacturing would take erated the pace of introducing new technology genera- time. It would take time to develop lithographic tech- tions to once every 2 years and that pace continues to niques to pattern smaller feature sizes, to grow thin- this day (see Figure 1). The trend of increasing chip size ner gate oxides, and to reduce defect levels at these has slowed due to cost constraints, so we have settled increasingly challenging dimensions. But this paper into a trend of roughly doubling transistor density and gave our industry a roadmap, a method for setting tar- transistor count every 2 years (see Figure 2). gets and expectations for coming generations of Even more surprising, from a MOSFET scaling per- process technology. This paper gave us the more spe- spective, is that over the past 10 years MOSFET gate cific transistor scaling formula needed to continue lengths have been scaling faster than other minimum Moore’s Law, which was first articulated in a paper by feature sizes (see Figure 1). Prior to the mid-1990’s,

Table I: Scaling Results for Circuit Performance (from Dennard)

Figure 1: Feature size scaling for Intel logic technologies

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Figure 3: MOSFET structure from Dennard’s 1974 paper (left) and from Intel’s 65 nm generation logic technology in 2005 (right) Figure 2: Transistor count trend for Intel microprocessors gate lengths were roughly the same size as other min- improved performance and power. But this 1974 imum process features, but starting with the 0.35 μm work ignored the impact of transistor sub-threshold generation, gate lengths have been scaling faster than leakage on overall chip power. Sub-threshold leakage 0.7x per generation to realize performance advan- was relatively low in the 1970’s and was a tiny con- tages, even though gate pitch has been scaling at the tributor to total power consumption on logic circuits.

normal rate. This has been a key factor in micro- But after 30 years of scaling, VT has scaled to the point processors achieving >3 GHz operating frequencies where sub-threshold leakage has increased from lev- sooner than most experts thought possible even 10 els of <10-10 amps/mm to >10-7 amps/μm. Due to leak-

years ago. It is exciting to see in Figure 3 how far we age constraints, it will be difficult to further scale VT have taken Dennard’s scaling law by comparing the 1 and thus it will also be difficult to scale operating volt- mm transistor described in his 1974 paper to the 35 age. nm gate length transistor used in Intel’s 65 nm gener- Another key assumption in Dennard’s scaling law ation logic technology that started high volume man- was the ability to scale gate oxide thickness. Gate ufacturing in 2005 [2]. The Intel transistor shown in oxide scaling has been a key contributor to scaling Figure 3 provides an example of an emerging trend improvements over the past 30 years, but this trend is among semiconductor manufacturers: the introduc- also slowing due to leakage constraints (see Figure 4).

tion of new structures and materials to extend transis- Intel’s 65nm generation transistors use a SiO2 gate tor scaling. In this case the new feature is selectively dielectric with a thickness of 1.2 nm [2]. This dielectric deposited SiGe source-drains to provide strained sili- is only about 5 silicon atomic layers thick and repre-

con for improved transistor performance [3]. sents what is likely the limit to which SiO2 can be Just as there have been questions about the end of scaled. Not only are we running out of atoms, but gate Moore’s Law, there have also been questions about oxide leakage due to direct tunneling current is becom- the end of MOSFET scaling. In both cases, the answer ing a noticeable percentage of overall chip power. is that the end is not yet in sight, although we face Dennard’s scaling law assumed that channel dop- growing challenges in their continuation. Voltage scaling concentration could be continually increased to ing has been an extremely important component of enable shorter channel lengths with the appropriate

MOSFET scaling because it maintains constant electric VT. When channel doping concentration gets too high field, which is important for reliability, and it lowers transistor power, which is needed to maintain constant power density. But even in the early days of MOSFET scaling it was difficult to follow ideal voltage scaling requirements because of the need to use industry standard voltages, such as 12V, 5V, 3.3V, etc. Eventually we were able to deviate from standard voltage levels on key products such as microprocessors and were free to adjust product voltage levels to meet specific performance and power targets. More recently, however, voltage scaling has run into lower

limits imposed by threshold voltage (VT) scaling limits [4]. Dennard’s scaling law assumed that V would T Figure 4: Gate oxide thickness trend for Intel logic scale along with operating voltage, and thus provide technologies

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dielectrics, metal gates and multiple-gate devices have been or will be introduced to continue scaling. So although the letter of “Dennard’s Law” can no longer be followed, it has gotten us very far over the past 30 years and the spirit is alive and well in transistor R&D facilities around the world.

References [1] R. Dennard, et al., “Design of ion-implanted MOSFETs with very small physical dimensions,” IEEE Journal of Solid State Circuits, vol. SC-9, no. 5, pp. 256-268, Oct. 1974. Figure 5: Copper interconnects with low-_ dielectrics from [2] P. Bai, et al., “A 65nm logic technology featuring Intel’s 65 nm logic technology 35nm gate lengths, enhanced channel strain, 8 two problems occur: 1) carrier mobility and perform- Cu interconnect layers, low-k ILD and 0.57 μm2 ance degrade due to increased impurity scattering, 2) SRAM cell,” International Electron Devices Meet- source and drain junction leakage increases due to ing Technical Digest, pp. 657-660, 2004. direct band-band tunneling. Junction leakage is [3] K. Mistry, et al., “Delaying forever: Uniaxial already a limiter for ultra-low power integrated cir- strained silicon transistors in a 90nm CMOS tech- cuits and will eventually be a limiter for mainstream nology,” Symposium on VLSI Technology Digest microprocessor products. of Technical Papers, pp. 50-51, 2004. Although Dennard’s paper is best known for artic- [4] Y. Taur and E. Nowak, “CMOS devices below 0.1 ulating MOSFET scaling rules, less noticed was the μm: How high will performance go?” Interna- paper’s description of interconnect scaling results, as tional Electron Devices Meeting Technical Digest, reproduced here in Table II. The key point of this pp. 215-218, 1997. table is that scaled interconnects, unlike scaled tran- [5] M. Bohr, “Interconnect scaling - The real limiter sistors, do not speed up. Scaled interconnects provide to high performance ULSI,” International Elec- roughly constant RC delays because the reduction in tron Devices Meeting Technical Digest, pp. 241- line capacitance is offset by an increase in line resist- 244, 1995. ance. This was not much of a concern in 1974 when interconnect delay was typically a small portion of About the Author circuit clock cycle times. But more modern logic tech- Mark Bohr is an Intel Senior Fellow nologies have been wrestling with the constraints and Director of Process Architecture imposed by interconnect delay and interconnect den- and Integration. He is a member of sity [5], and have been addressing these constraints by Intel’s Logic Technology Development adding more metal layers, converting from aluminum group located in Hillsboro, Oregon,

to more conductive copper wires, and replacing SiO2 where he is responsible for directing dielectrics with low-κ dielectrics to reduce capaci- process development activities for tance (see Figure 5). Intel’s advanced logic technologies. As briefly described above, scaling transistors He joined Intel in 1978 and has been responsible for beyond the 65 nm generation will clearly have more process integration and device design on a variety of challenges to contend with. It is also commonly rec- process technologies for dynamic RAM, static RAM and ognized that following the simple scaling rules microprocessor products. He is currently directing devel- described by Dennard and his team back in 1974 is opment activities for Intel’s 32 nm logic technology. now no longer a sufficient strategy to meet future Bohr was born in Chicago, Illinois in 1953. He transistor density, performance, and power require- received the B.S. degree in industrial engineering in ments. But ours is a very inventive industry and new 1976 and the M.S. degree in electrical engineering in transistor technologies such as strained silicon, high-κ 1978, both from the University of Illinois, Urbana- Table II: Scaling Results for Interconnect Lines (from Dennard) Champaign. In 1998 he received the Distinguished Alumnus Award from the University of Illinois department of Electrical and Computer Engineering. Bohr is a Fellow of the Institute of Electrical and Electronics Engineers and was the recipient of the 2003 IEEE Andrew S. Grove award. In 2005 he was elected to the National Academy of Engineering. He holds 42 patents in the area of integrated circuit processing and has authored or co-authored 40 published papers.

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TECHNICAL ARTICLES Device Scaling: The Treadmill that Fueled Three Decades of Semiconductor Industry Growth Pallab Chatterjee, i2 Technologies, Inc.

n 1974 Robert Dennard, etal1, wrote a paper that of linear relationships between different device explored different methods of scaling MOS devices, geometries to simplify the “design rules” that abstract- Iand pointed out that if voltages were scaled with ed the manufacturing constraints from design. Linear lithographic dimensions, one achieved the benefits we device scaling theory also allowed simplification of a all now assume with scaling: faster, lower energy, and very complex interaction of process and device cheaper gates. The lower energy per switching event physics with design. exactly matched the increased energy by having more Device models to represent the complex physics of gates and having them switch faster, so in theory the CMOS devices in circuit simulators, like SPICE, provided power per unit area would stay constant. This set of lin- the abstraction between circuit theory and device ear scaling principles of MOS technology has served as physics. Based on these abstractions the industry was the treadmill on which the entire Semiconductor Indus- able to rapidly develop design tools and systems. The try has grown for the past three decades. University of California, Berkeley4 was a leader in developing a suite of design tools that connected logic level Scaling in the 70’s: The Era of NMOS design to circuit design to physical design and verifica- Dynamic Random Access Memories tion tools to check for design rules. The entire ASIC The late 70’s NMOS based DRAMs led the technology world of semi-custom chips opened up based on this set scaling charge in a world that was still largely bipolar and of abstractions and made scaling applicable to all chips. dominated by TTL logic chips. The first rounds of the application of scaling theory were focused on DRAMs. The Emergence of TCAD: Systematic Unique clock design schemes for DRAMs devised at Technology Design Mostek and technology from Intel and IBM ushered in The notion of creating generations of process tech- the 16k bit VLSI DRAM, the pride of the late 70’s. nology that could be used for a variety of applications Japan’s MITI created the VLSI Technology Project2, was emerging simultaneously with the ASIC move- a consortium of five top Japanese microelectronics ment to systematize chip design. Linear scaling factors companies: Hitachi, NEC, Fujitsu, Mitsubishi and began to be used as the names of the generation of Toshiba. This consortium developed a complete tech- technology and an informal time table started being nology infrastructure for the 256K DRAM and discussed across the industry. A team at Stanford Uni- launched into the 1 micron VLSI era with strong versity initiated a whole new field of technology CAD5 progress in ultra clean technologies which gave Japan with Process Simulators and Device Simulators. This the lead in VLSI manufacturing in the early 80’s. allowed systematic design of process and devices using formal design of experiment methods. The Early 80’s: Crossing the Micron Barrier Manufacturing yield and defect analysis did not come Even though the scaling charge was led by NMOS, under the purview of scaling theory and threatened to power and ease of design considerations favored stop the scaling treadmill. Redundancy and repair tech- CMOS Technology as the industry workhorse. The niques based on laser links were the initial answer to world, however, was stuck at the TTL voltage and continue memory scaling beyond 256 Kbit. This was logic level standard or 5V. The resistance to scaling followed by yield analysis tools that were developed at voltage in the early 80’s from system designers backed Carnegie Mellon University6. Defect measurement tools into the semiconductor world. This led me to propose offered by KLA, systematic yield analysis and ramp a quasi constant voltage scaling3.The emergence of processes made the technology treadmill continue to voltage tolerant device structures like the lightly dope move down the linear scaling path. drain (LDD) transistor, silicide clad source drain, and hot electron defense resulted from this. These tech- Single Wafer Manufacturing Systems for nologies provided some of the keys to continue scal- Scaling to Larger Wafers with Sub Half ing feature sizes slower than voltage and continuing Micron Features the treadmill for the Semiconductor Industry. From 1988 through 1993 Texas Instruments partnered with DARPA, the U.S. Air Force, semiconductor equip- ASIC and CAD Transforms the Chip Design ment makers, and university researchers in the Micro- Industry electronics Manufacturing Science and Technology Carver Meade and Lynn Conaway in their classic (MMST) Program7. Its purpose was to develop advanced book, ‘Introduction to VLSI Systems’, used the notion IC manufacturing technologies enabling dramatic

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improvements in process control, cycle-time, and overall temperature control. Some of the initial MMST work flexibility and continue the scaling of devices to deep on RTP lamps was performed in collaboration with submicron to cost effectively. In particular, the MMST Stanford University. Applied Materials, Inc. subse- Program demonstrated the technical feasibility of 100% quently introduced RTP on their Centura HT™ cluster single-wafer processing, dynamic/object-oriented Com- tool. MMST also created the first lithography cluster puter-Integrated-Manufacturing (CIM), real-time/model- tool and the concept of the vacuum carrier which is based process control, in-situ sensors, 95% dry process- more popularly knows as the SMIF box. ing, and integrated mini environments. At that time, state-of-the-art commercial wafer fabs SIA Industry Roadmap used a mix of approximately 60% single-wafer and In November 1992, 179 of the key semiconductor tech- 40% batch processing equipment. Since then, com- nologists of the US gathered in Irving, Texas for a his- plete sets of commercial single-wafer process tools toric workshop to create a common vision for the course have become available and are the norm for deep of the semiconductor industry for the next 15 years submicron manufacturing. based on scaling technology8. The group consisted pri- The most significant contribution of MMST to sin- marily of scientists and engineers from the US Semicon- gle-wafer processing was in the area of Rapid Thermal ductor Industry and a liberal sprinkling of academics, Processing (RTP). In contrast to large furnaces for government agencies and national laboratories. The thermal processing, the MMST program developed workshop, sponsored by the Semiconductor Industry processing chambers in which single wafers were Association and coordinated by Semiconductor Research heated by lamps under multi-zone, closed-loop wafer- Corporation and Sematech, created the roadmap below. 1992 SIA Overall Roadmap Technology Characteristics

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Five areas of critical challenges that could decrease ments of the entire industry on the key technology the rate or even stop the progress of scaling of Semi- issues has indeed been an enabler for scaling down conductor technology were identified: to 90nm. The top three among these are: • Patterning material and processes for device structures below 0.25μm 1. Sub-wavelength optical lithography (including • Electrical interconnections, both on and off chip OPC/Resolution Enhancement Techniques): • Electrical test, time cost and capability • Design, modeling, simulation capability for all Advances in scanners and resist technology elements of IC technology and products enabled printing features less than one-half of the • Software capability, availability and quality for all light wavelengths. Chemically amplified resists, aspects of IC technology and production. light polarization, phase shifting techniques (alter- As we look back at the last 15 years now at the end nating apertures and attenuated), as well as com- of 2006, this roadmap has truly focused the invest- prehensive Model Based Optical Proximity Correc- ment and made most of the predictions come true. tions of critical layer layouts, are the key enablers.

Emergence of Foundry Manufacturing 2. Extending bulk CMOS by several performance Companies boosters - stress/strain, ultra shallow junctions, and As the process technology scaling became more sys- ox nitrides: tematic the disaggregating of IC manufacturing became a reality. Since the establishment of TSMC in Conventional bulk CMOS device architectures have 1987 to satisfy customers’ needs under the disintegra- been extended to 90 nm and below technology tion trend, the pure play foundry industry has grown nodes by employing several performance boosters to a multi-billion business. In turn, the pure play such as: foundry business model has further accelerated the - bi-directional stress/strain layers to enhance disintegration trend in the semiconductor industry. carrier mobility for both electrons and In the past decade, leading foundry companies have holes, caught up with the leading IDMs (Integrated Device - ultra-shallow junctions obtained by very Manufacturers) in process technology prowess. The low energy implants and flash/laser technological challenges of foundry companies in the anneal next decade will be even more challenging than those - very thin (1.2 nm) gate ox nitride layers that of leading IDMs because of the need to emphasize provide uniform layers, good interface to more on process versatility, cost effectiveness and easy both substrate and polysilicon gate and pre- adoption by diversified customers. vent Boron penetration. The specific technology development challenges of a successful foundry company in the next decade 3. Multilevel Cu interconnect including CMP: include: (1) aggressive scaling of transistors, interconnect, and design rules for both performance and den- Up to 12 layer of Cu interconnect layers have been sity; (2) embedded technologies for SOC solutions; (3) achieved thanks to Double Damascene Cu deposi- cost effective and manufacturability process technolo- tion/patterning technology and improvement in chem- gy; (4) a versatile technology portfolio; and (5) easy ical mechanical polishing. Dishing/erosion effects integration among customers, design service/IP have been reduced by applying smart dummy fill and providers and the foundries. additional manufacturability layout design rules to In the next decade, the foundry paradigm is eliminate wide lines/small spacing patterns and dras- expected to play an even more important role as tic density variations within each interconnect layer. foundry companies continue to build their core com- petencies, including leading-edge process technolo- As we look forward to the continuation of these 30 gies, advanced and flexible manufacturing capabili- years of scaling progress, there are similar chal- ties, and customer-oriented services systems. The lenges to overcome to scale to 45nm and below: strong entrenchment of the foundry industry will further move the semiconductor industry in the direction 1. Device/process variability9: of complete disintegration. Process variability sources can be categorized based Scaling continues to be the Treadmill of the on the spatial hierarchy: lot-to-lot, wafer-to-wafer, Semiconductor Industry within-wafer or within-die, or root causes (random Looking back at the last few years since the first SIA or systematic). These sources create a complicated workshop, the ability to marshal and focus the invest- distribution of parameters that must be addressed

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by circuit designers. One of the key parameters is due to in-situ equipment sensor/FDC deployment. poly linewidth, since it has the dominant effect on MOS transistor electrical performance. For 90nm 5. Compact device models: technologies, more than 50% of the variance in poly line width comes from within-die (within field) vari- Below 100 nm, compact device models must ations. The next component is die-to-die. The per- accommodate microscopic (i.e., “non-bulk”) physi- centage of systematic variations increases with cal effects with minimal impact on overall compu- device scaling. For 90nm NMOS transistors, it reach- tational complexities. BSIM has filled this role for es 40% of the overall Across Chip Variance (ACV). many technology generations as the workhorse, both for model characterization and node-to-node Transistors behave differently based upon the technology predictions. It continues to have the neighborhood layout pattern due to printability and confidence of industry and seems likely to remain stress/strain effects. Moreover, printability and in service (with the possible exception of RF) down Chemical Mechanical Polishing (CMP) cause signif- to about 45 nm. icant variations in interconnect parameters such as resistance and capacitance. More recent MOS models are formulated as functions of surface potential, rather than threshold 2. New device architecture (UTB, dual gates) less voltage, in the channel and s/d edges. Surface dependent on channel doping fluctuations: potential is directly linked to intrinsic channel charge dynamics and enables addition of important Despite quite a few novel device architectures pro- physical effects with an economy of model com- posed in recent years (FinFET, Ultra Thin Body plexity. The formulation admits an expression for Transistor, Inverted T FET), the bulk CMOS device transistor drive current that is continuous from architecture is used virtually exclusively at 45 nm. accumulation to saturation, thereby avoiding the It will most likely dominate the 32 nm nodes, necessity of matching multiple regions. although SOI substrates are gaining more acceptance. This leaves the device performance variations Compact models at 65 nm have high priority needs very susceptible to random dopant fluctuations. for improvement: Performance boosters are additive and help, but (a) scalability of sub-threshold currents and output also create additional variability sources which resistance from short-to-long channel lengths, forces circuit designers to accept much higher vari- due largely to lateral doping non-uniformities ability and as well as leakage currents. (b) dependence of noise on voltage and geometry; i.e., considering 1/f noise dependence on ran- 3. Material improvements: high-k for gate dielectrics, dom noise trap occurrences porous low-k for interconnects: (c) capabilities for handling geometrical statistical fluctuations which affect noise, threshold volt- Several candidates for high-k materials have been age and drive current. explored; but although Hf or Zr based oxides/sili- cates provide attractive dielectric constant values The above problems become more severe at 45 nm,

and are stable, they do require interfacial SiO2 lay- along with the following additional priorities: ers between high-k layers and substrate/polysili- (1) gate current scaling and dependences on novel con. The final stack is not as beneficial anymore. (e.g., multi-layer) gate stacks, Hence, high-k gate dielectrics are not employed in (2) carrier mobility in the channel due to layout- the vast majority of 45 nm technologies and only in induced stress/strain, combination with metal gates do they have a (3) statistical variations stemming from random chance at 32 nm. dopant placements, (4) ballistic transport of carriers in intrinsic channel 4. Advanced process control (especially feed forward): and, (5) quantum mechanical effects due to confine- Given the increasing complexity and small process ment in thin films. windows, yield variability is a very significant problem. Baseline process variability keeps on increas- Summary ing (tails of wafer yield distributions) and the pres- Scaling theory has been the organizing principle of the ent metrology/inspection static sampling plans fail progress of the semiconductor industry throughout at detecting excursions in-line. New approaches for three decades. It has created a framework for contin- yield relevant SOC and APC are needed to take ued improvement in density and cost performance advantage of the increased process observables and facilitated the desegregation of the entire industry

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About the Author around design and manufacturing. Few concepts in Dr. Pallab Chatterjee is Executive our time have had as much influence on the economy. Vice President, Solutions Officer and Chief Delivery Officer of i2 Tech- Acknowledgement nologies, Inc. I would like to thank Ping Yang, Bob Doering, He is responsible for Solutions Andrzej Strojwas, Robert Dutton, Bill George, Operations, which includes Solu- Lawrence Arledge, and Alberto Sangiovanni-Vincen- tion business units for SRM and telli for providing perspectives on the various aspects MDM, Research and Development, of impact of scaling on the semiconductor industry for Information Technology, Global Solution Center, this paper. Global Customer Solution Management and i2’s India Operations. References During his tenure at i2 Dr. Chatterjee has overseen the [1] R.H. Dennard, F.H. Gaensslen, V.L. Rideout, E. evolution of i2’s industry-leading solutions, including the Bassous, andA.R. LeBlanc, “Design of Ion- development and delivery of the i2 Agile Business Implanted MOSFET’s with Very Small Physical Process Platform and the company’s new-generation Dimensions,” IEEE Journal of Solid-State Circuits, supply chain management solutions. His extensive glob- Oct. 1974. al management experience and an in-depth understand- [2] Cheney, D.W. and Grimes, W.W. Japanese Tech- ing of i2’s market-leading supply chain solutions from a nology Policy: What’s the secret (February 1991), customer's perspective have made him a valuable addi- Council on Competitiveness, pp. 1-26. tion to the i2 team since his arrival in January 2000. [3] P. K. Chatterjee, W. R. Hunter, T. C. Holloway, Chatterjee worked at Texas Instruments from 1976- and Y. T. Lin, “Technology Induced Non-Con- 2000. During his tenure there he held various execu- stant Field Scaling and its Impact on Submicron tive positions. Under his leadership as senior vice Device Performance,” Dev. Res. Conf., Cornell, president of Research and Development and chief June 1980 technology officer, the Texas Instruments Technology [4] Alberto Sangiovanni-Vincentelli, Editorial, Spe- Labs became known as a standard for excellence cial Issue on CAD of VLSI, IEEE Transactions of acknowledged by both academia and industry. As TI’s Circuits and Systems, July 1981. and Richard senior vice president and chairman of the Manufac- Newton, Donald O. Pederson, Alberto Sangio- turing Excellence team, he was responsible for man- vanni-Vincentelli, and Carlo Sequin, Design Aids ufacturing improvements which delivered hundreds for VLSI: The Berkeley Perspective, IEEE Transac- of millions of dollars in bottom-line improvement. As tions on Circuits and Systems, Vol. CAS-28, No. president of TI’s Personal Productivity Products (cal- 7, pp. 660-680, July 1981 culators and PC business), he contributed to increas- [5] D. A. Antoniadis and R. W. Dutton, Models for ing Texas Instruments’ market share and managed Computer Simulation of Complete IC Fabrication more than $1.5 billion worldwide. In the role of chief Process. IEEE J. Solid-State Circuits, SC-14(2):412- information officer, he led the global i2 and SAP 430, and Robert Dutton: Father of TCAD- implementation and process transformation for Texas http://www10.edacafe.com/nbc/articles/view_ar Instruments. ticle.php?articleid=315936 During Chatterjee’s tenure at Texas Instruments, he [6] W. Maly, A.J. Strojwas and S. W. Director, “VLSI was a TI senior fellow in 1985, an IEEE fellow in 1986, Yield Prediction and Estimation - A Unified and received the IEEE J. J. Ebers award in 1986. He Framework,” IEEE Trans. on CAD of ICAS, Spe- was elected a member of the National Academy of cial Issue on Statistical Design, Jan.1986 Engineers in 1997. [7] R.R. Doering and D.W. Reed, “Exploring the Lim- Chatterjee has been awarded numerous patents and its of Cycle Time for VLSI Processing,” Technical has written several publications on the high technolo- Digest of the 1994 Symposium on VLSI Technol- gy industry. He earned a Bachelor of Technology ogy, pp. 31-32, Honolulu, Hawaii, June 7, 1994. degree in electronics and communication engineering [8] Semiconductor Technology Workshop Conclu- from the Indian Institute of Technology, Kharagpur, sions Report 1992. Linda Wilson, International India. As a student there, he was awarded the Presi- Technology Roadmaps for Semiconductors dent of India Gold Medal as the class valedictorian and Sematech and http://www.reedelectronics.com/ the B.C. Roy Memorial Gold Medal for extracurricular semiconductor/article/CA490081 excellence. He received his master's and doctorate [9] A. J. Strojwas, “Conquering Process Variability: A degrees in electrical engineering from the University of Key Enabler for Profitable Manufacturing in Illinois, and was awarded a honorary Doctor of Sci- Advanced technology Nodes”, Keynote Paper, ence Degree from Indian Institute of Technology, ISSM 2006, Tokyo, Japan, September 2006 Kharagpur, India.

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TECHNICAL ARTICLES Recollections on MOSFET Scaling By Dale L. Critchlow, IBM Fellow, Retired; [email protected]

The Beginnings doping levels were scaled by a constant factor κ: a) the By 1970 the MOSFET technology was finding its way circuit delay was decreased by κ, b) the power/circuit was into manufacturing in a number of companies.1 Bob decreased by κ2, and c) the power delay product was Dennard and I were part of the team that developed the reduced by κ3. Further, the power/unit area of silicon NMOS technology (2) in the T. J. Watson IBM Research remained constant! These were exactly the results we Laboratories in the 1960s. The first IBM NMOS MOSFET needed to develop a competitive low cost memory. On product, which was entering large scale manufacturing, the down side, there were questions about the scalability was a high-speed main-memory with a 50ns typical of the threshold voltage and the fact that the IR drops and access time (100ns spec) at the board level. It used 1Kb RC time constants of the interconnects become more chips (soon replaced with 2Kb chips) with a six-device severe with scaling. Of course, there were a host of tran- cell using off-chip bipolar sense amplifiers and high sistor design, process and reliability challenges. level decoders proposed by Peter Pleshko and Lewis At that point, we were convinced that MOSFET mem- Terman (3). These chips replaced the bipolar main- ory would replace fixed head files. Further, we speculat- memory technology which had been introduced a cou- ed that it may also replace moveable head disk storage ple of years earlier to replace ferrite core memory. for some applications. We also started to believe that the In mid-1970, IBM Research management was search- MOSFET would someday replace the bipolar transistor in ing for a technology to fill the “file gap” between move- high-performance logic and memory applications. able head magnetic disks and random access main-memory for transaction based systems. This performance gap Driving the Demonstration and was being filled by expensive fixed head HDDs which Implementation of Scaling was Key had much smaller latency time than the moveable head Bob Dennard’s most profound contributions were to HDDs. Don Rosenheim (Manager of Applied Research) demonstrating the feasibility of MOSFET scaling, and and Sol Triebwasser challenged my department to devel- then leading the way into implementation in real prod- op a proposal for a “monolithic file” with a cost/bit of ucts. He worked with a succession of very talented engi- about 1 millicent/bit or 1/1000 of the projected main- neers over several decades, providing guidance as well memory cost. Bob Dennard was manager of a small as continuing to make significant technical contributions. group including Fritz Gaensslen and Larry Kuhn which The principles of scaling were first presented at the reported to me. There were a number of options includ- 1972 IEDM (4) along with the design and experimen- ing shift registers and CCDs, but Dennard as the inven- tal characteristics of an ion-implanted 1μm transistor tor was keen on pursing the one-transistor DRAM cell. with a 20nm gate oxide2 which had been optimized Bob did some preliminary analyses, and concluded that for scaling. One of the original slides used to describe we would need feature sizes of about 1μm, a 5X shrink scaling is shown in Fig. 1. (Bob remembers a high from those in manufacturing, to achieve our goals. degree of skepticism about the feasibility of 20nm We realized that we would have to scale the vertical dimensions (oxide thickness and junction depth) and adjust the doping level of the substrate to maintain usable device characteristics. Further, we would have to scale the operating voltages as well to preserve reliability and limit power dissipation. In fact, we had done this twice before in the 1960s, first from 24V to 12V and then to 6V using rudimentary scaling to guide our designs. (Engi- neers of that era, before the advent of computer simulation, were well versed in design by similitude or scaling.) We observed that our current transistors with channel lengths of 5μm and gate oxide thickness of 100nm could be operated at 20V. Therefore, we could scale to a 4V power supply with a 1um, 20nm transistor. We noted that the circuits would consume less power and be faster. Within a few days Bob, Fritz and Larry had formalized the constant-field scaling theory and its limitations. The implications of scaling were remarkable. If all Fig. 1 Slide from 1972 IEDM showing some of the scaling dimensions, voltages (including threshold voltage) and principles.

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oxides from the audience many of whom were strug- Vacuum Science and Technology (13) which showed gling with making reliable 100nm oxides.) This was the practicality of scaling to submicron devices and soon followed with a 1973 IEDM paper (6) utilizing described the hierarchical wiring system needed to ion-implantation to allow improved scaled transistors. take advantage of scaling. In 1985 he published an The paper normally considered the “scaling paper” authoritative paper on scaling to deep sub-micron was published in 1974 (7). In 1975 Dennard, with oth- dimensions in Physica (14). ers, proceeded to demonstrate scaling on a complex Although he was not listed as an author, Bob had a chip by scaling an existing 8Kb PMOS chip (original- major influence on the keystone 1988 paper (15) by Bijan ly designed in 3.75μm ground rules) by 3X and fabri- Davari, et al, which described the 2.5V, 0.25μm CMOS cating it with 1.25μm feature sizes using electron technology which was key to the replacement of bipolar beam lithography (8). A photo of several cells and technologies for high-speed main-frame computers and support circuits is shown in Fig. 2. Hwa Yu developed microprocessors. an anisotropic dry etching process which made it possible to delineate the 1.25μm features. The success of Technical Challenges and Advances to this experiment had a major impact on how seriously Make Scaling Feasible people took scaling both inside and outside IBM. Even though the principles of scaling, and the under- Attention was then turned to high-speed logic and standing that the MOSFET could be scaled existed in SRAM. One of our goals was to lay the groundwork for the early 1970s, the benefits of scaling could not have replacing bipolar transistors in mainframe computers. been accomplished without many other technical This culminated in a series of eight papers (9) describ- advances in the industry over the decades. There were ing a 1μm technology that took advantage of the scaling remarkable improvements in optical lithography, dry principles. Bob was coauthor of several of the papers. etching, ion implantation, insulators, polycide and sili- Bob continued to push the envelope with a large num- cided contacts, multilevel metal, planarized BEOL, cop- ber of publications in cooperation with a succession of per wiring, shallow trench isolation, packaging, design young researchers. Describing these papers is well techniques, testing and characterization, design tools beyond the scope of this paper. However, a few key and system architecture. The switch to CMOS was criti- papers stand out. In 1984, with Giorgio Baccarani and cal to containing the level of chip power. Matt Wordeman, he generalized the scaling theory to take These improvements allowed scaling of the MOS- into account the parameters which did not scale well (10). FET technology to meet the expectations of the indus- In 1985, he co-authored a definitive paper on 1μm CMOS try following the trends popularized in recent decades (11) with Yuan Taur and others. In 1995, a paper laying as Moore’s Law (16). the groundwork for a 0.1mm CMOS on SOI technology was published by Ghavam Shahidi and others (12). The Long Delay before Switching to Lower In addition, Dennard furthered the cause and pre- Power Supply Voltages sented the challenges of MOSFET scaling to technical While the advantages of scaling were apparent to many audiences outside the IEEE organization. For exam- people, it was two decades before the power supply ple, he published a paper in 1981 in the Journal of was scaled for mainstream products, Fig. 3. The indus-

Fig. 2 Photograph of portion of experimental 8Kb DRAM Fig. 3 Transition of mainstream MOSFET products from 5V chip using 1.25μm features which was scaled from a to scaled voltages occurred two decades after scaling 3.75μm design. principles were defined.

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try settled on 5V supplies in the early 1970s to be com- large number of outstanding engineers in IBM, other patible with bipolar TTL. In fact, this was a lower volt- companies and Universities who shared an incredible age than what could have been possible for the dimen- 40 year journey in MOSFET technology. sions being used. Consequently, the improvements in transistor design and chip fabrication were applied to References 5V technologies, significantly improving component [1] To the Digital Age: Research Labs, Start-Up Compa- packing density and performance over several genera- nies, and the Rise of the MOS Technology; Ross K tions. Further, the LDD device (17) allowed reliable Bassett, The John Hopkins University Press, 2002. operation and high performance at 5V. The tighter tol- [2] “Design and characteristics of n-channel Insulated- erances necessary to make scaling practical improved gate Field-Effect Transistors”; D. L. Critchlow, R. H. 5V designs as well, reducing the performance advan- Dennard, S. E. Schuster; IBM Journal of Research tage of full scaling. Most importantly, the whole com- and Development, vol. 17, no. 5, p. 430, 1973. puter industry was optimized around a 5V power sup- [3] “An investigation of the potential of MOS transistor ply and very successful products were being delivered. memories”; P. Pleshko and L. M. Terman; IEEE An earlier switch to a lower voltage would have been Transactions on Electronic Computers, vol. EC-15, greatly disruptive to the designers, the manufacturers No. 4, pp. 423-427, August 1966. and in the marketplace. [4] “Design of micron MOS switching devices”; R. H. The 5V standard finally collapsed in the late 1980s Dennard, F. H. Gaensslen, L. Kuhn, H. N. Yu; IEDM due to three major forces: Tech. Dig., pp. 168 - 170, December 1972. 1) The power dissipation at 5V became untenable, [5] “Fundamental limitations in microelectronics – 1. especially as the circuits were driven to higher MOS technology”; B. Hoeneisen and C. Mead, Solid speeds. State Electronics, vol. 15, no. 7, pp. 819-829, July 1972. 2) The portable, battery-powered applications were [6] “Ion implanted MOSFETs with very short channel demanding higher performance, low power and lengths”; R. H. Dennard, F. H. Gaensslen, H. N. Yu, compatibility with battery voltages. V. L. Rideout, E. Bassous, A. LeBlanc; IEDM Tech. 3) The inherent speed advantages of scaled transis- Dig., pp. 152 - 155, December 1973. tors, as tolerances improved, were needed for [7] “Design of ion-implanted MOSFET's with very small high-speed applications. physical dimensions”; Robert H. Dennard, Fritz H. Once the dam broke there was tremendous change Gaensslen, Hwa-Nien Yu, V. Leo Rideout, Ernest within a few years, first to 3.3V then to 2.5V, etc. Bassous, Andre R. LeBlanc; IEEE Journal of Solid- State Circuits, vol. 9, pp. 256 - 268, October 1974. The Impact of MOSFET Scaling has been [8] “Fabrication of a miniature 8-Kbit memory chip Monumental using electron beam exposure”; H. Yu, R. Dennard, Scaled CMOS has become the dominant technology T.H. P. Chang, C. Osburn, V. DiLonardo and H. for digital and many analog applications and will con- Luhn; J. Vac. Sci. Technol., vol. 12, no. 6, p.1297. tinue to be a fundamental driving force of the indus- Nov./Dec. 1975. try for years to come. [9] “1 mm MOSFET VLSI technology: Parts I-VIII”; IEEE By the late 1980s, DRAM had long displaced fixed Journal of Solid-State Circuits, vol. SC-14, pp. 240- head files in the file gap. In recent years, we have 301, April 1979. been seeing flash memory replacing disk drives in [10] “Generalized scaling theory and its application to a many portable applications. _ micrometer MOSFET design”; Giorgio Baccarani, The 2.5V CMOS technology (15) was the death Matthew R. Wordeman, Robert H. Dennard; IEEE knell for high performance silicon bipolar technolo- Trans. Electron Devices, vol. 31, pp. 452 - 462, April gies in high-end computers. BiCMOS had gathered 1984. some momentum, but when designers came to real- [11] “A self-aligned 1-μm-channel CMOS technology ize that very effective off-chip drivers could be made with retrograde n-Well and thin epitaxy”; Yuan using MOSFET circuits, BiCMOS soon faded. By the Taur, Genda J. Hu, Robert H. Dennard, Lewis M. early 1990s, the high-end computers were being Terman, Chung-Yu Ting, Karen E. Petrillo; IEEE designed using low-voltage scaled CMOS (18) replac- Journal of Solid-State Circuits, vol. 20, pp. 123 - 129, ing bipolar chips. Bipolar and BiCMOS have found February 1985. new applications for very high-speed applications [12] “A room temperature 0.1μm CMOS on SOI”; G. G. using more exotic technologies. Shahidi, C. A. Anderson, B. A. Chappell, T. I. Chap- pell, J. H. Comfort, B. Davari, R. H. Dennard, R. L. Acknowledgements Franch, P. A. McFarland, J. S. Neely, T. H. Ning, M. The author is indebted to B. Davari, R. H. Dennard, R. Polcari, J. D. Warnock; IEEE Transactions on E. J. Nowak and L. M. Terman for providing informa- Electron Devices, vol. 41, issue 12, pp. 2405-2412, tion for this paper. He also wishes to acknowledge a Dec. 1994.

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[13] “CMOS scaling for high performance and low About the Author power – The Next Ten Years”; B. Davari, R. H. Dale Critchlow is a retired electrical Dennard, and G. G. Shahidi; Proceedings of the engineer with 35 years experience IEEE, Vol. 83, No. 4, pp. 595-606, April, 1995. Earli- at IBM and 15 years in academia. er version published in Nikkei Microelectronics, pp. He received his Ph.D. in Electrical 144-1`54, September 1994. Engineering from Carnegie Institute [14] “MOSFET miniaturization – From one micron to the of Technology in 1956. After teach- limits”; R. H. Dennard and M. R. Wordeman; Physi- ing at CIT for two years, he joined ca B + C, vol. 129, pp. 3-15, 1985. IBM Research. He became one the [15] “A high performance 0.25 μm CMOS technology”; early members of the NMOS MOSFET project in the B. Davari, W. H. Chang, M. R. Wordeman, C. S. Oh, T. J. Watson Research Center in 1964, where he Y. Taur, K. E. Petrillo, D. Moy, J. J. Bucchignano, H. managed the MOSFET device and circuit design Y. Ng, M. G. Rosenfield, F. J. Hohn, M. D. Rodriguez; work through 1976. Next he transferred to the IBM IEDM Tech. Dig., pp. 56 - 59, December 1988. Components Division, first in East Fishkill, NY, and [16] Research Highlights with focus on Moore’s Law; then in Essex Junction, VT where he managed a IEEE Solid-State Circuits Society Newsletter, vol. 20, group responsible for the advanced development of no. 3, September 2006. MOSFET logic and memory technologies. He retired [17] “Fabrication of high-performance LDDFET's with from IBM in 1993 and was faculty member at the oxide sidewall-spacer technology”; Paul J. Tsang, University of Vermont until 2005. He has active in Seiki Ogura, William W. Walker, Joseph F. Shepard, IEEE activities and has published a number of Dale L. Critchlow; IEEE Trans. Electron Devices, vol. papers and patents. 29, pp. 590 - 596, April 1982. Dr. Critchlow is a Life Fellow of the Institute of [18] “Possibilities of CMOS Mainframe and its Impact on Electrical and Electronic Engineers, an IBM Fel- Technology R&D”: A. Masaki, Symposium on VLSI low and a member of the National Academy of Technology, May 28-30, 1991, pp. 1-4. Engineers.

1 Ross Bassett wrote an excellent Ph.D. thesis and published a book [1] on the early history of the MOSFET technology. The appendices have a wealth of authoritative historical information. 2 Concurrently, B. Hoeneisen and C. Mead published a theoretical paper [5] projecting that a 0.4mm transistor with 14nm oxides and 2V operation could be built. The Business of Scaling Rakesh Kumar TCX Inc., Technology Connexions San Diego, CA [email protected]

n addition to technical challenges, managing the eco- roughly 20% of worldwide electronics sales and about nomics of scaling and increasing demand have been 2% of the worldwide GDP4. Fueling the growth has Ikey factors in driving the semiconductor industry to been increasing demand for components for personal nearly $250B over the last 40+ years. The functionality per computers, automotive, mobile wireless and consumer chip has increased 2x every two years1,2. Although the cost of wafer fabs and manufacturing has increased significantly over the years, the semiconductor industry has maintained a reduction of about 29%/year in the cost per function (CPF)3. This translates to a halving of the CPF every two years1. In this paper we will provide an overview of salient business aspects and economics of scaling.

1. Introduction Since the introduction of the first commercial integrated circuit in 1961 and the introduction of the first microprocessor in 1971, the semiconductor industry has experienced a healthy growth of approximately 15% CAGR4. In the mean time semiconductor sales have grown more rapidly than the worldwide electronics sales and the worldwide GDP and are now Figure 1 Worldwide semiconductor sales

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products. Although the growth rate is predicted to slow used to estimate yield. Examples are the number of down, the industry has demonstrated much resilience vias and contacts in a design, the number of metal layer in combating technical and business challenges. cross-overs, and the like. A detailed discussion of these Taking advantage of scaling, the industry has is beyond the scope of this paper. increased the number of components per chip steadily, as shown in Figure 2. This figure shows the historical 3. Overall Cost Reduction increase in the number of transistors per chip (39% per A key factor in managing the business feasibility of scal- year average) in industry leading microprocessors4. This ing is the semiconductor industry’s ability to maintain an trend shows a doubling of the transistors per chip every overall CPF reduction of 29%/year3 to 35%/year4. Within two years. This trend was predicted by Gordon Moore any given process technology node the die cost and CPF and has become known as “Moore’s Law”1,2. The figure are reduced due to the manufacturing and defectivity also shows the reduction of minimum feature size at an learning curves. This is shown graphically in a concep- average rate of 12% per year. The number of transistors tual chart, Figure 3. As the volume of wafer and product per chip has increased 6 orders of magnitude while the shipments ramps up in each technology node, there is a minimum feature size has been scaled down over two reduction in die cost (and therefore CPF) due to a reduc- orders of magnitude during the last 35 years. tion in wafer cost; this decrease is due to process optimization and the manufacturing learning curve. Also, die cost is reduced as yield enhancement efforts are implemented, defectivity is reduced, yield increases and therefore NDPW increases. A compilation of defect density trends indicates an average reduction of 19% per year over the last 35 years4. The technology “cross-over” occurs when the CPF in the newer technology is below the CPF in the older technology.

Figure 2 Historical trends of transistors per chip and minimum feature size 2. The Basic Cost Equations The basic equation for predicting the cost of an integrated circuit die (or “chip”) is:

Die Cost = Wafer Cost / Net Die per Wafer

where wafer cost is determined by factors such as Figure 3 Cost per function and technology “cross-over” facilities and equipment depreciation, materials, labor points and processing cost, and 4. Cost Reduction from Technology Scaling Net Die per Wafer (“NDPW”) = Yield* Gross Die per An industry target has been to reduce minimum fea- Wafer (“GDPW”) ture size by around 30% at every process technology transition. Table 1 shows the various process technol- Gross Die per Wafer (“GDPW”) = Total usable Area on ogy generations or “technology nodes” used since the the Wafer / Die Area mid 1980’s. Yield is a function of defectivity (or defect density) Table 1 Scaling ratio for various technology nodes since and critical area. Contributors to defectivity are usually the mid 1980’s categorized as systematic (or gross) and random defects3. Many different yield models have been used in the industry. Simple models, such as the Poisson and the Murphy models using the die area as the critical area were prevalent in the early days. The Bose-Einstein model using die area but identifying a defectivity per critical layer has been used extensively in recent years8,9. Custom models exist at captive suppliers. More recently, sophisticated calculations of critical area based on information embedded in the design database are being

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Such technology scaling was achieved typically in the following manner: a. Drive new photo lithography equipment and processes that allowed printing and patterning of dimensions 30% smaller than in the previous generation. b. Make improvements to other parts of the process, e.g., gate oxidation, ion implantation, diffusion, etching, interconnect metallurgy etc. c. Engineer and optimize the transistor device structure and various aspects of the process to meet performance and cost goals, and be manu- Figure 4 (a) “Linear Shrink” from technology T1 to T2 and facturable and reliable. (b) “Re-design” d. Execute a “Linear Shrink” of an existing product reducing the die size by a scaling factor such as 0.7. Due to various intricacies of the process, the design rules and device characteristics at shrinking geometries, such scaling became increasingly difficult. In the mid-1980’s such an approach, which was referred to by some people as a “dumb shrink” became known as an Table 2 (a) Summary of scale factors for a “Linear Shrink” “intelligent laborious shrink” at some companies. e. A new set of design rules - both physical and The “Re-Design” approach is illustrated via Figure electrical - were usually used to design new 4(b) which depicts increased packing density products that took full advantage of the new achieved by taking advantage of more aggressive technology capability. While the shrink approach technology features and design rules and a “Clever- was able to get an initial product out in the new ness Factor”, F. The number of transistors packed in technology node, the “Re-Design” approach was the same size die increases by a factor F2k-2. Further necessary to maximize performance and mini- increases in packing density resulted from the use of mize cost of products in the new node. larger die sizes. Manufacturing enhancements of the f. In addition, the new technology usually had some process, the equipment and the clean room environ- new features aimed at increasing the packing effi- ment resulted in lower defect densities. This allowed ciency, design productivity and device perform- the fabrication of larger dice with acceptable yields in ance. Some examples are: increasing the number the new technology node in spite of the tighter of metal interconnect layers, self-aligned polysili- geometries. The increase in the maximum allowed die con gate structure, oxide and trench isolation, size is represented by the factor S. For simplicity, we standard cells, EDA tools and re-usable IP blocks. assume a square die and “die size” represents one lin- We will now discuss migration of designs from one ear edge of the die. Table 2(b) summarizes the scale node to the next using either the “Linear Shrink” or factors and typical values. These typical values show the “Re-Design” approach. To illustrate the “Linear a 29% annual reduction in CPF, a 4x increase in func- Shrink”, consider Figure 4(a), which depicts a square tions over a 3 year period, which is consistent with die with dimension y and having N transistors, in Moore’s Law1, 2 and the ITRS 20053. technology node T1. A simple shrink of the die into technology node T2 would reduce the die size by the scale factor k, where 0

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processors with increasing transistors per chip6. For a. For a 10mm die in 0.8um technology processed example, in 1989 the 8086 and 80286 microprocessors on 150mm and 200mm wafers, W=1.35, g=1.95. fit into an area that was a fraction of the area in pre- Therefore, die cost on 200mm wafers = 69% of vious technology generations. Then the 80486 was die cost on 150mm wafers. introduced in the new node with a larger die size and b. For a 10mm die in 130nm technology processed 4x the number of transistors of the previous proces- on 200mm and 300mm wafers, W=1.75, g=2.45. sor in the previous node. Therefore, die cost on 300mm wafers = 71% of die cost on 200mm wafers.

Figure 5 Technology scaling methodology reported by Intel Figure 6 Silicon wafer diameter increase over time

5. Die Cost Reduction by Increasing Wafer Size The industry has successfully increased wafer size7 from 50mm (2”) to 300mm (12”) as shown in Figure 6. The wafer diameter steps result in either a 1.33x or a 1.5x diameter ratio versus the previous size. An increased number of gross die per wafer results from the use of larger diameter wafers, as shown in Figure 7. The available silicon area is either 1.78x or 2.25x for the two different diameter ratios. The actual ratio of GDPW is generally higher and is a function of the die size, as shown in Figure 8. This is due to Figure 7 Increased gross die from a wafer diameter improved optimization of die-stepping algorithms to increase in the same technology maximize the number of full die. Larger diameter wafers also allow a reduction of the number of partial die around the perimeter of the wafer; this effect is more dominant for larger die sizes. Manufacturing on larger diameter wafers offers an improved economy of scale. The use of larger diameter wafers does increase wafer cost. However, we will show that there is a reduction in the die cost. Early on in the introduction of a new wafer size, a 70% increase in wafer cost is reasonable4. In mature production the cost to process a larger diameter wafer could increase 30%. Figure 8 GDPW increase as a function of die size for two different wafer size transitions Relative Die Cost on larger diameter wafers = W/g, 6. Optimizing the Die Size and Packing where W is the relative wafer cost for the larger wafer Density per Chip and g is the relative GDPW Selecting the optimum packing density and the die size becomes a challenge in this dynamic industry. As mentioned earlier, the range of values for W are We have developed models to predict the optimum 1.3-1.7 and for g are 1.8-2.5. Therefore, the range of die size and functions per chip. In Figures 9 and 10 relative die cost is 0.5-0.9, a 10-50% die cost reduction we show examples of the cost/gate for 90nm and when using larger diameter wafers. 180nm technologies as a function of die size and mil- A couple of examples for a mature and a relatively lions of gates per chip. The curves have a U-shape. If new technology are shown here: the die size is too small the cost is dominated by the

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overhead of the input/output structures, the scribe technical challenges at the 32nm node will lane, etc. If the die size gets too big, the cost per gate require ever increasing capital and manpower increases due to the increased complexity. For sim- investments. plicity, gate count is assumed here to be an equiva- b. Manufacturing entities have worked diligently to lent 2-input NAND gate count. Each equivalent gate accelerate the manufacturing and defectivity uses four transistors. The optimum gate density and learning curves. cost per gate can be converted to transistor density c. Creative co-design of process and design consid- and cost per transistor. The actual transistor count per erations has been called for by many authors10 chip increases rapidly as larger amounts of memory is and are being implemented to manage chal- included on the die. For reference, one of Intel’s Pen- lenges such as increased leakage and standby tium processors is reported with 55M transistors (14M power. equivalent gates) in a 90nm technology4. Referring to d. New product introductions on the 65nm tech- Figure 10, this data point will be considered reason- nology node have been made at leading edge ably well optimized in our analysis, since it is located users in the 2005 time frame; the cross-over near the minimum, just at the cusp of the steep slope point varies but is expected to be in 2007. Lead and marked by the arrow. The shape of the curve is products on 45nm will likely be announced in affected by parameters such as wafer cost, defect den- 2007 with a cross-over in 2009. These timetables sity, physical and electrical design rules, design tools’ indicate a less than 3 year cycle for the intro- packing efficiency. duction of new technology nodes. e. As in the past, technical solutions for the next technology (32nm), e.g. the use of double-exposure lithography, will add significantly to capital, process development and therefore wafer cost. The author is confident that the industry will find a new manufacturing and design optimization point that will allow introduction of new prod- cents/KGates ucts cost-effectively at this node. f. The increasing cost of wafers, masks and design require users to very carefully assess the selection of the proper technology for their products. The Figure 9 Cost per gate as a function of die size for 90nm trend is towards the use of leading edge technol- and 180nm technologies ogy nodes only for products with very high vol- umes, a compelling technical argument and a clear value proposition.

8. Summary This paper has provided a simplified view of the business aspects of scaling and technology migra- tions that have been key to sustaining a phenomenal cents/KGates reduction in CPF for integrated circuits. Although trends such as the increasing cost of wafer fabs, masks and the increasing cost of complex designs indicate a possible slow down of the implementation Figure 10 Cost per gate as a function of packing density of new technologies, the industry marches onward. for 90nm and 180nm technologies The industry has demonstrated resilience in finding solutions to challenges. New technologies are still 7. Current Trends being introduced at a feverish pace allowing This paper has focused on providing a historical per- increased packing density, reduced CPF and spective of business aspects of scaling. While a improvements in performance. detailed discussion of the current status of technical and business challenges is beyond the scope of this 9. Acknowledgements paper, we will provide some highlights of current The author wishes to thank Behrooz Abdi, Bill Bider- trends in this section. mann, Mung Chen, James Clifford, Brian Henderson, a. The cost of wafer fabrication facilities and equip- Professor Dave Hodges, Merrill Hunt, Matt Nowak ment, masks and chip design have all escalated and Ian Young for reviewing the manuscript and significantly over the years. Finding solutions to offering their valuable suggestions.

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10. References About the Author 1. G.E. Moore, “Progress in Digital Electronics”, Rakesh Kumar is President of TCX, 1975 IEDM, pp11-13. a consulting services company. He 2. G.E.Moore, “No Exponential is Forever; but “For- is also CEO of ei2, a fabless product ever” can be delayed”, ISSCC 2003, Paper 1.1. integration company. Previously he 3. International Technology Roadmap for Semicon- was VP & GM of the worldwide Sil- ductors 2005, http://public.itrs.net icon Technology business unit at 4. IC Knowledge, www.icknowledge.com Cadence Design Systems and Tality. 5. W.Haensch, E.Nowak, R.H.Dennard, et. al., “Sili- During his 32 years of industry con CMOS Devices beyond scaling”, IBM J. Res. experience Rakesh has also been at Unisys and and Dev., Vol. 50, April/May 2006. Motorola where he held various technical and man- 6. P. Gelsinger, P. Gargini, G. Parker, A. Yu, “2001: agement positions with increasing responsibility. He A Microprocessor Odyssey”, published in “Tech- has numerous publications and patents to his credit. nology 2001”, MIT Press, pp. 95-113, July 1992. Dr. Kumar is on the AdCom of the IEEE Solid State 7. P. Gelsinger, “Moore’s Law – The Genius Lives Circuits Society and serves as its Treasurer. He has On”, IEEE SSCS Newsletter, September 2006. chaired and served on the Steering committee of the 8. R.C.Leachman, “Yield Modeling”, http://www.ieor. IEEE Custom IC Conference for fourteen years. berkeley.edu/~ieor130/yield_models.pdf Rakesh received his Ph.D. and M.S. in Electrical 9. M.Sydow, “Compare Logic-Array To ASIC-Chip Engineering from the University of Rochester in 1974 Cost per Good Die”, Chip Design Magazine, Feb- and 1971 respectively. He received his B. Tech. in ruary/March 2006. Electrical Engineering from the Indian Institute of 10. T.C. Chen, “Where CMOS is Going: Trendy Hype Technology, New Delhi in 1969. [email protected] vs. Real Tecdhnology”, ISSCC 2006, Paper 1.1. 858.748.4624 A Perspective on the Theory of MOSFET Scaling and its Impact Tak H. Ning, IBM Thomas J. Watson Research Center, Yorktown Heights, NY, [email protected]

t was certainly the best of times to work on silicon inte- of negligible standby power dissipation [3]. So, when grated-circuit technology when I joined IBM Research the theory of MOSFET scaling [1] was published, the Iin 1973. My first assignment was to study the so-called prospect of MOSFET circuits with very low standby hot-electron effects in MOSFET’s. At the time and for power dissipation, that are both simple to make and many years that followed, hot-electron effects severely scaleable, seemed quite realizable. The theory pre- limited the progress of MOSFET technology, particularly scribed some simple rules to follow in scaling and CMOS technology. The reasons for this will be explained described the expected resultant circuit benefits, as list- later. In the subsequent three decades, I have had the ed in Table I. To first order, the expected drain current opportunity to participate in the evolution of silicon inte- equation for the scaled MOSFET is given by grated-circuit technology and witness the tremendously rapid rise and fall of a couple of the platform technolo- (1) gies. One of the most significant milestone events along

the way was the establishment of a theory for scaling where Id (reference) is the drain current of the refer-

down the physical dimensions of MOSFET’s, published in ence MOSFET and Id (scaled) is the drain current of 1974 [1]. In this paper, I provide a brief personal perspec- the scaled MOSFET. tive on the significant role this theory played in the evolution of silicon integrated-circuit technology. TABLE I: Rules and results for circuit performance in scal- From the very beginning, the basic idea of integrating MOSFET by a factor κ [1] ed-circuit technology has been to employ advanced lithographic and process techniques to make ever smaller devices and to increase the chip-level integration. The technology to produce stable n-channel MOSFET’s was developed in IBM in the 1960’s [2]. Using n-channel instead of p-channel, the performance of MOSFET’s was improved by about a factor of two. In 1963, CMOS circuits were reported with the promise

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However, a typical MOSFET in production in the The opportunity for scaled CMOS to break into early 1970’s had a gate oxide of about 100 nm in high-end applications came when the industry thickness, a channel length of about 5 μm, and a worked together to established voltage standards power supply voltage of 5 V or larger. As explained below 5 volt. Once it was recognized that CMOS at in a paragraph below, the performance of these high- less than 5 V could be accepted by the market, engi- voltage MOSFET circuits was simply much too inferi- neers wanted to reduce CMOS voltage as fast as pos- or compared to the performance of silicon bipolar cir- sible. As an illustration of this “lower is better” mind cuits. Bipolar was the high-performance technology, set at the time regarding CMOS voltage, Figure 1 is a the backbone of computers and high-performance plot of three CMOS voltage roadmaps proposed in the electronics, while MOSFET was the low-cost technol- early and mid 1990’s. At the first semiconductor tech- ogy for applications where performance was not nology roadmap workshop in 1992 [6], there was a required. consensus that CMOS power supply voltage would The benefit of applying the scaling theory to MOS- not be below 2 V until 2004. In 1995, it was proposed FET technology, especially to CMOS technology, that leading CMOS should have a power supply volt- seemed obvious and exciting. If we just follow the age of 1.8 V in 1999. By the time the 1997 roadmap rules and scale the CMOS devices by a factor of ten, [7] was prepared, it was proposed that the voltage in the resulting circuits will be ten times faster. For more 1999 should be 1.5 V instead. For several years now, than two decades following the publication of the advanced CMOS microprocessor chips use a power MOSFET scaling theory, CMOS engineers focused supply voltage of 1 to 1.2 V. much of their efforts in scaling down the physical size of CMOS transistors. However, instead of scaling down the power supply voltage, they left it at 5 volts, which was the standard for practically all integrated circuits. There was simply little or no market for integrated-circuit chips using non-standard voltages. Such constant-voltage scaling of MOSFET quickly ran into two major difficulties, namely the power density of a CMOS circuit in switching increased very rapidly by a factor of κ2 to κ3, and the fast increasing electric field caused hot-electron and oxide reliability problems. Power density was not much of a problem because the integration level was still relatively low so that the Fig. 1. Proposed power supply voltage trends for CMOS. total chip power was readily manageable. However, (After references [6] and [7]) device engineers had to devote much effort to devel- Reducing CMOS voltage makes the fabrication op practical techniques, such as LDD (Lightly Doped process for scaled CMOS less complex and hence Drain) [4], in order to bring the reliability issues under lowers the cost. For one thing, process steps used to control. Controlling hot-electron effects added signifi- implement LDD can be omitted. With the introduction cant cost to the CMOS chips. of scaleable technology elements such as shallow- Scaling at constant voltage severely limited the per- trench isolation and dual-poly gate (i.e., p+-polysili- formance potential of CMOS as well, particularly for con gate for p-FET and n+-polysilicon gate for n-FET) driving long wires and driving signals off chip. To first to the fabrication of reduced-voltage CMOS circuits, order, the performance for driving a capacitance load C as illustrated in Fig. 2, CMOS technology became is CV/I, where V is the voltage swing and I is the cur- readily scaleable [8]. The same device schematic in rent delivered by the transistor. For bipolar circuits, V is Fig. 2 was used to represent several generations of typically about 200-400 mV for driving on chip, and CMOS technology, making the migration of devices about 800 mV for driving off chip. Thus, at 5 V, the volt- and circuits from one generation to the next relative- age swing of CMOS circuits was much too large for ly simple to implement, and exhibited more pre- high-performance applications. Besides, in the late dictable results. For the decade that followed, there 1970’s, bipolar engineers also developed a theory for was accelerated progress throughout the semiconduc- scaling bipolar circuits [5] which guided the rapid tor industry scaling such a CMOS device structure to development of faster and lower-power bipolar circuits. ever smaller dimensions, as evidenced by the acceler- For more than twenty years after the MOSFET theory ated rate at which CMOS power supply voltage was was published, CMOS remained a low-cost technology reduced. limited to applications where performance was not an With CMOS channel lengths scaled to around 100 important factor. When performance was needed, nm and voltages reduced to around 1 volt, the per- scaled advanced bipolar technology was used. formance of digital CMOS became comparable to that

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early 2000’s. These limits are the high tunneling current through the thin gate insulator and the high device off current. That we reached these scaling limits so soon should come as no surprise. In the case of gate insulator thickness, it was shown that scaling CMOS to the regime where gate tunneling current is appreciable has little impact on the device characteristics [10]. Today, leading- edge CMOS microprocessor chips employ gate oxide layers as thin as 1 nm, which is pretty much the limit set by acceptable gate tunneling current. The limit due to high device off current has been looming there since the very beginning, as shown in Eq. (1). In Eq. (1), the factor [Vg − Vt − Vd /2]/κ scales only if the threshold voltage

Fig. 2. Schematic of a CMOS device structure that was Vt is scaled. If Vt is not scaled, this factor is smaller than scaleable to deep sub-micron dimensions. (After Davari, [8]) expected from scaling and the resultant device speed is less than expected from scaling. As the CMOS voltage of digital bipolar. The era of bipolar for high-per- was scaled below about 2 V, device designers had to

formance digital circuits came to an end when IBM reduce Vt in order to achieve the intended device per-

decided to replace bipolar by CMOS as the technolo- formance targets. Reducing Vt has the effect of increasing gy for mainframe computers. At first, the CMOS main- the device off current, as illustrated schematically in Fig.

frame processors was not really as fast as the bipolar 4. Reducing Vt repeatedly for several generations has lead versions, but the highly scaleable properties of CMOS to a dramatic increase of CMOS device off current. allowed CMOS processors to catch up in just a few Today, CMOS circuits no longer have negligible standby years, as shown in Fig. 3 [9]. Since then, CMOS has power dissipation. Instead, the performance of leading- become unquestionably the technology for all digital edge CMOS logic chips is limited by a combination of applications. device off current and gate tunneling current.

Fig. 3. IBM S/390 mainframe uniprocessor performance. Fig. 4. Schematic showing the increase of device off current

(After Rao et al., [9]) when Vt is reduced, where Vt2 < Vt1. Every technology has its limits, and CMOS is no Without the ability to reduce gate insulator thickness exception. The fact that the CMOS device structure and device threshold voltage any further, CMOS device depicted in Fig. 2 is highly scaleable was both good designers find it difficult to increase device speed by the news and bad news. The good news was that it usual means of scaling device channel length. Today, became relatively straight forward to establish an device engineers focus primarily on technology innova- industry-wide technology roadmap, and every leading tions for continued device performance improvement semiconductor company wanted and was able to beat from one generation to the next. The most notable inno- the roadmap targets. Again, this is evidenced by the vations that have been successfully developed and put increasingly aggressive rate of CMOS power supply into volume manufacturing to date include using silicon- voltage reduction illustrated in Fig. 1. System devel- on-insulator (SOI) as the wafer substrate [11], using opers and consumers certainly benefited tremendous- embedded SiGe in the source/drain region of p-channel ly from the faster-than-projected rate of CMOS scaling. FET’s to improve hole mobility [12], and using highly- The bad news was that the industry also reached the stressed dielectric films on top of n-channel FET’s to limits of CMOS scaling at rate faster than anticipated. improve electron mobility [13]. Each of these innovations Two of the limits of CMOS scaling were reached in the offers incremental but appreciable improvements to the

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speed and/or power dissipation of CMOS circuits. Cir- Industry Association. cuit designers can always tradeoff the speed improve- [8] B. Davari, “CMOS technology scaling, 0.1 μm and ment for lower power dissipation. Judging from the pre- beyond,” IEDM Tech. Dig., pp. 555-558 (1996). sentations at device conferences, it is reasonable to [9] G.S. Rao, T.A. Gregg, C.A. Price, C.L. Rao, S.J. Repka, expect a steady stream of additional innovations for “IBM S/390 parallel enterprise servers G3 and G4,” enhancing CMOS performance to become ready for IBM J. Res. Develop., Vol. 41, pp. 397-403 (1997). manufacturing in the next decade. [10] H.S. Momose, M. Ono, T. Yoshitomi, T. Ohguro, S. Nowadays, the concern is not the lack of innovative Nakamura, M. Saito, and H. Iwai, “Tunneling gate ideas for improving CMOS performance, but the time oxide approach to ultra-high current drive in small- and cost needed to bring a specific innovation from its geometry MOSFET’s,” IEDM Tech. Dig., pp. 593-596 concept stage to volume manufacturing. Most major (1994). innovations take 10 ±5 years from concept to manufac- [11] G. G. Shahidi, A. Ajmera, F. Assaderaghi, R. J. Bolam, turing, which is long compared to the 2 to 3 years to E. Leobandung, W. Rausch, D. Sankus, D. Schepis, scale CMOS from one generation to the next (the linear L. F. Wagner, K. Wu, and B. Davari, “Partially-deplet- dimension is reduced by a factor of 0.7 and the circuit ed SOI technology for digital logic,” IEEE ISSCC density is improved by a factor of 2 each generation). Technical Digest, pp. 426-427 (1999). Going forward, it is important that circuit and system [12] S. Thompson, N. Anand, M. Armstrong, C. Auth, B. designers recognize this paradigm shift in CMOS devel- Arcot, M. Alavi, P. Bai, J. Bielefeld, R. Bigwood, J. opment and plan their product strategies accordingly. Brandenburg, M. Buehler, S. Cea, V. Chikarmane, C. Thanks to the insights provided by the simple theory Choi, R. Frankovic, T. Ghani, G. Glass, W. Han, T. of MOSFET scaling, we have been able to make unprece- Hoffmann, M. Hussein, P. Jacob, A. Jain, C. Jan, S. dented progress in advancing CMOS technology over a Joshi, C. Kenyon, J. Klaus, S. Klopcic, J. Luce, Z. Ma, period of about thirty years. In the process, we have run B. Mcintyre, K. Mistry, A. Murthy, P. Nguyen, H. Pear- the course of CMOS development guided by the theory son, T. Sandford, R. Schweinfurth, R. Shaheed, S. of scaling. We have left the period when leadership in Sivakumar, M. Taylor, B. Tufts, C. Wallace, P. Wang, CMOS technology was judged by being the first to scale C. Weber, and M. Bohr, “A 90 nm logic technology CMOS to the next dimensional node and entered a peri- featuring 50 nm strained silicon channel transistors, 7 od when leadership is judged more by being able to layers of Cu interconnects, low-k ILD, and 1 μm2 enhance chip-level performance through innovation. SRAM cell,” IEDM Tech. Dig., pp. 61-64 (2002). [13] Most dielectric films are of high stress as deposited. References Until recently, device engineers worked hard to min- [1] R.H. Dennard, F.H. Gaensslen, H.-N. Yu, V.L. Ride- imize the stress in the deposited films to avoid pos- out, E. Bassous, and A.R. LeBlanc, “Design of ion- sible deleterious effects such as wafer bowing and implanted MOSFET’s with very small physical film cracking and/or peeling. To day, device engi- dimensions,” IEEE J. Solid-State Circuits, Vol. SC-9, neers work hard to increase the stress in a control- pp. 256- 268 (1974). lable manner to increase n-FET drive current. [2] An account of the challenges and major milestones in the development of n-channel MOSFET can be About the Author found in the article by E.W. Pugh, D.L. Critchlow, Tak H. Ning received his Ph. D. degree R.A. Henle, and L.A. Russell, “Solid state memory in physics from the University of Illi- development in IBM,” IBM J. Res. Develop., Vol. 25, nois at Urbana-Champaign in 1971. He pp. 585-602 (1981). joined IBM Thomas J. Watson [3] F.M. Wanlass and C.T. Sah, “Nanowatt logic using Research Center in 1973. His early field-effect metal-oxide semiconductor triodes,” IEEE technical contributions were in under- ISSCC Technical Digest, pp. 32-33 (1963). standing hot-electron effects and in [4] S. Ogura, P.J. Tsang, W.W. Walker, D.L. Critchlow, advanced bipolar technology. From and J.F. Shepard, “Design and characteristics of the 1982 to 1991, he managed the silicon devices and tech- lightly doped drain-source (LDD) insulated gate nology department in IBM Research, contributing to and field-effect transistor,” IEEE Trans. Electron Devices, leading the research effort on CMOS, bipolar, DRAM, Vol. ED-27, pp. 1359-1367 (1980). EEPROM and SOI. He was appointed an IBM Fellow in [5] P.M. Solomon and D.D. Tang, “Bipolar circuit scal- 1991. In recent years, he has focused his technical activ- ing,” IEEE ISSCC Technical Digest, pp. 86-87 (1979). ities on understanding the limits of CMOS as well as the [6] Semiconductor Industry Association, 1992 Semicon- opportunities beyond CMOS. He received the 1989 IEEE ductor Technology Workshop, Working Group Electron Devices Society J.J. Ebers Award and the 1991 Report, published in 1993. IEEE Jack A. Morton Award. He is a member of the [7] The 1994 and 1997 National Technology Roadmaps National Academy of Engineering, and a fellow of the for Semiconductors, published by Semiconductor IEEE and of the American Physical Society.

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TECHNICAL ARTICLES Impact Of Scaling and the Scaling Development Environment Yoshio Nishi, Department of Electrical Engineering Center for Integrated Systems, Stanford University, [email protected]

he largest question in the early to mid 70’s was processes and a variety of thermal processes. This how far silicon could go in competition against almost implied that we needed to look around for Tnewly emerging materials and devices such as 360 degree instead of any particular focus. Also, it magnetic bubble memory, Gunn effect functional was the time when layout design was viewed as devices, integrated injection logic, GaAs MESFET inte- such a serious bottle neck that almost 90% of the grated circuits, and Josephson junction logic. world population might need to become layout The typical roadmap of major semiconductor designers and technicians by the end of the 80’s. manufacturing companies in those days was such Fortunately, many IEEE technical conferences, such that (1)Silicon based integrated circuits would lose as IEDM and ISSCC were quite interesting in terms position by the mid 80’s except for silicon on sap- of a large variety of research results presented, but phire, SOS, based ones, (2)GaAs integrated circuits when it came to the future of silicon integrated cir- would become the dominant design for high speed cuits, general perception was to seriously stagnant at and /or low power applications, (3) Optical lithog- around 1um geometry. raphy would surrender its position against either Dr. Robert Dennard’s paper in 1974(1) appeared in electron beam lithography or soft X-ray lithogra- the IEEE Journal of Solid State-Circuits. As the first phy, (4) Geometry shrink, however, may proceed proposal for the scaling principle, it looked, at first despite challenges around. In other words, no one glance, rather simple and did not attract much atten- was even close to predicting what we are seeing tion, at least I remember from a little corner of Toshi- today. In fact, many central research organizations ba Research and Development Center where I was in in industry decided that silicon would not be a right charge of SOS microprocessor technology and also subject any more for advanced research, and either involved in Japan’s VLSI project looking into short shut down silicon research activities or transferred channel MOSFET technology research. However, it the division to their operation divisions. did not last long before more people started under- In the middle of the 70’s, Japan launched a large standing what it possibly would imply to the world national project, called the “VLSI project” which was of MOS integrated circuits. However, it needed to instigated by the announcements made by Bell Lab- wait for CMOS taking the “dominant” design position oratories for electron beam direct writing lithogra- in the mainstream of integrated circuits before the phy, and by IBM demonstrating 8kbit dynamic ran- scaling theory became the physics based guiding dom access memory at 1um minimum geometry, principle for Moore’s Law to continue. Without scal- both of which were supposed to provide solutions ing theory, I doubt that Moore’s Law could have sur- for future computing systems in the mid 80’s and vived for more than three decades. It was the first beyond. The project consisted of Fujitsu, Hitachi, attempt to couple geometry shrink with other impor- Mitsubishi, NEC and Toshiba, and had a centralized tant factors such as power-delay products, on-chip research center for basic research to which all mem- interconnect performance as well as integration den- ber companies sent researchers, and also two branch sity. The magic number alpha of “1.4” or 0.7x shrink laboratories for Fujitsu-Hitachi-Mitsubishi group and over all device parameters, as shown below became NEC-Toshiba group focused on more development a general guideline from one technology node to the oriented work. Two government laboratories, Elec- next technology node since then. trotechnical Laboratory and NTT Laboratories were also involved. dimensions tox, L, W 1/α Moore’s Law was already becoming popular, but doping α when it came to any methodical approach to make voltage 1/α it happen rather than a religious belief, there was not integration density α2 much idea which was viewed credible enough. delay 1/α2 Japan’s VLSI project had both logic and memory as power dissipation/Tr 1/α2 the targeted areas with MOSFETs, bipolar such as ECL/CML, and compound semiconductor devices. It is indeed difficult to see any other such exam- The tool side was even broader, covering from opti- ple in which one set of rather simple principles can cal, electron beam and X-ray lithography, plasma survive for such a long time. I would, however, say

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that this has survived because of its simplicity and About the Author transparency. There have been enormous impacts Yoshio Nishi is a Professor in the coming from the scaling principle, not only in the Department of Electrical Engineering way we design devices and develop technology to (research) and in the Department of meet requirements, but also on the semiconductor Material Science and Engineering at device manufacturing industry as well as manufac- Stanford University He also serves as turing equipment business by providing clear and Director of Stanford Nanofabrication easily understandable directions with investment Facility of National Nanotechnology timing. The scaling principle and Moore’s Law Infrastructure Network of US, and have been inseparable in terms of providing a driv- Director of Research of Center for Integrated Systems. ing force to technology research and development Professor Nishi Received a BS in material science and and justifying huge investment for more advanced PhD in electronics engineering from Waseda University infrastructures for manufacturing. It was because and the University of Tokyo, respectively. scaling continuously provided 2x density of inte- He joined Toshiba R&D in the areas of research for semi- gration at reduced cost per gate or bit with better conductor device physics and interfaces mostly in silicon, performances to integrated circuits chips designed resulting in discovery of ESR PB Center at SiO2-Si interface, and manufactured with more advanced technology the first 256bitMNOS non-volatile RAM, SOS 16bit micro- in the past three decades. It should not be forgot- processor and the world first 1Mb CMOS DRAM. He was ten that scalable design library has become one of also involved in MITI VLSI project for ultra short channel the prerequisites for the design community, which MOS device technology research from 1976-1981. cut down design cost increase coupled with enor- He moved to Hewlett-Packard in 1986 as the Director mous progress made in computer aided design of Silicon Process Lab, followed by establishing ULSI from logic design down to layout design capabili- Research Lab as the Founding Director. ty. In 1995 he joined Texas Instruments, Inc as Senior VP Today we are still thinking with the scaling prin- and Director of Research and Development for semicon- ciple even though the scaling factor could be quan- ductor group, and implemented new R&D model for sil- tized due to actual size approaching the integer icon technology development, followed by establishing times an atomic size, and performance would be in the Kilby Center. the same way as somewhat quantized by nature. In May, 2002, he became a faculty member of Stanford This would force us to rethink scaling not just for University. His research interests cover nanoelectronic the geometry scaling, but also consider a variety of devices and materials including metal gate/high k MOS, new materials to keep the pace of improvement device layer transfer for 3D integration, nanowire devices both in performance and cost. As we see the era for and resistance change non-volatile memory materials and “nanoelectronics” either evolutionary and/or revolu- devices. He published more than 200 papers including tionary challenges, this is a great moment at which conference proceedings, and co-authored/edited 9 books. we all should appreciate what Dr. Dennard has He holds more than 70 patents in the US and Japan. given to all of us. During the period of 1995-2002 he served SRC and International Sematech as Board member, NNI Panel, References MARCO Governing Council. etc. Currently he is an asso- [1] R.H. Dennard, F.H. Gaensslen, H.N. Yu, V.L. ciate member of the Science Council of Japan. Rideout, E.Bassous and A. R. Le Blanc, “Design Dr. Nishi is a Fellow of IEEE, a member of Japan Soci- of Ion-Impanted MOSFET’s with Very Small ety of Applied Physics and the Electrochemical Society. Physical Dimensions,” IEEE J. Solid-State Circuits, Recent awards include the 1995 IEEE Jack Morton SC-9, p. 256 (1974). Award, and the 2002 IEEE Robert Noyce Medal.

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TECHNICAL ARTICLES It’s All About Scale Hans Stork, Texas Instruments, Inc., [email protected]

Abstract limiting increases in the final cost per wafer to less The electronics industry often thinks of scaling in only than 30%. The compound effect of a new node every one dimension: making things smaller. But it really two (early on, three) years has brought mainframe scales in two directions, both smaller and larger, and capability down to the package of a cell phone. the semiconductor industry has employed both, allow- We’ve moved from megawatts to milliwatts, from ing roughly 40 years of exponential progress in the MHz to GHz, from kilobits to gigabits, and so on. cost reduction of electronic functions. The future of Most importantly, all while moving from millions of the semiconductor industry holds daunting challenges, dollars to just a few dollars . including some related to scaling things larger, but a This progress wasn’t obvious at the outset. If we historical view shows this has always been true. had known then what is possible now, we would have done it faster. Every time a new node is con- Introduction templated, lithography capability is two generations The topic of scaling usually invokes pictures of ever away from physical or practical (i.e. economic) lim- smaller features, transistors and wires, packing ever its. Today, the patterning process calls for 193nm more functions onto densely packed circuit boards. immersion lithography with various resolution On the other hand, fabs, tools, teams and complexi- enhancements. Combining wavelength reduction, ty have been increasing in size at nearly the same lens improvement, mask sophistication and resist exponential pace. It is the combined effect of these enhancement now allows printing of features with a two trends, smaller features working to solve larger minimum pitch of lines and spaces near 125nm. problems, that has allowed rooms full of electronic Future improvements in numerical aperture (NA) to equipment to shrink into slivers of silicon, at a frac- 1.35 are expected to bring this down to sub-80nm tion of the cost, operating at a fraction of the power, for regular arrays. Printing even smaller features and available to anyone, anywhere in the world. with higher transistor density may require new However, just as the amount of silicon required to capability such as Extreme UV, which requires all perform a function has gotten smaller, the number of reflective optics and a vacuum toolset. Serious chal- users and their demands has scaled up. A modern lenges also need to be overcome with regard to data center is capable of serving millions instead of source power and mask capability. The perennial few, and of solving bigger problems with ever alternative, direct-write e-beam, may have applica- greater precision. tion in very low volume product or as mask writer, Looking back at the progress of integrated circuit using a massively parallel beam to overcome the scaling, it is easy to forget that it was never obvious charge-throughput limitations of a single beam. In how to progress beyond the next two generations. all cases, the mask plays a critical role, and has The few that tried to extrapolate progress beyond this become the key concern for designers. window, or proclaimed that the end of scaling was Masks are no longer “black and white” but their near, were mostly proven wrong. With that historical features manipulate a complex two-dimensional con- lesson in mind, the following sections look at the trast image through focus and exposure windows. recent past and near term future of feature scaling, This specialty of Resolution Enhancement Technology resource scaling, and application scaling. (RET) has resulted in tricks like Sub Resolution Assist Features (SRAFs) for vias, model-based Optical Prox- Scaling Transistors and Interconnect imity Correction (OPC), and will likely embrace Insights into the scalability of the physics of field model-based placement for SRAFs and dual-pattern, effect devices unleashed a steady and rapid reduc- dual-etch for better poly and contacts definition. As tion in feature sizes. Under conditions of constant one might imagine, these techniques have greatly electric fields, smaller devices switch faster at lower contributed to the cost of masks, and hence product power. Density increases quadratic, power dissipa- design. Scaling down has meant scaling up. tion reduces cubic, and speed increases linearly. Ide- While the horizontal dimensions have become ally then, scaling allows more things to happen smaller than the gate dielectric of the past, the tech- faster at the same energy cost, and is economically nology has reached the practical limits of oxide attractive if the manufacturing cost per square area thickness reduction. While dielectric improvements grows only modestly. Specifically, in the past decade using Nitrogen and/or Hafnium may extend the or so, CMOS has improved density at each node by effective thickness, it is likely limited to at most a 2x, increased performance more than 20%, while factor of two. Additional benefits may be gained

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from metal gate electrodes by eliminating the deple- ber of mask layers has also increased rapidly. The tion layer on the top side of the dielectric. Any size and cost of fabs has thus grown exponentially, mobility degradation because of additional scatter- each supplying an ever larger fraction of the market, ing will be overcome by the significant mobility and each generation requiring a larger investment enhancements due to strain. In fact, the successful and higher market risk. application of strain is a superb example of unan- Resource demands have also rapidly grown on the ticipated improvements that work precisely because product side. Thanks to the ability to yield hundreds of the new small scale of the devices. Many of the of millions of transistors on a single die, design teams effects below 100nm introduce problematic behav- for chips are now equivalent to those that were iors: tunneling contributes to leakage in thin required to build large computers. Product designs dielectrics and high field junction profiles; line edge need to comprehend everything from knowing the roughness in resists patterns results in excessive strengths and limitations of the process, to defining short channel effects; and grain–boundary and side- and building the software infrastructure that support wall scattering increase the resistivity of copper such sophisticated systems-on-a-chip. wires with very small cross-sections. Low resistance is critical to high efficiency use of the device prop- Scaling the Applications erties. Contact and via resistance are therefore Absolute interconnect performance has become a becoming a bigger concern going forward as their dominant speed limit and, consequently, variations in properties scale non-linearly in the wrong direction. line-width and thickness add increasingly to the And, as many now know, the capacitance of the design margin. While many effects are systematic, the interconnect is approaching its physical limits as complexity of interconnect prevents a brute force well. The low dielectric constant materials that computational solution. This has become typical of reduce the k-value from 4 for silicon dioxide, to the technical problems to be solved at the design and around 2.5 for heavily Carbon mixed compounds, application level. Conceptually, the problem of opti- are mechanically weak and can interfere with pack- mizing interconnects to minimize delay and power is aging robustness, as well as cause electrically lower governed by simple physics. However, the sheer size breakdown voltages. of a problem like this, or that of RET or for that mat- All these process and materials changes have ter, fab operations, is overwhelming. Not just for the allowed density scaling to continue at its historical design teams, but frequently for their compute pace of 2x every generation. The price has not only resources as well. And finally, the challenge is not been more complexity, but also the introduction of overcome by solving a steady state or exact condition. several design tradeoffs. Design innovations now Parameters are not perfectly controlled, and it is need to limit static and dynamic power dissipation, becomingly increasingly clear that comprehending tolerate escalating parameter variations, maximize variations is where the next breakthrough may be increasingly restricted layout options, and incorporate needed. Nature gives us examples of how it has fig- analog and RF functions at the low voltages compati- ured out that designing with imperfect and infinitely ble with extremely small dimensions. variable components can be successful. Although human communication may be effective while being Scaling the Resources imperfect, other communication or computation tasks Immersion lithography allows for effectively shorter cannot tolerate any practical errors. wavelength and a higher NA lens design to improve For example, encouraging progress by the EDA the lithographic patterning pitch. A manufacturable tool suppliers is trailing the needs for leading product implementation requires cost effective throughput, designs. Integrating analog and RF functions in defect density, and resist solution. The large increase advanced CMOS requires an architectural approach to in capital equipment cost consumes the largest frac- maximize the features of density and speed, rather tion of the process cost budget. As is the case for than the precision of analog components. every process tool, to maintain cost effectiveness, high throughput/automation is required to offset the Summary initial capital outlays. But now the high volume Over the past 40 years the world has benefited from capability of each tool requires the fabs to be ever exponential growth in the application of semiconduc- larger to avoid one-of-a-kind tool challenges. In tors. Thanks to scaling transistor dimensions into the addition, chips now may include over 10 layers of nanometer regime and scaling the manufacturing interconnect. While the process is repeatable, the capabilities to produce billions of individual chips, the interconnect fraction of a fab is easily half the fab industry has achieved economies of scale that allow size because of the multitude of tools. The explosion what was once mainframe capability to be affordable in process steps, represented typically by the num- to everyone in the world in something as small as a

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cell phone. With many fundamental physical scaling area. Starting in 1987 he led an exploratory devices limits still far away, this progress can and will contin- group which demonstrated record breaking SiGe ue if demand for the applications supports the HBTs. Hans was awarded two Outstanding Techni- increased investment necessary to get there. cal Achievement Awards from IBM. He has written or co-authored nearly 100 cited papers and holds eleven US patents. He was elected IEEE Fellow in About the Author 1994 for his contributions to SiGe devices and Johannes M.C. (Hans) Stork is Senior technology. Vice President and Chief Technolo- Hans has served on various conference and IEEE gy Officer of Texas Instruments committees, including IEDM, VLSI, and BCTM Incorporated. As Director of the Sil- between 1986 and 1996. Presently, Dr. Stork serves on icon Technology Development the Board of Directors of Sematech, and is chairman organization, Dr. Stork’s primary of the Semiconductor Research Corporation (SRC) responsibilities are the development Board of Directors. He has been a member of the SIA of advanced CMOS, packaging and Technology Strategy Committee since 1999. mixed signal process technologies. In 2000-2001, he participated as a technical advisor He joined Texas Instruments in September 2001, to Government efforts on high performance comput- after being the Director of the Internet Systems and ing benchmarks and the national security issues of Storage Lab at HP Laboratories, Hewlett-Packard from Internet computing, and has recently been elected a 1999 until 2001. He had joined Hewlett-Packard in member of the advisory committee for the Emerging 1994, holding the position of Director of the ULSI Technology Fund in the state of Texas. Research Lab between 1995 and 1999. Dr. Stork was born in Soest, The Netherlands, and Dr. Stork started his professional career in 1982 received the Ingenieur degree in electrical engineering at IBM's T.J. Watson Research Center as a research from Delft University of Technology, Delft, The Nether- staff member in the bipolar technology and circuits lands, and holds a PhD from Stanford University.

hese three reprints show the difference between conference and journal reporting in the 1970s. When the concept of scaling first saw the light of day at IEDM in 1972, only an abstract remained as an archive report. TBy 1973, the IEDM Digest provided a broader basic overview of Dennard’s report. Denard’s 1974 explana- tion of scaling turned out to be the most cited article in the 51 year history of the JSSC, close to 700 times, according to the last count in 2005 by the independent citation report firm, Thomson ISI (sscs.org/jssc/topcites.htm). The mission of Journal of Solid-State Circuits is to provide the full archival source for important technical milestones and fundamental explanations critical to the field.

Design of Micron MOS Switching Devices R. H. Dennard, F. H. Gaensslen, L. Kuhn, H. N. Yu, IBM Thomas J. Watson Research Center, Yorktown Heights, N. Y.

odern photolithographic technology offers the ricated without the usual deleterious effects associat- capability of fabricating MOSFET devices of ed with short channels. The measured characteristics Mmicron dimensions and less. It is by no means of these short-channel devices and the larger devices obvious that such small devices can be designed with from which they were scaled will be compared. suitable electrical characteristics for LSI switching appli- The scaling procedure helps to better understand cations. In this talk we will describe short-channel the limitations of miniaturization of MOS devices. Sig-

devices (Leff ~ l µ) designed by scaling down larger nificant problems are encountered when operating devices with desirable electrical characteristics. Later- voltages become comparable to the band gap which al and vertical dimensions, doping level, and operat- cannot be scaled within the silicon technology. The ing voltages and currents are scaled in a self-consis- subthreshold characteristic of the device then tent fashion. In this way small devices have been fab- becomes an important consideration.

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Ion Implanted MOSFET’s With Very Short Channel Lengths R. H. Dennard, F. H. Gaensslen, H. N. Yu, V. L. Rideout, E. Bassous , and A. LeBlanc IBM Thomas J. Watson Research Center, Yorktown Heights, N. Y.

t has been shown previously that MOSFET switching the surface potential in the channel region is indeed devices can be scaled down to have one micron spac- controlled by the gate. Merging of the depletion layers Iing between source and drain. In order to achieve in the lighter doped substrate is prevented by using shal- electrical characteristics suitable for dynamic memory and low implanted source and drain junctions of depth com- other digital applications, such miniaturized devices must parable to the p-type implanted region, and also by have reduced gate insulator thickness and junction depth, choice of a moderate substrate doping level. reduced operating voltages, and increased substrate doping (1). The previously described one micron device structure is shown in Fig.1(a). With uniform substrate doping, a 200°A gate insulator is required to achieve the desired control of the gate threshold voltage over the operating range of the source and drain voltages.

Figure 2(a) Vertical substrate doping profile, and (b) the resulting threshold versus source - substrate bias characteristic compared with alternate approaches. Experimental confirmation is shown by large dots. The vertical-doping profile of the implanted region beneath the gate is shown in Fig. 2(a). Intuitively, it was felt that a step function profile is preferable for the one micron implanted device, and such a profile has been used for design purposes. In practice a single energy implant through the gate oxide with thermal treatment used in the subsequent processing gives a reasonably good approximation to the step function. Fig. 2(b) shows the gate threshold voltage (relative to the source) required to turn on the device as a function of the source - substrate potential using the one-dimensional model described in another conference paper (2). The implantation profile was chosen to be deep enough to prevent depletion layer punch through, Figure 1: MOS device designs for micron source-drain and shallow enough to give the desired threshold voltage spacing. (a) Unimplanted design (b)Design with ion control with a 350°A gate insulator thickness. Throughout implantation. the operating bias range (Vs-sub > 1), the gate field for the The present paper addresses improvements in the threshold condition depletes the heavier doped implanted design of micron devices which can be obtained by region, and this depletion extends well into the lighter using ion implantation. The new n-channel design, doped substrate. This gives a threshold voltage relatively which is shown in Fig. 1(b), uses a lighter doped sub- independent of source-substrate bias compared to a uni- strate with a relatively heavy doped p-type region at the formly doped substrate with the same 350°A oxide thick- surface between the source and drain. This implanted p- ness. (See Fig. 2(b)). Compared to a non-implanted design type region gives the desired threshold magnitude, and with a 200°A gate insulator, the new design has the same also controls the extent of the source and drain deple- slope in the threshold versus source bias characteristic, but tion regions beneath the gate. With the gate turned off, the overall threshold level is higher, which is desirable to these depletion regions must be kept separated so that provide adequate design margins for circuit applications.

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The one-dimensional threshold model is adequate for implant was found to be somewhat less effective in devices with long source-drain separation, but in practice minimizing the threshold decrease for narrow source the short devices of interest suffer a decrease in threshold drain spacing. The sensitivity to the source and drain voltage due to penetration of the drain field into the chan- junction depth and to the background doping was also nel region normally controlled by the gate. These short investigated, and the results are shown in Table I. channel effects have been studied using a two-dimen- These results show that there is little room for deviation sional numerical model (3). The computed turn-on char- from the original design and justify the original choices. acteristic is shown in Fig. 3 for two values of source-drain spacing L in the range of one micron and for a relatively long (10 micron) device, all normalized to the same width-to-length ratio (W/L=1). A drain voltage of 4 volts is applied in all cases, which is the maximum considered for this design. The effect on the short devices is a shift of the characteristic along the gate voltage axis. This repre-

sents a lowering of the threshold voltage. (Vt corresponds to a drain current of about 10-7 amps above which the cur- 2 rent varies as (Vg-Vt) rather than exponentially with Vg. Otherwise the device turns off properly. Figure 4. Experimental threshold voltage as a function of source-drain spacing compared to computed values.

Table 1

In summary, ion implantation allows the fabrication Figure 3: Computed and experimental turn-on characteris- of very small MOSFET switching devices with consider- tics for different values of source-drain spacing, L. ably thicker gate insulators. Capacitance from the Experimental devices have been fabricated to test this source and drain to the substrate and to the gate is design with various source-drain separations from 0.5 to reduced by more than a factor of two compared to con- 10 microns. The p-type region was obtained with a 35 ventional structures. Conversely, for a given thickness, KeV B11 implantation through the 350 Å gate oxide into smaller devices can be achieved using ion implantation. 2 ohm-cm substrates. The narrow silicon gates were delineatead by contact printing from high-quality masks. Acknowledgements Self-aligned source and drain regions were formed with We wish to acknowledge the valuable contributions a 100 KeV As75 implantation through the 350°A oxide of B.L. Crowder and F.F. Morehead, who provided layer. The most significant thermal treatment after the B11 the ion implantations and related design information. implant was eleven minutes at 1000°C. Also important were the contributions of P. Hwang Good agreement was found between the threshold and W. Chang to two-dimensional device computa- characteristics of the experimental devices and the tions. J. J. Walker and V. DiLonardo assisted with the design predictions as shown in Fig. 2(b). The turn on mask preparation and testing activities. The devices characteristic of an experimental device of L=1.2 were fabricated by staff of the silicon technology microns displays the same behavior as the calculated facility at the T.J. Watson Research Center. characteristic. (See Fig. 3). The variation of threshold voltage with source-drain spacing (at maximum drain [1] R.H. Dennard, F.H. Gaensslen, L. Kuhn, and H.N. voltage) is shown in Fig.4 and compared with the cal- Yu, “Design of Micron MOS Switching Devices” culated values from Fig. 3 (D=0.2µ). IEEE IEDM, Dec. 1972. Several design perturbations were simulated to test [2] V.L. Rideout, F.H. Gaensslen, and A. LeBlanc, the sensitivity to key parameters. One variable which “Device Design Considerations for Ion Implanted was investigated was the use of a shallower implanted MOSFET’s” to be presented at IEEE IEDM, Dec. 1973. surface layer, D=0.1 microns deep, with the dose adjust- [3] D.P. Kennedy and P.C. Murley, “Steady State Math- ed to give about the same threshold value. Results for ematical Theory for the Insulated Gate Field Effect this case are also shown in Fig. 4. The shallower Transistor” IBM J. of Res. Develop. 17, 1, (1973).

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TECHNICAL ARTICLES Design of Ion-Implanted MOSFET’s with Very Small Physical Dimensions ROBERT H. DENNARD, MEMBER, IEEE, FRITZ H. GAENSSLEN, HWA-NIEN YU, MEMBER, IEEE, V. LEO RIDEOUT, MEMBER, IEEE, ERNEST BASSOUS, AND ANDRE R. LEBLANC, MEMBER, IEEE

Reprinted from the IEEE Journal of Solid-State Circuits, Vol. SC-9, October 1974, pp. 256-268.

Abstract—This paper considers the design, fabrication, and characterization of very small LIST OF SYMBOLS MOSFET switching devices suitable for digital α Inverse semilogarithmic slope of sub-threshold characteristic. integrated circuits using dimensions of the order D Width of idealized step function profile for channel implant. of 1 μ. Scaling relationships are presented which Wf Work function difference between gate and substrate. , show how a conventional MOSFET can be si ox Dielectric constants for silicon and silicon dioxide. reduced in size. An improved small device struc- Id Drain current. k Boltzmann’s constant. ture is presented that uses ion implantation to κ Unitless scaling constant. provide shallow source and drain regions and a L MOSFET channel length. nonuniform substrate doping profile. One- μeff Effective surface mobility. dimensional models are used to predict the sub- ni Intrinsic carrier concentration. strate doping profile and the corresponding Na Substrate acceptor concentration. threshold voltage versus source voltage charac- s Band bending in silicon at the onset of strong inversion for teristic. A two-dimensional current transport zero substrate voltage. model is used to predict the relative degree of b Built-in junction potential. short-channel effects for different device param- q Charge on the electron. eter combinations. Polysilicon-gate MOSFET’s Q eff Effective oxide charge. with channel lengths as short as 0.5 μ were fab- tox Gate oxide thickness. T Absolute temperature. ricated, and the device characteristics measured V ,V ,V ,V Drain, source, gate and substrate voltages. and compared with predicted values. The per- d s g sub Vds Drain voltage relative to source. formance improvement expected from using Vs−sub Source voltage relative to substrate. these very small devices in highly miniaturized Vt Gate threshold voltage. integrated circuits is projected. ws, wd Source and drain depletion layer widths. W MOSFET channel width. INTRODUCTION New high resolution lithographic techniques for form- region in the silicon substrate under the gate elec- ing semiconductor integrated circuit patterns offer a trode. For switching applications, the most undesir- decrease in linewidth of five to ten times over the able ‘short-channel” effect is a reduction in the gate optical contact masking approach which is common- threshold voltage at which the device turns on, ly used in the semiconductor industry today. Of the which is aggravated by high drain voltages. It has new techniques, electron beam pattern writing has been shown that these short-channel effects can be been widely used for experimental device fabrication avoided by scaling down the vertical dimensions [1]-[4] while X-ray lithography [5] and optical projec- (e.g., gate insulator thickness, junction depth, etc.) tion printing [6] have also exhibited high-resolution along with the horizontal dimensions, while also pro- capability. Full realization of the benefits of these new portionately decreasing the applied voltages and high-resolution lithographic techniques requires the increasing the substrate doping concentration [7], [8]. development of new device designs, technologies, Applying this scaling approach to a properly and structures which can be optimized for very small designed conventional-size MOSFET shows that a dimensions. 200-Å gate insulator is required if the channel length This paper concerns the design, fabrication, and is to be reduced to 1μ. characterization of very small MOSFET switching A major consideration of this paper is to show how devices suitable for digital integrated circuits using the use of ion implantation leads to an improved dimensions of the order of 1μ. It is known that design for very small scaled-down MOSFET’s. First, reducing the source-to-drain spacing (i.e., the chan- the ability of ion implantation to accurately introduce nel length) of an FET leads to undesirable changes in a low concentration of doping atoms allows the sub- the device characteristics. These changes become sig- strate doping profile in the channel region under the nificant when the depletion regions surrounding the gate to be increased in a controlled manner. When source and drain extend over a large portion of the combined with a relatively lightly doped starting sub-

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state-of-the-art n-channel MOSFET [9] with a scaled- down device designed following the device scaling principles to be described later. The larger structure shown in Fig. 1(a) is reasonably typical of commercially available devices fabricated by using conventional diffusion techniques. It uses a 1000-Å gate insulator thickness with a substrate doping and substrate

bias chosen to give a gate threshold voltage Vt of approximately 2 V relative to the source potential. A Fig. 1. Illustration of device scaling principles with κ = 5. substrate doping of 5 x 1015 cm-3 is low enough to give (a) Conventional commercially available device structure. (b) Scaled-down device structure. an acceptable value of substrate sensitivity. The substrate sensitivity is an important criterion in digital strate, this channel implant reduces the sensitivity of switching circuits employing source followers the threshold voltage to changes in the source-to-sub- because the design becomes difficult if the threshold strate (“backgate”) bias. This reduced “substrate sen- voltage increases by more than a factor of two over sitivity” can then be traded off for a thicker gate insu- the full range of variation of the source voltage. For lator of 350-Å thickness which tends to be easier to the device illustrated in Fig. 1(a), the design parame- fabricate reproducibly and reliably. Second, ion ters limit the channel length L to about 5μ. This implantation allows the formation of very shallow restriction arises primarily from the penetration of the source and drain regions which are more favorable depletion region surrounding the drain into the area with respect to short-channel effects, while maintain- normally controlled by the gate electrode. For a max- ing an acceptable sheet resistance. The combination imum drain voltage of approximately 12-15 V this of these features in an all-implanted design gives a penetration will modify the surface potential and sig- switching device which can be fabricated with a nificantly lower the threshold voltage. thicker gate insulator if desired, which has well-con- In order to design a new device suitable for small- trolled threshold characteristics, and which has signif- er values of L, the device is scaled by a transformation icantly reduced interelectrode capacitances (e.g., in three variables: dimension, voltage, and doping. drain-to-gate or drain-to-substrate capacitances). First, all linear dimensions are reduced by a unitless This paper begins by describing the scaling princi- scaling factor κ, e.g. tox = tox/κ, where the primed ples which are applied to a conventional MOSFET to parameters refer to the new scaled-down device. This obtain a very small device structure capable of reduction includes vertical dimensions such as gate improved performance. Experimental verification of insulator thickness, junction depth, etc., as well as the the scaling approach is then presented. Next, the fab- horizontal dimensions of channel length and width. rication process for an improved scaled-down device Second, the voltages applied to the device are structure using ion implantation is described. Design reduced by the same factor (e.g. Vds = Vds/κ). Third, considerations for this all-implanted structure are the substrate doping concentration is increased, again based on two analytical tools: a simple one-dimen- using the same scaling factor (i.e., Na = κNa). The sional model that predicts the substrate sensitivity for design shown in Fig. 1(b) was obtained using κ = 5 long channel-length devices, and a two-dimensional which corresponds to the desired reduction in chan- current-transport model that predicts the device turn- nel length to 1μ. on characteristics as a function of channel length. The The scaling relationships were developed by predicted results from both analyses are compared observing that the depletion layer widths in the with experimental data. Using the two-dimensional scaled-down device are reduced in proportion to the simulation, the sensitivity of the design to various device dimensions due to the reduced potentials and parameters is shown. Then, detailed attention is given the increased doping. For example, to an alternate design, intended for zero substrate 1/2 bias, which offers some advantages with respect to ws ={[2si(ψb + Vs−sub/κ)]/qκNa} ws/κ. (1) threshold control, Finally, the paper concludes with a discussion of the performance improvements to be The threshold voltage at turn-on [9] is also decreased expected from integrated circuits that use these very in direct proportion to the reduced device voltages so small FET’s. that the device will function properly in a circuit with reduced voltage levels. This is shown by the thresh- DEVICE SCALING old voltage equation for the scaled-down device. The principles of device scaling [7], [8] show in a con- = ( /κ ){− + κ (ψ + /κ) 1/2} cise manner the general design trends to be followed Vt tox ox Q eff [2 Si q Na s Vs−sub ] in decreasing the size and increasing the performance + (W f + ψs ) Vt /κ. (2) of MOSFET switching devices. Fig. 1 compares a

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In (2) the reduction in Vt is primarily due to the due to the heavier doped substrate. Other scaling decreased insulator thickness, tox/κ, while the relationships for power density, delay time, etc., are changes in the voltage and doping terms tend to can- given in Table I and will be discussed in a subsequent cel out. In most cases of interest (i.e., polysilicon section on circuit performance. gates of doping type opposite to that of the substrate In order to verify the scaling relationships, two sets or aluminum gates on p-type substrates) the work of experimental devices were fabricated with gate function difference W f is of opposite sign, and insulators of 1000 and 200 Å (i.e., κ = 5). The meas- approximately cancels out ψs .ψs is the band ured drain voltage characteristics of these devices, bending in the silicon (i.e., the surface potential) at normalized to W /L = 1, are shown in Fig. 2. The two the onset of strong inversion for zero substrate bias. It sets of characteristics are quite similar when plotted would appear that the ψ terms appearing in (1) and with voltage and current scales of the smaller device (2) prevent exact scaling since they remain approxi- reduced by a factor of five, which confirms the scal- mately constant, actually increasing slightly due to the ing predictions. In Fig. 2, the exact match on the cur- increased doping since ψb ψs = (2kT/q) ln rent scale is thought to be fortuitous since there is (Na /ni ). However, the fixed substrate bias supply some experimental uncertainty in the magnitude of normally used with n-channel devices can be adjust- the channel length used to normalize the characteris- ed so that (ψs + Vsub ) = (ψs + Vsub)/κ . Thus, by tics (see Appendix). More accurate data from devices scaling down the applied substrate bias more than the with larger width and length dimensions on the same other applied voltages, the potential drop across the chip shows an approximate reduction of ten percent source or drain junctions, or across the depletion in mobility for devices with the heavier doped sub- region under the gate, can he reduced by κ. strate. That the threshold voltage also scales correctly All of the equations that describe the MOSFET by a factor of five√ is verified in Fig. 3, which shows device characteristics may be scaled as demonstrated the experimental Id versus Vg turn-on characteris- above. For example, the MOSFET current equation [9] tics for the original and the scaled-down devices. For given by the cases shown, the drain voltage is large enough to cause pinchoff and the characteristics exhibit the μ /κ − − / = eff ox W Vg Vt Vd 2 · expected linear relationship. When projected to inter- Id /κ /κ κ tox L cept the gate voltage axis this linear relationship (Vd /κ) = Id /κ (3) defines a threshold voltage useful for most logic circuit design purposes. is seen to be reduced by a factor of κ, for any given set of applied voltages, assuming no change in mobility. Actually, the mobility is reduced slightly due to increased impurity scattering in the heavier doped substrate. It is possible to generalize the scaling approach to include electric field patterns and current density. The electric field distribution is maintained in the scaled- down device except for a change in scale for the spatial coordinates. Furthermore, the electric field strength at any corresponding point is unchanged because V /x = V /x. Thus, the carrier velocity at any point is also unchanged due to scaling and, hence, any saturation velocity effects will be similar in both devices, neglecting microscopic differences due to the fixed crystal lattice dimensions. From (3), since the device current is reduced by κ, the channel current per unit of channel width W is unchanged by scaling. This is consistent with the same sheet density of carriers (i.e., electrons per unit gate area) moving at the same velocity. In the vicinity of the drain, the carriers will move away from the surface to a lesser extent in the new device, due to the shallower diffusions. Thus, the density of mobile carriers per unit volume will be Fig. 2. Experimental drain voltage characteristics for (a) higher in the space-charge region around the drain, conventional, and (b) scaled-down structures shown in complementing the higher density of immobile charge Fig. 1 normalized to W/L = 1.

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Fig. 3. Experimental turn-on characteristics for conventional and scaled-down devices shown in Fig. 1 normalized to W/L =1.

One area in which the device characteristics fail to scale is in the subthreshold or weak inversion region of the turn-on characteristic. Below threshold, Id is exponentially dependent on Vg with an inverse semilogarithmic slope, α, [10], [11] which for the scaled- down device is given by

Fig. 4. Detailed cross sections for (a) scaled-down device volts dVg structure, and (b) corresponding ion-implanted device α = structure. decade d log I 10 d /κ = ( / ) + Si tox , a factor of four, and an implanted boron surface layer kT q log10 e 1 (4) oxwd /κ having a concentration somewhat greater than the concentration used throughout the unimplanted struc- which is the same as for the original larger device. ture of Fig. 4(a). The concentration and the depth of The parameter α is important to dynamic memory cir- the implanted surface layer are chosen so that this cuits because it determines the gate voltage excursion heavier doped region will be completely within the required to go from the low current “off” state to the surface depletion layer when the device is turned on high current “on” state [11]. In an attempt to also with the source grounded. Thus, when the source is extend the linear scaling relationships to α one could biased above ground potential, the depletion layer reduce the operating temperature in (4) (i.e., will extend deeper into the lighter doped substrate, T = T/κ, but this would cause a significant increase and the additional exposed “bulk” charge will be rea- in the effective surface mobility [12] and thereby inval- sonably small and will cause only a modest increase idate the current scaling relationship of (3). In order in the gate-to-source voltage required to turn on the to design devices for operation at room temperature device. With this improvement in substrate sensitivity and above, one must accept the fact that the sub- the gate insulator thickness can be increased to as threshold behavior does not scale as desired. This much as 350 Å and still maintain a reasonable gate nonscaling property of the subthreshold characteristic threshold voltage as will be shown later. is of particular concern to miniature dynamic memo- Another aspect of the design philosophy is to use ry circuits which require low source-to-drain leakage shallow implanted n+ regions of’ depth comparable to currents. the implanted p-type surface layer. The depletion regions under the gate electrode at the edges of the ION-IMPLANTED DEVICE DESIGN source and drain are then inhibited by the heavier The scaling considerations just presented lead to the doped surface layer, roughly pictured in Fig. 4(b), for device structure with a 1-μ channel length shown in the case of a turned-off device. The depletion regions Fig. 4(a). In contrast, the corresponding improved under the source and drain extend much further into design utilizing the capability afforded by ion implan- the lighter doped substrate. With deeper junctions tation is shown in Fig. 4(b). The ion-implanted device these depletion regions would tend to merge in the uses an initial substrate doping that is lower by about lighter doped material which would cause a loss of

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threshold control or, in the extreme, punchthrough at the edges of the gates. The gate-to-drain (or source) high drain voltages. However, the shallower junctions overlap is estimated to be of the order of 0.2 μ. The give a more favorable electric field pattern which high temperature processing steps that follow the avoids these effects when the substrate doping con- implantations include 20 min at 900°C, and 11 min at centration is properly chosen (i.e., when it is not too 1000°C, which is more than adequate to anneal out light). the implantation damage without greatly spreading The device capacitances are reduced with the ion- out the implanted doses. Typical sheet resistances implanted structure due to the increased depletion were 50/ for the source and drain regions, and layer width separating the source and drain from the 40/ for the polysilicon areas. Following the As75 substrate [cf. Figs. 4(a) and 4(b)], and due to the nat- implant, a final insulating oxide layer 2000-Å thick ural self-alignment afforded by the ion implantation was deposited using low-temperature chemical-vapor process which reduces the overlap of the polysilicon deposition. Then, the contact holes to the n+ and gate over the source and drain regions. The thicker polysilicon regions were defined, and the metalization gate insulator also gives reduced gate capacitance, but was applied and delineated. Electrical contact directly the performance benefit in this respect is offset by the to the shallow implanted source and drain regions decreased gate field. To compensate for the thicker was accomplished by a suitably chosen metallurgy to gate oxide and the expected threshold increase, a avoid junction penetration due to alloying during the design objective for maximum drain voltage was set final annealing step. After metalization an annealing at 4 V for the ion-implanted design in Fig. 4(b), com- step of 400 °C for 20 min in forming gas was per- pared to 3 V for the scaled-down device of Fig.4(a). formed to decrease the fast-state density.

FABRICATION OF ION-IMPLANTED MOSFET’s ONE-DIMENSIONAL (LONG CHANNEL) The fabrication process for the ion-implanted MOS- ANALYSIS FET’s used in this study will now be described. A The substrate doping profile for the 40 keV, four-mask process was used to fabricate polysilicon- 6.7 × 1011 atoms/cm2 channel implant incident on gate, n-channel MOSFET’s on a test chip which con- the 350-Å gate oxide, is shown in Fig. 5. tains devices with channel lengths ranging from 0.5 to 10 μ. Though the eventual aim is to use electron- beam pattern exposure, it was more convenient to use contact masking with high quality master masks for process development. For this purpose high resolution is required only for the gate pattern which uses lines as small as 1.5 μ which are reduced in the subsequent processing. The starting substrate resistivity was 2 ·cm (i.e., about 7.5 × 1015cm−3). The method of fabrication for the thick oxide isolation between adjacent FET’s is not described as it is not essential to the work presented here, and because several suitable techniques are available. Following dry thermal growth of the gate oxide, low energy (40 keV), low dose (6.7 × 1011 atoms/cm2) B11 ions were implanted into the wafers, raising the boron doping near the silicon surface. All implantations were performed after gate oxide growth in order to restrict diffusion of the implanted regions. After the channel implantation, a 3500-Å thick poly- Fig. 5. Predicted substrate doping profile for basic ion- implanted device design for 40 keV B11 ions implanted silicon layer was deposited, doped n+, and the gate through the 350-Å gate insulator. regions delineated. Next, n+ source and drain regions 2000-Å deep were formed by a high energy (100 Since the oxide absorbs 3 percent of the incident keV), high dose (4 × 1015 atoms/cm2) As75 implanta- dose, the active dose in the silicon is 6.5 × 1011 tion through the same 350-Å oxide layer. During this atoms/cm2. The concentration at the time of the step, however, the polysilicon gate masks the channel implantation is given by the lightly dashed Gaussian 75 region from the implant, absorbing all of the As function added to the background doping level, Nb. dose incident there. The etching process used to For 40 keV B11 ions, the projected range and standard delineate the gates results in a sloping sidewall which deviation were taken as 1300 Å and 500 Å, respec- allows a slight penetration of As75 ions underneath tively [13]. After the heat treatments of the subsequent

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processing, the boron is redistributed as shown by the and a reasonably low substrate sensitivity, particular- heavier dashed line. These predicted profiles were ly for Vs−sub ≥ 1 V. For Vs−sub < 1 V, a steep slope obtained using a computer program developed by F. occurs because the surface inversion layer in the F. Morehead of our laboratories. The program channel is obtained while the depletion region in the assumes that boron atoms diffusing in the silicon silicon under the gate does not exceed D, the step reflect from the silicon-oxide interface and thereby width of the heavier doped implanted region. For raise the surface concentration. For modeling purpos- Vs−sub ≥ 1 V, at inversion the depletion region now es it is convenient to use a simple, idealized, step- extends into the lighter doped substrate and the function representation of the doping profile, as threshold voltage then increases relatively slowly with shown by the solid line in Fig. 5. The step profile Vs−sub [11]. Thus, with a fixed substrate bias of -1 V, approximates the final predicted profile rather well the substrate sensitivity over the operating range of and offers the advantage that it can be described by a the source voltage (e.g., ground potential to 4 V) is few simple parameters. The three profiles shown in reasonably low and very similar to the slope of the Fig. 5 all have the same active dose. nonimplanted 200-Å design. However, the threshold Using the step profile, a model for determining voltage is significantly higher for the implanted design threshold voltage has been developed from piecewise which allows adequate design margin so that, under solutions of Poisson’s equation with appropriate worst case conditions (e.g., short-channel effects boundary conditions [11]. The one-dimensional model which reduce the threshold considerably), the thresh- considers only the vertical dimension and cannot old will still be high enough so that the device can be account for horizontal short-channel effects. Results of turned off to a negligible conduction level as required the model are shown in Fig, 6 which plots the thresh- for dynamic memory applications. old voltage versus source-to-substrate bias for the ion- Experimental results are also given in Fig. 6 from implanted step profile shown in Fig. 5. For compari- measurements made on relatively long devices (i.e., son, Fig. 6 also shows the substrate sensitivity charac- L = 10μ) which have no short-channel effects. teristics for the nonimplanted device with a 200-Å These data agree reasonably well with the calculat- gate insulator and a constant background doping, and ed curve. A 35 keV, 6 × 1011 atoms/cm2 implant was for a hypothetical device having a 350-Å gate insula- used to achieve this result, rather than the slightly tor like the implanted structure and a constant back- higher design value of 40 keV and 6.7 × 1011 ground doping like the nonimplanted structure. atoms/cm2.

TWO-DIMENSIONAL (SHORT CHANNEL) ANALYSIS For devices with sufficiently short-channel lengths, the one-dimensional model is inadequate to account for the threshold voltage lowering due to penetration of the drain field into the channel region normally controlled by the gate. While some models have been developed which account for this behavior [14], the problem is complicated for the ion-implanted structure by the non-uniform doping profile which leads to an electric field pattern that is difficult to approximate. For the ion-implanted case, the two-dimensional numerical current transport model of Kennedy and Mock [15], [16] was utilized. The computer program was modified by W. Chang and P. Hwang [17] to han- dle the abrupt substrate doping profiles considered for these devices. Fig. 6. Calculated and experimental substrate sensitivity The numerical current transport model was characteristics for non-implanted devices with 200- and used to calculate the turn-on behavior of the ion- 350-Å gate insulators, and for corresponding ion-implanted device with 350-Å gate insulator. implanted device by a point-by-point computation of the device current for increasing values of The nonimplanted 200-Å case exhibits a low substrate gate voltage. Calculated results are shown in Fig. sensitivity, but the magnitude of the threshold voltage 7 for two values of channel length in the range of is also low. On the other hand, the nonimplanted 350- 1μ, as well as for a relatively long-channel device Å case shows a higher threshold, but with an unde- with L = 10μ. All cases were normalized to a sirably high substrate sensitivity. The ion-implanted width-to-length ratio of unity, and a drain voltage case offers both a sufficiently high threshold voltage of 4 V was used in all cases. As the channel length

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Fig. 7. Calculated and experimental subthreshold turn-on characteristic for basic ion-implanted design for various channel lengths with Vsub = -1V, Vd = 4V. Fig. 8. Experimental and calculated dependence of thresh- μ old voltage on channel length for basic ion-implanted is reduced to the order of 1 , the turn-on charac- design with V =-1V, V = 4V. teristic shifts to a lower gate voltage due to a low- sub d ering of the threshold voltage. The threshold volt- degree of control of L can be achieved. The experi- age occurs at about 10−7 A where the turn-on char- mental drain characteristics for an ion-implanted acteristics make a transition from the exponential MOSFET with a 1.1-μ channel length are shown in subthreshold behavior (a linear response on this Fig. 9 for the grounded source condition. The gener- 2 semilogarithmic plot) to the Id ∝ Vg square-law behavior. This current level can also be identified from Fig. 3 as the actual current at the projected threshold voltage, Vt . When the computed characteristics were plotted in the manner of Fig. 3 they gave 4 × 10−8 A at threshold for all device lengths. The band bending, ψs , at this threshold condition is approximately 0.75 V. Some of the other device designs considered with heavier substrate concen- trations gave a higher current at threshold, so, for simplicity, the value of 10−7 A was used in all cases Fig. 9. Experimental drain voltage characteristics for basic ion-implanted design with V = 1V, L = 1.1μ, and w = with a resultant small error in . sub Vt μ Ω MOSFET’s with various channel lengths were 12.2 . Curve tracer parameters; load resistance 30 , drain voltage 4 V, gate voltage 0-4V in 8 steps each 0.5 V apart. measured to test the predictions of the two-dimensional model. The technique for experimentally determining the channel length for very short devices is al shape of the characteristics is the same as those described in the Appendix. The experimental results observed for much larger devices. No extraneous are plotted in Fig. 7 and show good agreement with short-channel effects were observed for drain voltages the calculated curves, especially considering the as large as 4 V. The experimental data in Figs. 6 - 9 somewhat different values of L. Another form of pres- were taken from devices using a B11 channel implan- entation of this data is shown in Fig. 8 where the tation energy and dose of 35 keV and 6.0 × 1011 threshold voltage is plotted as a function of channel atoms/cm2, respectively. length. The threshold voltage is essentially constant The two-dimensional simulations were also used to for L > 2μ, and falls by a reasonably small amount as test the sensitivity of the design to various parameters. L is decreased from 2 to 1 μ, and then decreases The results are given in Fig. 10, which tabulates val- more rapidly with further reductions in L. For circuit ues of threshold voltage as a function of channel applications the nominal value of L could be set length for the indicated voltages. Fig. 10(a) is an ide- somewhat greater than 1 μ so that, over an expected alized representation for the basic design that has range of deviation of L, the threshold voltage is rea- been discussed thus far. The first perturbation to the sonably well controlled. basic design was an increase in junction depth to 0.4 For example, L = 1.3±0.3μ would give μ. This was found to give an appreciable reduction Vt = 1.0±0.1 V from chip to chip due to this short- in threshold voltage for the shorter devices in Fig. channel effect alone. This would be tolerable for 10(b). Viewed another way, the minimum device many circuit applications because of the tracking of length would have to be increased by 20 percent different devices on a given chip, if indeed this (from 1.0 to 1.2 μ) to obtain a threshold comparable

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In fact, the threshold for this case for a device with L = 0.8μ is about the same as for an L = 1.0μ device of the basic design. This important improvement is apparently due to the reduced depletion layer widths around the source and drain with the lower voltage drop across those junctions. Also, with these bias and doping conditions, the depletion layer depth in the silicon under the gate is much less at threshold, particularly near the source where only the band bending, ψs , appears across this depletion region, which may help prevent the penetration of field lines from the drain into this region where the device turn-on is controlled.

CHARACTERISTICS OF THE ZERO SUBSTRATE BIAS DESIGN Since the last design shown in Fig. 10(e) appears to be better behaved in terms of short-channel effects, it is worthwhile to review its properties more fully. Experimental devices corresponding to this design were built and tested with various channel lengths. In this case a 20 ke V, 6.0 × 1011 atoms/cm2 B11 implant was used to obtain a shallower implanted layer of approximately 1000-Å depth [11]. Data on threshold voltage for these devices with 4 V applied to the drain is presented in Fig. 11 and corresponds very well to Fig. 10. Threshold voltage calculated using two-dimen- the calculated values. Data for a small drain voltage is sional current transport model for various parameter con- also given in this figure, showing much less variation ditions. A flat-band voltage of -1.1 V is assumed. of threshold with channel length, as expected. The dependence of threshold voltage on source-to-sub- to the basic design. This puts the value of the shal- strate bias is shown in Fig. 12 for different values of lower junctions in perspective. Another perturbation L. The drain-to-source voltage was held at a constant from the basic design which was considered was the low value for this measurement. The results show that use of a substrate doping lighter by a factor of 2, the substrate sensitivity is indeed about the same for with a slightly higher concentration in the surface this design with zero substrate bias as for the original layer to give the same threshold for a long-channel design with Vsub =−1 V. Note that the smaller devices device [Fig. 10(c)]. The results for smaller devices show a somewhat flatter substrate sensitivity charac- proved to be similar to the case of deeper junctions. teristic with relatively lower thresholds at high values The next possible departure from the basic design is of source (and drain) voltage. the use of a shallower boron implantation in the channel region, only half as deep, with a heavier concentration to give the same long-channel threshold [Fig. 10(d)]. With the shallower profile, and considering that the boron dose implanted in the silicon is about 20 percent less in this case, it was expected that more short-channel effects would occur. How- ever, the calculated values show almost identical thresholds compared to the basic design. With the shallower implantation it is possible to use zero substrate bias and still have good substrate sensitivity since the heavier doped region is completely depleted at turn-on with a grounded source. The last design perturbation considers such a case, again with a heavier concentration to give the same long- Fig. 11. Experimental and calculated dependence of channel threshold [Fig. 10 (e)]. The calculations for threshold voltage on channel length for ion-implanted this case show appreciably less short-channel effect. zero substrate bias design.

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temperature aggravates the situation [18]. Thus, for dynamic memory, the basic design with Vsub =−1 V presented earlier is preferred.

CIRCUIT PERFORMANCE WITH SCALED- DOWN DEVICES The performance improvement expected from using very small MOSFET’s in integrated circuits of comparably small dimensions is discussed in this section. First, the performance changes due to size reduction alone are obtained from the scaling considerations given earlier. The influence on the circuit perform- Fig. 12. Substrate sensitivity characteristics for ion- implanted zero substrate bias design with channel length ance due to the structural changes of the ion-implant- as parameter. ed design is then discussed. Table I lists the changes in integrated circuit per- The turn-on characteristics for the zero substrate formance which follow from scaling the circuit bias design, both experimental and calculated, are dimensions, voltages, and substrate doping in the shown in Fig. 13 for different values of L. The rela- same manner as the device changes described with respect to Fig. 1. These changes are indicated in terms of the dimensionless scaling factor κ.

TABLE I SCALING RESULTS FOR CIRCUIT PERFORMANCE

Justifying these results here in great detail would be Fig. 13. Calculated and experimental subthreshold turn-on tedious, so only a simplified treatment is given. It is characteristics for ion-implanted zero substrate bias argued that all nodal voltages are reduced in the design. miniaturized circuits in proportion to the reduced supply voltages. This follows because the quiescent tively small shift in threshold for the short-channel voltage levels in digital MOSFET circuits are either the devices is evident; however, the turn-on rate is con- supply levels or some intermediate level given by a siderably slower for this case than for the Vsub =−1 V voltage divider consisting of two or more devices, and case shown in Fig. 7. This is due to the fact that the because the resistance V /I of each device is depletion region in the silicon under the gate is very unchanged by scaling. An assumption is made that shallow for this zero substrate bias case so that a large parasitic resistance elements are either negligible or portion of a given gate voltage change is dropped unchanged by scaling, which will be examined sub- across the gate insulator capacitance rather than sequently. The circuits operate properly at lower volt- across the silicon depletion layer capacitance. This is ages because the device threshold voltage Vt scales discussed in some detail for these devices in another as shown in (2), and furthermore because the toler- paper [11]. The consequence for dynamic memory ance spreads on Vt should be proportionately applications is that, even though the zero substrate reduced as well if each parameter in (2 ) is controlled bias design offers improved threshold control for to the same percentage accuracy. Noise margins are strong inversion, this advantage is offset by the flatter reduced, but at the same time internally generated subthreshold turn-on characteristic. For such applica- noise coupling voltages are reduced by the lower sig- tions the noise margin with the turn-on characteristic nal voltage swings. of Fig. 13 is barely suitable if the device is turned off Due to the reduction in dimensions, all circuit ele- by bringing its gate to ground. Furthermore, elevated ments (i.e., interconnection lines as well as devices)

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will have their capacitances reduced by a factor of κ. high performance circuits by widening the power This occurs because of the reduction by κ2 in the area buses and by avoiding the use of n+ doped lines for of these components, which is partially cancelled by signal propagation. the decrease in the electrode spacing by κ due to Use of the ion-implanted devices considered in this thinner insulating films and reduced depletion layer paper will give similar performance improvement to widths. These reduced capacitances are driven by the that of the scaled-down device with κ = 5 given in unchanged device resistances V /I giving decreased Table I. For the implanted devices with the higher transition times with a resultant reduction in the delay operating voltages (4 V instead of 3 V) and higher time of each circuit by a factor of κ. The power dissi- threshold voltages (0.9 V instead of 0.4 V), the current 2 2 pation of each circuit is reduced by κ due to the level will be reduced in proportion to (Vg − Vt ) /tox reduced voltage and current levels, so the power- to about 80 percent of the current in the scaled-down delay product is improved by κ3. Since the area of a device. The power dissipation per circuit is thus about given device or circuit is also reduced by κ2, the the same in both cases. All device capacitances are power density remains constant. Thus, even if many about a factor of two less in the implanted devices, more circuits are placed on a given integrated circuit and n+ interconnection lines will show the same chip, the cooling problem is essentially unchanged. improvement due to the lighter substrate doping and decreased junction depth. Some capacitance elements TABLE II such as metal interconnection lines would be essen- SCALING RESULTS FOR INTERCONNECTION LINES tially unchanged so that the overall capacitance improvement in a typical circuit would be somewhat Parameter Scaling Factor less than a factor of two. The delay time per circuit ρ κ / Line resistance, RL = L/Wt which is proportional to VC I thus appears to be κ Normalized voltage drop IRL/V about the same for the implanted and for the directly Line response time RLC l scaled-down micron devices shown in Fig. 4. Line current density I/A κ SUMMARY As indicated in Table II, a number of problems This paper has considered the design, fabrication, and arise from the fact that the cross-sectional area of characterization of very small MOSFET switching conductors is decreased by κ2 while the length is devices. These considerations are applicable to high- decreased only by κ. It is assumed here that the ly miniaturized integrated circuits fabricated by high- thicknesses of the conductors are necessarily reduced resolution lithographic techniques such as electron- along with the widths because of the more stringent beam pattern writing. A consistent set of scaling rela- resolution requirements (e.g., on etching, etc.). The tionships were presented that show how a conven- conductivity is considered to remain constant which is tional device can be reduced in size; however, this reasonable for metal films down to very small dimen- direct scaling approach leads to some challenging sions (until the mean free path becomes comparable technological requirements such as very thin gate to the thickness), and is also reasonable for degener- insulators. It was then shown how an all ion-implant- ately doped semiconducting lines where solid solu- ed structure can be used to overcome these difficul- bility and impurity scattering considerations limit any ties without sacrificing device area or performance. A increase in conductivity. Under these assumptions the two-dimensional current transport model modified for resistance of a given line increases directly with the use with ion-implanted structures proved particularly scaling factor κ. The IR drop in such a line is there- valuable in predicting the relative degree of short- fore constant (with the decreased current levels), but channel effects arising from different device parame- is κ times greater in comparison to the lower operat- ter combinations. The general objective of the study ing voltages. The response time of an unterminated was to design an n-channel polysilicon-gate MOSFET transmission line is characteristically limited by its with a 1-μ channel length for high-density source-fol-

time constant RLC, which is unchanged by scaling; lower circuits such as those used in dynamic memo- however, this makes it difficult to take advantage of ries. The most satisfactory combination of subthresh- the higher switching speeds inherent in the scaled- old turn-on range, threshold control, and substrate down devices when signal propagation over long sensitivity was achieved by an experimental MOSFET lines is involved. Also, the current density in a scaled- that used a 35 keV, 6.0 × 1011 atoms/cm2 B11 channel down conductor is increased by κ, which causes a implant, a 100 keV, 4 × 1015 atoms/cm2 As75 reliability concern. In conventional MOSFET circuits, source/drain implant, a 350-Å gate insulator, and an these conductivity problems are relatively minor, but applied substrate bias of –1 V. Also presented was an they become significant for linewidths of micron ion-implanted design intended for zero substrate bias dimensions. The problems may he circumvented in that is more attractive from the point of view of

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threshold control but suffers from an increased sub- deduce W from the resistance of a long, slender, n+ threshold turn-on range. Finally the sizable perform- line. The channel resistance can be calculated from ance improvement expected from using very small = / MOSFET’s in integrated circuits of comparably small Rchan Vchan Id dimensions was projected. = (Vd –Id (R s + Rd + 2Rc + Rload))/Id ,(A2)

APPENDIX where Rc is the contact resistance of the source or EXPERIMENTAL DETERMINATION OF drain, and Rload is the load resistance of the measure- CHANNEL LENGTH ment circuit. Id was determined at Vg = Vt + 0.5 V A technique for determining the effective electrical with a small applied drain voltage of 50 or 100 mV. channel length L for very small MOSFET’s from exper- The procedure is more simple and accurate if one imental data is described here. The technique is based uses a set of MOSFET’s having different values of on the observation that L mask but all with the same value of Wmask. Then one needs only to plot Rchan versus L mask in order to WRchan = Lρchan (A1) determine L.

where Rchan is the channel resistance, and ρchan the Acknowledgements sheet resistance of the channel. For a fixed value of We wish to acknowledge the valuable contributions Vg − Vt > 0, and with the device turned on in the of B. L. Crowder and F. F. Morehead who provided below-pinchoff region, the channel sheet resistance is the ion implantations and related design information. relatively independent of L. Then, a plot of WRchan Also important were the contributions of P. Hwang versus L mask will intercept the L mask axis at L and W. Chang to two-dimensional device computa- because L = L mask − L , where L is the processing tions. J. J. Walker and V. DiLonardo assisted with the reduction in the mask dimension due to exposure and mask preparation and testing activities. The devices etching. An example of this technique is illustrated in were fabricated by the staff of the silicon technology Fig. 14. facility at the T. J. Watson Research Center.

References [1] F. Fang, M. Hatzakis, and C. H. Ting, “Electron- beam fabrication of ion implanted high-performance FET circuits,” J. Vac. Sci. Technol., vol. 10, p. 1082, 1973. [2] J. M. Pankrantz, H. T. Yuan, and L. T. Creagh, “A high-gain, low-noise transistor fabricated with electron beam lithography,” in Tech. Dig. Int. Electron Devices Meeting, Dec. 1973, pp. 44-46. [3] H. N. Yu, R. H. Dennard, T. H. P. Chang, and M. Hatzakis, “An experimental high-density memory array fabricated with election beam,” in ISSCC Dig. Tech. Papers, Feb. 1973, pp. 98-99. [4] R. C, Henderson, R. F. W. Pease, A. M. Voshchenkow, P. Mallery, and R. L. Wadsack, “A high speed p-channel random access 1024-bit memory made with electron lithography,” in Tech. Dig. Int. Electron Devices Meeting, Dec. 1973, pp. 138-140. [5] D. L. Spears and H. I. Smith, “X-Ray lithography Fig. 14. lllustration of experimental technique used to – a new high resolution replication process,” determine channel length, L. Solid State Technol., vol. 15, p.21, 1972. [6] S. Middlehoek, “Projection masking, thin pho- The experimental values of W and Rchan used in Fig. toresist layers and interference effects,” IBM J. 14 were obtained as follows. First, the sheet resist- Res. Develop., vol. 14, p. 117, 1970. ance of the ion-implanted n+ region was determined [7] R. H. Dennard, F. H, Gaensslen, L. Kuhn, and H. using a relatively large four-point probe structure. N. Yu, “Design of micron MOS switching Knowing the n+ sheet resistance allows us to compute devices,” presented at the IEEE Int. Electron the source and drain resistance R s and Rd , and to Devices Meeting, Washington, D.C., Dec. 1972.

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[8] A. N. Broers and R. H. Dennard, “Impact of elec- models, MOSFET device and integrated circuit design, tron beam technology on silicon device fabrica- and FET memory cells and organizations. Since 1971 tion,” Semicond. Silicon (Electrochem. Soc. Pub- he has been manager of a group which is exploring lication), H. R. Huff and R. R. Burgess, eds., pp. high density digital integrated circuits using advanced 830-841, 1973. technology concepts such as electron beam pattern [9] D. L. Critchlow, R. H. Dennard, and S. E. Schus- exposure. ter, “Design characteristics of n-channel insulated-gate field-effect transistors,” IBM J. Res. Fritz H. Gaensslen was born in Develop., vol. 17, p. 430, 1973. Tuebingen, Germany, on October [10] R. M. Swanson and J. D. Meindl, “Ion-implanted 4, 1931. He received the DipI. Ing. complementary MOS transistors in low-voltage and Dr. Ing. degrees in electrical circuits,” IEEE J. Solid-State Circuits, vol. SC-7, engineering from the Technical pp. 146-153, April 1972. University of Munich, Munich, [11] V. L. Rideout, F. H. Gaensslen, and A. LeBlanc, Germany, in 1959 and 1966, “Device design considerations for ion implanted respectively. n-channel MOSFET’s,” IBM J. Res. Develop., to Prior to 1966 he served as Assistant Professor in the be published. Department of Electrical Engineering, Technical Uni- [12] F. F. Fang and A. B. Fowler, “Transport proper- versity of Munich, Munich, Germany. During this peri- ties of electrons in inverted Si surfaces,” Phys. od he was working on the synthesis of linear and dig- Rev. vol. 169, p. 619, 1968. ital networks. In 1966 he joined the IBM T. J. Watson [13] W. S. Johnson, IBM System Products Division, E. Research Center, Yorktown Heights, N.Y., where he is Fishkill, N. Y., private communication. currently a member of a semiconductor device and [14] H. S. Lee, “An analysis of the threshold voltage process design group. His current technical interests for short channel IGFET’s,” Solid-State Electron., involve various aspects of advanced integrated cir- vol. 16, p. 1407, 1973. cuits like miniaturization, device simulation, and ion [15] D. P. Kennedy and P. C. Murley, “Steady state implantation. From September 1973 he was on a one mathematical theory for the insulated gate field year assignment at the IBM Laboratory, Boeblingen, effect transistor,” IBM J. Res. Develop., vol. 17, p. Germany. 1, 1973. Dr. Gaensslen is a member of the Nachrichtentech- [16] M. S. Mock, “A two-dimensional mathematical nische Gesellschaft. model of the insulated-gate field-effect transistor,” Solid-State Electron., vol.16, p. 601, 1973. Hwa-Nien Yu (M’65) was born in [17] W. Chang and P. Hwang, IBM System Products Shanghai, China, on January 17, Division, Essex Junction, Vt., private communi- 1929. He received the B.S., MS., and cation. Ph.D. degrees in electrical engi- [18] R. R. Troutman, “Subthreshold design considera- neering from the University of Illi- tions for insulated gate field-effect transistors,” nois, Urbana, in 1953, 1954, and IEEE J. Solid-State Circuits, vol. SC-9, p.55, April 1958, respectively. While at the Uni- 1974. versity, he was a Research Assistant in the Digital Computer Laboratory and worked on Robert H. Dennard (M’65) was the design of the Illiac-II computer. Since joining the born in Terrell, Texas, in 1932. He IBM Research Laboratory in 1957, he has been received the B.S. and M.S. degrees engaged in various exploratory solid-state device in electrical engineering from research activities. After working with the Advanced Southern Methodist University, Dal- Systems Development Division from 1959 to 1962, las, Tex., in 1954 and 1956, respec- he rejoined the Research Division in 1962 to work tively, and the Ph.D. degree from on the ultra-high speed germanium device technol- Carnegie Institute of Technology, ogy. Since 1967, he has been engaged in advanced Pittsburgh, Pa., in 1958. silicon LSI device technology research. He is cur- In 1958 he joined the IBM Research Division where rently the Manager of Semiconductor Technology at his experience included study of new devices and cir- the IBM T. J. Watson Research Center, Yorktown cuits for logic and memory applications, and devel- Heights, N.Y. opment of advanced data communication techniques. Dr. Yu is a member of Sigma Xi. Since 1963 he has been at the IBM T. J. Watson Research Center, Yorktown Heights, N.Y., where he V. Leo Rideout (S’61—M’65) was born in N.J. in 1941. worked with a group exploring large-scale integration He received the BS.E.E. degree with honors in 1963 (LSI), while making contributions in cost and yield from the University of Wisconsin, Madison, the

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M,S.E.E. degree in 1964 from Stan- N.Y. in 1965. ford University, Stanford, Calif., and From 1954 to 1959 he taught Chemistry and the Ph.D. degree in materials sci- Physics at the British Boys’ School, Alexandria, ence in 1970 from the University of Egypt. He went to France in 1959 where he worked Southern California (U.S.C.), Los for one year on infra red detectors at the Centre Angeles. His thesis work at U.S.C. National d’Etudes des Telecommunications, Issy-les- under Prof. C. H. Crowell concerned Moulineaux, Seine. From 1960 to 1964 he worked at thermally assisted current transport the Thomas A. Edison Research Laboratory in West in platinum silicide Schottky barriers. Orange, N.J., where his activities included studies in From 1963 to 1965 he was a member of the techni- arc discharge phenomena, ultra violet absorption cal staff of Bell Telephone Laboratories where he spectroscopy, and organic semiconductors. In 1964 worked on high-frequency germanium transistors and he joined the IBM Research Laboratory, Yorktown metal-semiconductor Schottky barriers on potassium Heights, N.Y., to work on semiconductors. As a tantalate. In 1966 he spent a year as a Research Assis- member of the Research staff he is presently tant in the department of Materials Science at the Tech- engaged in the study of materials and processes nological University of Eindhoven, Eindhoven, The used in the fabrication of silicon integrated circuits. Netherlands, studying acoustoelectric effects in cadmi- Mr. Bassous is a member of the Electrochemical um sulphide. In 1970 he joined IBM Research in the Society and the American Association for the device research group of Dr. L. Esaki where he Advancement of Science. worked on fabrication and contact technology for mul- tiheterojunction “superlattice” structures using gallium- Andre R. LeBlanc (M’74) received arsenide-phosphide and gallium-aluminum-arsenide. the B.S. degree in electrical engi- Since 1972 he has been a member of the semiconduc- neering, and the M.S. degree in tor device and circuit design group of Dr. R. Dennard physics from the University of Ver- at the IBM T. J. Watson Research Center, Yorktown mont, Burlington, in 1956 and Heights, N.Y. His present research interests concern 1959, respectively, and the D.Sc. high density silicon FET technology. He is the author degree in electrical engineering or co-author of 20 technical papers and 3 US. Patents. from the University of New Mexico, Dr. Rideout is a member of the Electrochemical Albuquerque, in 1962. Society, Tau Beta Pi, Eta Kappa Nu, Phi Kappa Phi, Prior to joining IBM, Essex Junction, Vt., in 1957, he and Sigma Xi. was affiliated with G.E. as an electrical engineer and also with Sandia Corporation in conjunction with the Univer- Ernest Bassous was born in sity of New Mexico. In 1959 he took an educational Alexandria, Egypt, on September 1, leave of absence to complete his doctorate. He is 1931. He received the B.Sc. degree presently a member of the Exploratory Memory Group in chemistry from the University of at the IBM Laboratory, Essex Junction, where his current London, London, England in 1953, technical interest includes a study of short-channel MOS- and the M.S. degree in physical FET devices. He has authored five publications and chemistry from the Polytechnic twelve papers, as well as several IBM Technical Reports. Institute of Brooklyn, Brooklyn, Dr. LeBlanc is a member of Sigma Xi and Tau Beta Pi.

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PEOPLE An Interview with James Meindl 2006 IEEE Medal of Honor Receipient Microelectronics pioneer recognized with highest IEEE award

ames Meindl, friend and pio- was only two doors away from neer of the solid-state circuits me at Stanford. Jcommunity was recognized in 2006 with the highest IEEE Q. How successful have you been award, the IEEE Medal of Honor, predicting your students’ “for pioneering contributions to accomplishments? microelectronics, including low A. I have had my share of surpris- power, biomedical, physical limits es not as often related to thesis and on-chip interconnect net- research productivity as to down works.” Meindl, a prolific author, stream professional accomplish- energetic mentor and broad ments that I might have (or not thinker, accepted the award as the have) projected. Higher level highlight of the IEEE Honors cere- professional accomplishments mony in June 2006. are strongly related to “people Besides his outstanding technical skills.” My favorite question for contributions, Meindl is well known myself regarding a Ph.D. gradu- to the solid-state circuits communi- ate is “what did he do best?" ty for his service in many important James Meindl receiving the IEEE Medal of Honor June 2006 at the IEEE roles, serving as the first editor of award ceremony. Researching the Future the JSSC and chair of the ISSCC. In Q. Defining problems, researching 2003 ISSCC recognized Meindl as ities is to engage the student in a to find solutions, communicat- the author with the highest number one quarter/semester special proj- ing the solutions, presenting of ISSCC papers during its first 50 ects course prior to any decision and writing which of these is years. He has more than 360 regarding a Ph.D. commitment. most fun and which is hardest? authored papers in IEEEXplore. For overseas students, this is often A. The most fun is finding an ele- not feasible and then at least a gant new solution and this is Q and A one academic year commitment what I strive to encourage every Meindl the Mentor with support is necessary based student to experience. Nothing Publishing 360 papers requires a on a resume and phone calls. is more challenging than asking lot of human interconnection, with the right question in unambigu- students and co-authors. Meindl is Q. What about written versus oral ous terms at the right time. an important force in generating qualifying exams? Checking solutions and inter- productive graduate students and A. Even though it was new to me preting them to extract deep industry leaders. Over his career, when I started on the faculty at insights are important aspects of he has supervised over 80 Ph.D. Stanford, I learned to prefer the Ph.D. research that I learned graduates at Stanford University, oral over a written exam because well at Carnegie Tech in the Rensselaer Polytechnic Institute the personal interaction with the 1950’s. and Georgia Institute of Technolo- student under challenging condi- gy, many of whom have gone on tions is extremely revealing. Q. What are the pros and cons of to have profound impact on the Observing the student “thinking research that ends up in the semiconductor industry. out loud and responding to public domain versus the clues” is most informative. research destined for privately Q. How do you select your gradu- held and licensed patents? ate students? Q. On picking thesis topics? A. The IP issues of today are com- A. The prime qualities I look for in A. My favorite word of advice to a plex and can be vexing. The selecting graduate students are Ph.D. student is “try the simplest SRC/MARCO Focus Center Pro- ability/talent, motivation/commit- case,” which I learned from Pro- gram, supported by a consor- ment, interpersonal skill/friendli- fessor William Shockley, Nobel tium of US companies and ness, integrity and responsive- Prize Recipient for the invention DARPA, has what I have found ness. The best test for these qual- of the transistor, whose office to be a quite reasonable

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approach to IP ownership: MARCO receives a non-exclu- he first Editor, James Meindl, then of the US Army Electronics sive royalty-free license to all Command had to be very diligent in his search for both adequate foreground IP and reasonable Tquantity and quality of papers for his first issues. assurance that any critical back- From the beginning, a decision was made that a major source of ground IP will be licensed for a papers for the JSSC should be the full-length versions of papers first reasonable royalty. Giving more presented at the ISSCC. However, this aspect took time. Many of the authority to the Provost’s office conference speakers at the ISSCC were not accustomed to publishing to negotiate IP agreements in refereed scholarly publications. After the vigorous refereeing and should help the current situa- selection process for paper presentation at the ISSCC, it was neces- tion. To be competitive global- sary to work rather carefully with prospective authors to encourage ly, US companies now need them for further effort to achieve the results for adequate publication university research results and in a major journal of the IEEE. the best interests of the country Dr. Meindl, as the first Editor made significant contributions, not are served when this happens. only in working with the authors to publish their good contributions in spite of the press of their dealing on a daily basis with the explod- Q. What are the new hot areas that ing technology of solid-state circuits and devices. In addition he set for the next decade? the tone for the Journal of Solid-State Circuits. In short order he was A. Electronics and more specifically able to achieve a high standard of quality and was able to establish ICs have been the principal driver a pattern of publishing major ISSCC presentations as regular title of the most important economic papers… event of the past half century, the From “The Origin of the Journal, the Council and the Conference information revolution. My view of of Solid-State Circuits” by Donald O. Pederson, JSSC, April 1984 the critical reason for the unprecedented impact of the IC is that it a marvelous consequence of a ment at the U.S. Army Electronics represents a fusion of the top- “fusion of the top-down and bot- Laboratory in Fort Monmouth, New down and bottom-up approaches tom-up approaches to nanotech- Jersey. He then joined Stanford to microelectronics that has now nololgy.” Top-down nanotechnolo- University in Palo Alto, California, evolved to become nanoelectron- gy has been used to pattern and where he developed low-power ics. Scaling is our common term for produce multibillion transistor chips integrated circuits and sensors for a the top-down approach. The bot- with minimum feature sizes now portable electronic reading aid for tom-up approach is epitomized by beyond 50 nm. Bottom-up nan- the blind, miniature wireless radio the self-assembled single crystal sil- otechnology has been used to pro- telemetry systems for biomedical icon ingot from which (now duce self-assembled single crystal research, and non-invasive ultra- 300mm) silicon wafers are sliced, ingots of silicon that are sliced to sonic imaging and blood-flow each yielding several hundred provide 300 mm diameter wafers for measurement systems. Dr. Meindl chips each now containing several microchip manufacturing. One was the founding director of the billion transistors. broad prospective is that to advance Integrated Circuits Laboratory and beyond the ultimate limits of CMOS a founding co-director of the Cen- Of course Moore’s Law will integrated electronics will require an ter for Integrated Systems at Stan- cease, perhaps in a 10-20 year time- elegant fusion of top-down and bot- ford. The latter was a model for frame. But my crystal ball suggests tom-up nanotechnology enabled by university and industry cooperative IC manufacturing will be important future discoveries and inventions in research in microelectronics. for more than double that number both physical and biological science From 1986 to 1993, Dr. Meindl of years. The “vacuum tube-to-tran- and engineering as profound as the was senior vice president for aca- sistor like” breakthrough that is mid-20th century inventions of the demic affairs and provost of Rens- needed to replace ICs will require a transistor and the integrated circuit. selaer Polytechnic Institute in Troy, much more elegant and still Carbon nanotube and graphene New York. In this role he was unknown fusion of top-down nan- nanoribbon technologies represent responsible for all teaching and otechnology in the sub-10nm range primitive examples of efforts to research. with self-assembled bottom-up nan- achieve such a fusion. He joined Georgia Tech in 1993 otechnology probably rooted in as director of its Microelectronic biochemical science. About James Meindl Research Center. In 1998, he Meindl accepted his award with Early in his career, Dr. Meindl became the founding director of these comments about technology. developed micropower integrated the Interconnect Focus Center, Early 21st century microchips are circuits for portable military equip- where he led a team of more than

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60 faculty members from MIT, solutions for solving interconnec- Garver Lamme Medal of the Amer- Stanford, Rensselaer, SUNY tivity problems that arise from try- ican Association for Engineering Albany, and Georgia Tech in a ing to interconnect billions of tran- Education, the J.J.Ebers Award of partnership with industry and gov- sistors within a tiny chip. the IEEE Electron Devices Society, ernment. His research at Georgia An IEEE Life Fellow, Dr. Meindl the IEEE Education Medal and the Tech includes exploring different is the recipient of the Benjamin IEEE Solid State Circuits Award.

Hugo De Man Awarded for Leadership in Integrated Circuit Design and Design Methodology Founder of IMEC recognized with highest SSCS award

basis of the platform based design switched-capacitor design, and methodology (this in the early was commercialized by Silvar- 1980s!) And De Man has major Lisco. A second project where I impacts on digital design” and collaborated with him was on the Rabaey cites the NORA CMOS as now ‘infamous’ Cathedral projects, an example. NORA stands for “No which really brought high-level Race,” which has precharge and synthesis to the foreground. Again, evaluation properties that enable Hugo observed early on that digi- one to design simple testing cir- tal signal processing was an area cuits for output stuck-at-zero, where design automation could stuck-at-one, stuck-open and have a big impact. Cathedral was stuck-on faults. widely known as one of the first Georges Gielen, professor at K. (and maybe last) instances of high- U. Leuven, lists fields that De Man level synthesis that was adopted in has contributed to: “advanced sim- industry.” Hugo De Man, Professor Emeritus at ulation (switched capacitors), high- the Katholieke Universitiet, Leuven, level synthesis (the different Cathe- Belgium, is the recipient of the 2007 IEEE Donald O. Pederson Technical dral projects), hardware-software Field Award in Solid-State Circuits. co-design, etc.” Much of this work has been taken up by spin-offs Hugo De Man, Professor Emeritus such as Silvar Lisco, EDC, and at the Katholieke Universiteit, Leu- CoWare. “His contributions to the ven, Belgium will receive the IEEE development of innovative design Donald O. Pederson Technical methodologies and related EDA Field Award in Solid-State Circuits, tools have enabled the design of on Monday 12 February 2007 at multi-million-transistor chips. Hugo the ISSCC for leadership in inte- and his colleagues have built IMEC grated circuit design and design (the Inter-University Microelectron- methodology. ics Center) and K.U. Leuven into Jan Rabaey, a U.C. Berkeley pro- the pre-eminent microelectronics His Royal Highness, the late King of fessor and a former graduate stu- research center in Europe.” Belgium, Boudewijn, talking with dent of De Man notes that De Man Rabaey recalls from their joint Hugo De Man while visiting the is responsible for “many firsts in projects that De Man “was quick microelectronics lab at the University the computer-aided design world - to observe that simulation tech- of Leuven in the seventies. mixed-mode simulation, switched- niques used for mixed-mode simu- capacitor simulation, digital signal lation as developed in the DIANA The IMEC Challenge processing optimization, high-level program could be easily adopted De Man comments that joining synthesis for DSP, silicon compila- to analyze discrete-time analog Roger Van Overstraeten’s team in tion, system-level design. De Man systems as well. This was the 1983 to set up IMEC was the great- was also the first to use the term beginning of the development of a est challenge of his career. IMEC is and ideas of ‘Meet-in-the-middle sophisticated environment that an independent research institute design methodology’, which is the ultimately covered all aspects of covering all aspects of micro-elec-

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tronics and combining internation- that you never walk alone but that was teaching.” al contract research by top players great things only happen when Claeys notes, “He initiated the in the field with doctoral level you stimulate the best people to so-called ‘student projects’ where- research, teaching and publica- join forces and have fun in doing by a group of 3 or 4 students had tions. According to Cor Claeys, a so. For that reason receiving the to work during the year on a ded- current Research Head at IMEC, it Don Pederson award is so dear to icated project. In the 70s it was a was formed from a small research me as I owe a lot to him, as does new teaching concept which later group of about 20 people at the everyone who had the privilege to became common practice.” University of Leuven. By the work with him. Gielen recalls that De Man intro- beginning of this decade IMEC had Another factor of luck is that I duced many “design projects in became the largest such group in belong to a generation that could our EE curriculum, where students Europe with 125 professional participate in the 60-year evolution could gain hands-on experiences researchers. Dave Hodges who from the single transistor circuit to with the course material. This knew and worked with him during the billion-transistor chip. Perhaps includes also many projects with De Man’s time as a post-doc at one of the most fascinating periods applying CAD software to VLSI U.C. Berkeley, 1970-71, says that in engineering history, although design.” De Man and others “built IMEC you never know.” Claeys can still remember how into the pre-eminent microelec- an exam question of De Man’s 35 tronics research center in Europe. Inspired Educator years ago required undergraduates It was always clear that he is a man De Man’s lectures were by far the to examine the whole picture with many talents. He and his stu- most inspiring of Rabaey’s under- before designing a circuit solution. dents have contributed much to graduate career. “In fact, they “I want to build a radio for my car the progress of microelectronics.” inspired me so much that I ulti- and I have to drive through the De Man explains, “IMEC helped mately changed my personal direc- Sahara, What type of technology in creating a great mixed industry- tion from control systems to inte- should I use? You first had to ana- university team to build a success- grated circuits,” Rabaey said. Gie- lyze the question: the desert ful research program on DSP sili- len also feels that De Man’s inspir- means a hot temperature, technol- con compilation, the results of ing lectures and presentations are ogy must reliable, before an which are still in use today. And his most memorable trait. Claeys answer could be given.” most of the team members have points out that even now as an Claeys pointed out that De Man either created their own spin-off emeritus professor, “his presenta- was available for the students companies, are captains of indus- tions are not at all a review of the when needed. “The assistants try or top level academics. So the history but more a look into the working for him and supervising greatest challenge became also the future. He is exploring new fields laboratories also had to treat the greatest fun as there is no satisfac- and tries to understand the physics students as a very valuable asset.” tion without overcoming some involved, their challenges and Claeys sums it up, “All his life he challenge first.” potentials their may bring in the remained an enthusiastic professor Willy Sansen, Head of ESAT- future.” who considered teaching as a very MICAS at K.U. Leuven, reports that Raebey recalls De Man was important job; I would more say a De Man’s “task has been to look known to be a fair but hard-driving mission in his life. Working togeth- around and provide advice to the advisor. His undergraduate lab er with students was an extremely policymakers of IMEC. He does mates made a movie for a Christ- important issue for him.” this exceedingly well!” mas party of De Man’s students “It is ironic, though, that De slaving on the terminals in the Man, despite being an inspired De Man Looks Back computer room, spewing tons of educator, never wrote a textbook “I was extremely lucky to meet computer paper from the printer, himself about digital design. Some two extra-ordinary visionary men- all this playing against the music of of his former students, like Jan tors who both became friends for Ike and Tina Turner’s “Proud Rabaey, have done so instead,” life: Roger Van Overstraeten and Mary” with the lyrics “Working for notes Gielen. Don Pederson. The first opened De Man every night and day.” De Man comments that a most the world of physics and technolo- Gielen recalls, “the large size of satisfying part of his career has gy for me, the second introduced the reading material for his cours- been seeing his Master and Ph.D. me to the passion of circuit and es. Hugo was infamous for that. students contribute to progress in system design and so many other He could motivate his students to the field worldwide, both in the good things in life. work themselves through the big academic world and in industry. Common to both was the vision piles of difficult material that he “For me, teaching is the most

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rewarding profession as it provides you with the opportunity to multi- Biography of Hugo De Man ply and transfer your knowledge Hugo De Man was born on September 19, 1940 in Boom, Belgium. and to help people to stimulate He received the Electrical Engineering and Ph.D. degrees from the their own great creative talent and Katholieke Universiteit Leuven (K.U. Leuven), Belgium, in 1964 and make it available to create a better 1968, respectively. society. I am extremely grateful to In 1968 he joined the K.U. Leuven, working on device physics and all of my students for this greatest IC design. From 1969 to 1971 he was a postdoc at U.C. Berkeley, in of all presents!” the CAD group of Prof. D.O. Pederson. In 1971 he returned to the K.U. Leuven, where he became full professor in 1974. Seeing Clearly And In 1975 he was a Visiting Associate Professor at U.C. Berkeley. He Conveying It was an Associate Editor for the IEEE Journal of Solid-State Circuits One of DeMan’s principles is that from 1975-1980 and Associate Editor for the IEEE Transactions on “if you cannot explain something CAD from 1982 to 1985. in simple words you don't know Prof. De Man has been advisor of 60 Ph.D. students. He has con- about what you are speaking. tributed to over 500 scientific publications and was keynote speaker Somebody can give high level at the ESSCIRC, DAC, DATE and ISSCC conferences. He was program technical presentations but often chair of ESSCIRC and DATE conferences. forget about basic things and con- He is co-founder of the Interuniversity Micro-Electronics Center cepts,” Claeys recalls. (IMEC) where, from 1984 to 1995, he was Vice-President of research Claeys continues by noting that on design methodologies for Integrated Telecom Systems. This group De Man would comment “many sci- created the CATHEDRAL suite of silicon compilation tools DSP chips entists are too much focused on and the COWARE hardware-software co design systems. This work their own narrow research field and and the co-design of numerous telecom and multimedia chips have the direct problems associated with resulted in 6 Spin-Off companies. them. Executing projects and attract- In 1995 he became a Senior Fellow of IMEC working on system ing new projects are key for them. design technologies. His interests continue in Technology Aware However, people should have a Design methods and education methods for SoC design. broad view and interest in order to Prof. De Man received best paper awards at ISSCC, ESSCIRC, ICCD put their own activities in the right and DAC and the 1985 Darlington Award of IEEE Circuits and Systems context and take sufficient time to Society. In 1999 he received the Technical Achievement Award of the think about future trends and chal- IEEE Signal Processing Society, The Phil Kaufman Award of the EDA lenges. He is a great scientist with Consortium and the Golden Jubilee Medal of IEEE CAS. In 2004 he an excellent scientific track record received the lifetime achievement awards of the European Design and but he also has a very good vision.” Automation Association (EDAA) as well as the European Electronics Rabaey agrees, “De Man is a real Industry. Since 2005 he has been Emeritus of the K.U. Leuven and is deep thinker - always listening and still active as Senior Fellow of IMEC. observing and from this distilling Prof. De Man is a Fellow of IEEE and a member of the Royal Acad- new visions. He also never emy of Sciences, Belgium. stopped learning. As such, he has impacted the directions of many people and companies.” always mature enough for imme- Sansen applauds De Man Georges Gielen continues, “De diate wide adoption in industrial receiving the Pederson award as Man is essentially a visionary practice.” “he has surely been one of the philosopher, who continuously Sansen always remembers De most ardent followers of Peder- looks ahead into the future Man’s laid-back kind of style, always son. He has been convinced all (future applications and societal providing a very broad view on along that CAD software is essen- needs, state of the technology, things. De Man has “a very broad tial to advance the design chips of etc.) and then tries to derive view on where microelectronics is high complexity. He has been in from that the research activities heading to; he continuously tries to the forefront to illustrate this. And that need to be started today. extrapolate how technologies and he has been very successful in The drawback of being a vision- system design can be teamed up putting out design software such ary though is that some of these towards higher complexity. Hugo that it could be used by design- tools were maybe commercial- deserves this prize as he has been ers; his ‘meet-in-the middle’ ized a bit too early in time, in the one of the longest followers of Don approach for system design has sense that the market was not Pederson,” observes Sansen. been exemplary.”

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Recipients of the IEEE Solid-State Circuit 1993 Kiyoo Itoh Awards 1992 Barrie Gilbert 1991 Frank Wanlass IEEE Donald O. Pederson Technical Field Award 1990 Toshi Masuhara in Solid-State Circuits 1989 James D. Meindl 2006 Mark A. Horowitz Solid-State Circuits Council Development Award IEEE Solid-State Circuits Technical Field Award 1988 Karl Stein 2005 Bruce A. Wooley 1987 Robert Widlar 2004 Eric Vittoz 1986 Barrie Gilbert 2003 Daniel Dobberpuhl 1985 Donald O. Pederson 2002 Chenming Hu and Ping Ko 2001 No Award The IEEE Solid-State Circuits Tech- 2000 Robert H. Krambreck and Stephen Law nical Field Award was created in 1999 Kensall D. Wise 1989 and was renamed the IEEE 1998 Nicky Lu Donald O. Pederson Technical 1997 Robert W. Brodersen Field Award in 2006. The awards 1996 Rudy J. van de Plassche before 1989 were Solid-State Cir- 1995 Lewis M. Terman cuits Council Award in Solid-State 1994 Paul R. Gray IEEE Pederson Circuits. Award Medal

Pioneer in Mixed Signal Circuits will Receive IEEE Gustav Robert Kirchhoff Award at ISSCC 2007 Yannis P. Tsividis to be honored in February for contributions to circuits and MOS device modeling. Katherine Olstein, SSCS Administrator, [email protected]

annis P. Tsividis will receive work throughout his career. the IEEE Gustav Robert “I changed Ph.D. topics twice YKirchhoff Field Award for before I found one that excited contributions to circuits and MOS me,” he said in an email interview. device modeling at the plenary ses- “It was exactly the prejudice that sion of the ISSCC in San Francisco, MOS ICs are only good for digital CA on 12 February 2007. The that presented a challenge to me. I Kirchhoff Award acknowledges still recall an industrial visitor at outstanding contributions with Berkeley, who came to see what I long-term impact to the fundamen- was doing in my thesis work, and tals of any aspect of electronic cir- said, with some irony, ‘So, you cuits and systems. want to make amplifiers out of When Glenn E. R. Cowan, a Tsi- switches?’” vidis graduate student at Columbia Today, the challenge of combin- University, recently applied for his “Like many EEs of my generation, I ing different domains is the first position after receiving the started as a child by building a crystal approach to research that he Ph.D., interviewers at IBM saw his radio, and have been tinkering ever enjoys most. “One of the pet proj- work with Dr. Tsividis on mixed-sig- since.” Yannis P. Tsividis ects in my group is continuous- nal VLSI computing as something transistor as part of his Ph.D. project, time DSPs, with no sampling or “different from the mainstream” and presented it at ISSCC 2003, and won aliasing – admittedly a long shot,” gave him an equally challenging the conference best paper award. he said. research job. A fellow student, Cowan recalled in a telephone inter- A Lifetime of Long Shots Potential of Mixed Signal view, developed a Tsividis idea on Challenge and cutting-edge risk MOS Was Hard to Foresee parametric amplifiers using a MOS have characterized Dr. Tsividis’s In the mid-seventies, it was diffi-

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cult to get the idea of mixed signal input?’ That student had re-invent- MOS ICs accepted. “When Yannis ed oscillators right on the spot.” began his graduate work around In order to reach undergradu- 1970,” said Dr. Paul Gray, an early ates, a professor “must be willing collaborator who is now Professor to find ways to explain things intu- Emeritus and Professor in the itively to the students – not just Graduate School, EECS, UC Berke- throw a bunch of equations at ley, in an email statement, “bipolar them,” Tsividis said. “The key is to was used for virtually all analog make the math interesting, by integrated circuits and most digital making clear why it’s useful. circuits, which were at low inte- Dumping the first circuits class on gration levels at the time. MOS was Kirchhoff Medal anybody in an EE department has used for memory and was just often had disastrous results in the beginning to be used for some Subsequent milestones, Tsividis motivation of students – I’m sure complex logic circuits.” CMOS was said, have been “the work my stu- our field has lost some of the best in its infancy. “It was not easy to dents and I did on switched-capac- minds because of this,” he said. see that MOS technology would itor circuit analysis and simulation; bring about the need to integrate our techniques for automatically Interdependence of both analog and digital on the tuned integrated continuous-time Research and Teaching same chip. This backdrop made filters; and our work related to pre- “Whenever I want to really under- MOS analog circuits a somewhat cision MOS modeling for analog stand an area different from mine, speculative proposition.” and mixed-signal design.” I ask to teach a class in it,” Tsividis Dr. Tsividis, who is an IEEE Fel- said. “This is how I learned about Career Breakthrough Was low, has received two best paper DSPs, communications, signals and The First Useful MOS awards from the IEEE Circuits and systems, and semiconductor Operational Amplifier Systems Society, as well as the devices. Only when I am forced to “Working with Paul Gray, Yannis IEEE-wide Baker best paper explain something carefully to oth- P. Tsividis developed and demon- award. ers, do I understand it fully.” As for strated the world’s first useful MOS his graduate students, he aims operational amplifier,” said Dave Master Teacher especially “to strike the right bal- Hodges, Professor of Engineering, The recipient in 2005 of the IEEE ance between helping them and EECS, UC Berkeley, via email. “It Undergraduate Teaching Award, challenging them to come up with was fundamental to the develop- Dr. Tsividis is unusual among their own solutions.” ment of mixed signal MOS inte- prominent researchers for his Shanthi Pavan, a recent Tsividis grated circuits, which provide vast- enthusiasm about teaching at this Ph.D., who is now an assistant ly higher levels of circuit integra- level. “I find it extremely reward- professor at the Indian Institute of tion than bipolar analog devices,” ing,” he said. “I have created a Technology in Madras, India, said the prior mainstream technology. first-year undergraduate class, in an email that he remembers Before CMOS was fully devel- ‘Introduction to Electrical Engi- especially Prof. Tsividis’s “infec- oped, the implementation of high neering,’ where we mix circuits tious enthusiasm,” “clarity,” “metic- gain op amps in NMOS was a real and electronics and attempt to ulous feedback,” and “virtually lim- challenge, Hodges said. “Yannis make students tinker. The idea is itless patience.” Dr. Cowan would came up with some circuit ideas to to make them excited and motivat- concur. “I don’t think people can overcome this” using NMOS-only ed about what they will be learn- decide to become great teachers,” technology. Yannis’s most lasting ing in their follow-up classes. Just he said. ”It has to come from the contribution to the usefulness of to show you how rewarding heart.” CMOS was his work on the adap- undergraduate teaching can be, let tation of weighted-capacitor A/D me tell you a story from that class. Yannis Tsividis received the Bach- conversion techniques to a special The class has a heavy lab compo- elor’s degree in electrical engi- kind of converter used for voice, nent. During an experiment on neering from the University of called a companding coder. He amplifiers, a student comes to me Minnesota in Minneapolis in 1972, and others first demonstrated this and says, ‘I see how, if I put a sig- and the MS and Ph.D. degrees, technique, which became very nal in, I get a signal out, and if I do also in electrical engineering, from widely used in telephone systems not put a signal in, I get nothing the University of California at around the world in the 1980’s and out. What would happen if I took Berkeley in 1973 and 1976. He is 1990’s.” the output signal and used it as the Charles Batchelor Memorial Pro-

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fessor of Electrical Engineering at These include techniques for fully log/RF MOS circuits, and analog- Columbia University in New York, integrated analog filters, which inspired digital signal processing and has taught at the University of have been used in very large vol- techniques, including continuous- California, Berkeley, MIT, and the ume products such as disc drives time digital filters which operate National Technical University of and consumer electronics; without aliasing, and digital filters Athens. switched-capacitor circuit theory which use internal companding. Dr. Tsividis began his career by and simulation, with the resulting A Fellow of the IEEE, Dr. Tsividis demonstrating the feasibility of software program Switcap widely is the recipient of the 1984 IEEE MOS mixed-signal circuits. In 1976, used for such systems in the early W.R.G. Baker Best Paper Award, at a time that MOS was considered days of MOS telecom ICs; com- the 1986 European Solid-State Cir- a digital integrated circuit technolo- panding analog filters; discrete- cuits Conference Best Paper Award, gy, he designed and built a fully time parametric circuits; mixed the 1998 IEEE Circuits and Systems integrated MOS operational ampli- analog-digital VLSI computation; Society Guillemin-Cauer Best Paper fier and demonstrated its use in a and precision MOS device model- Award, and the 2005 IEEE Under- PCM codec. These results were ing, with benchmarks incorporated graduate Teaching Award, and co- widely adopted by the industry in into IEEE standards for judging recipient of the 1987 IEEE Circuits the first massively produced mixed- compact models. His book, “Oper- and Systems Society Darlington signal MOS ICs. Together with his ation and Modeling of the MOS Best Paper Award and the 2003 students, he has since made many Transistor” is a standard reference IEEE International Solid-State Cir- other contributions at the device, in the field. His most recent cuits Conference L. Winner Out- circuit, system and simulation level. research effort involves 0.5 V ana- standing Paper Award.

IEEE Educational Innovation Award to Fiez TekBots® Named But Only Hint At Her Wide Ranging Talents

erri Fiez, Chair of EE at J. Allstot, Fiez’s graduate Oregon State Universi- advisor at Oregon State Uni- Tty, was presented with versity, predicted in 1988 the 2006 IEEE Educational that she would be a star. Activities Board Major Educa- Terri had only completed tional Innovation Award “for her masters when she was undergraduate engineering first presenting her research education innovation through report at ISSCC and Allstot creation and development of had recommended that Hel- Platforms for Learning ® and lums be sure to meet her its implementation in the elec- because she was the best trical and computer engineer- among the Allstot’s gradu- ing curriculum through the ate students. TekBots® program.” Profes- Allstot, now Chair of EE at (l to r) Moshe Kam, IEEE VP Educational Activities, sor Fiez developed the pro- Terri Fiez, and Bruce Eisenstein, Awards Committee University of Washington, gram at OSU in Corvalis, Ore- Chair Educational Activities, in New Orleans on 24 recalls that “From the time I gon over the last decade. November 2006 during the BoD Meeting Series when first met Terri, it was clear Dr. Jim Hellums, TI Fel- Fiez received the Major Educational Innovation that she was a ball of fire. low, who supervises funding Award of the IEEE Educational Activities Board. She has a great personality of research at academic insti- and is naturally comfortable tutions, visits the Oregon campus program in industry than at a Uni- in the academic environment, and has watched many of the Plat- versity because of the bureaucracy whether as a student, professor, or forms for Learning develop. TI and inertia. Some people who did- administrator. Terri is equally good funds a number of graduate n’t want to do it just don’t. Even as at strategic and tactical thinking.“ research projects managed by Fiez a Department Head at a University Hellums recalled that Allstot had today and has provided equipment one has to convince and cajole. It just proposed a robotics course at for the program. “It would be eas- is a Herculean effort.” OSU in the 90s and had found no ier to develop and launch a new Hellums remembers that David takers to expand the program

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about the time he left OSU for Ari- needed to incorporate the Platform ence that addresses what seemed zona. Fiez came on campus, took for Learning into their undergradu- to be missing in our own educa- the course and grew the TekBot ate curriculum. So, she presented tional experiences.” program, “got it done and made it the idea to Tektronix, Inc., and Nowadays, Hellums reports successful. Then she enlarged the garnered critical support by adopt- going to other schools and encour- scope to the Platforms for Learning, ing the ‘TekBots’ moniker for the aging them to pick up the Plat- which is all hers. It’s her vision and program. On the surface, such a forms for Learning program. “I try excitement that gets it developed.“ move might appear to be hype. to sell her idea.” The TekBots Plat- Allstot recalls, “I'm guessing here, However, it is far more significant form for Learning has been imple- but I don't think she got interested than that. Previous to Terri's mented in eight engineering cours- in robots until she became Head of arrival, the Freshman Robot es at OSU at the freshman through ECE at OSU. There was a freshman sequence culminated in a so-called senior levels and is used by five robot course sequence that had other institutions. been put in place at OSU one The concept includes two year prior to her arrival. It was “She had a good idea and she critical elements that aim to based on the freshman robot keep freshman and sopho- course that CMU ECE had found a way to describe it in mores involved and staying in developed a few years earlier, very simple, but powerful an EE program, Hellums but had some innovative addi- reports. “It deals with the tions including enrolling some terms, that everyone could challenges of the major being students from the local high understand.” too hard or too boring and schools. But, it was just a start. gets over that sophomore The next step in the thinking, Dave Allstot hump,” said Hellums. First as I understand it, was to deter- robot implementations often mine a way for those courses end up looking like the OSU to impact the entire undergraduate ‘Robot Rodeo’ that was open to the mascot – a Beaver with whiskers curriculum. One idea was to general public, especially prospec- that sense objects and back up involve seniors in capstone projects tive students and their families. move around them. By working that improved the robots and alter- That term was almost pejorative, in with applications of theory, sens- natives to them for the freshman my opinion, because it conjured ing, seeing, reacting and moving, sequence would be developed, as up the old ‘cow college’ image that the students realize what engineers well. Of course, this left the uncom- Oregon State had in the early days do in their career and see it can be fortable two-year robot-free gap when it was Oregon Agricultural fun. They also work in teams. Hel- between the Freshman and Senior College. It certainly didn't suggest lums recalls that there was nothing years. This is the kind of situation leading-edge high-technology edu- done in teams when he was a stu- where Terri shines. She conceived cation and research. With the sim- dent but industry always works in the “Platform for Learning” idea so ple twist of a phrase, TekBots, teams, often fairly large teams. So that the first-year robot experience Terri conveyed the message that it the students learn early on to find was continued throughout the was really leading-edge robot their place in a team. undergraduate years, and centered learning that had critical support Kartikeya Mayaram, professor at around a central theme that moti- from the local high-tech industry,” Oregon State University, and a vated upper level classes. This recalls Allstot. long time research collaborator meant adding capabilities to the Fiez emphasized that “this with Fiez, sees definite differences Freshman robots such as wireless award really recognizes an amaz- in the graduate students who have communications and control, etc. ing team. Over the last six years, come from the Learning Platforms As is typical of Terri, she had a we have had a core team of Don curriculum. “They are ready to hit good idea and she found a way to Heer (Education coordinator), the ground running. They are describe it in very simple, but pow- Roger Traylor (senior instructor), already very good at trouble shoot- erful terms that everyone could Gale Sumida (Research and Edu- ing. They have skills that enable understand. This is really important cation Support), Tom Thompson them to do independent research for encouraging younger kids to get (Math and Science education PhD and basically they are more involved in Electrical Engineering.” student and Philomath High resourceful in terms of knowing “This also presented an oppor- School teacher). Together, it has where to go and how to find infor- tunity for Terri to shine in another been a thrill working with the fac- mation. That’s a very valuable set way. To be successful, she knew ulty and students in our depart- of skills to come with to graduate that significant resources would be ment to create a unique experi- school.”

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Allstot points out that as a researcher “Terri has made signifi- erri S. Fiez (’82, M’85, SM’95, F’05) cant research contributions to received the B.S. and M.S. degrees in oversampled data converters and Telectrical engineering from the Uni- substrate noise analysis tech- versity of Idaho, Moscow, in 1984 and 1985 niques. She has made tremendous respectively. In 1990 she received the Ph.D. contributions to the high-technol- degree in electrical and computer engineer- ogy industry by advising many ing from Oregon State University, Corvallis. students who are prepared to ‘hit From 1985 to 1988 she worked at Hewlett- the ground running’ in their jobs. Packard Corporation, in Boise and Corvallis. She’s made important educational She was on the faculty at Washington State innovations, and her impact at University from 1990 to 1999. In 1999, she Oregon State cannot be overstat- Dr. Terri S. Fiez joined the Department of Electrical and ed. She has done a lot at many dif- Computer Engineering at OSU as Professor ferent levels.” and Department Head. She became Director of the School of Elec- Mayaram outlines how Fiez’s trical Engineering and Computer Science in 2003. program has permeated much of Dr. Fiez has participated extensively in IEEE activities including: the EE Curriculum. “Fiez is very IEEE International Solid-State Circuits Conference (2000-2006), involved with the Platforms for IEEE Custom Integrated Circuits Conference (1994-1998), IEEE Learning and works with a core Transactions on Circuits and Systems II Associate Editor (1995- team examining the curriculum. 1997), IEEE Journal of Solid-State Circuits Guest Editor (1997-1998) They look for critical points that and IEEE CAS Distinguished Lecturer (2002-2004). Fiez received the curriculum would benefit the National Science Foundation Young Investigator Award and from the platforms methodology, the IEEE Solid-State Circuit Predoctoral Fellowship. She was elect- and develop a straw man proposed Fellow of the IEEE in 2005 “for contributions to analog and al. So the core team does a lot of mixed-signal integrated circuits.” the ground work before they actually go and talk with the faculty. Then it’s an interactive her students she’s a great person her family and professional inter- process at that point. Professor and her students love her. She ests, more so than me and most of Roger Traylor who teaches the keeps in touch with most of her our colleagues.” freshman introductory course, is graduate students long after they Allstot asked Fiez, “Why do you already very involved in the Tek- have graduated and been work- obviously enjoy it so much?” Fiez Bot program. They have a good ing for ages. She advises them replied, “I can't think of a more idea of what’s going on in a class even at later stages in their satisfying career. The opportunities and they make a proposal for career,” Mayram notes. for creativity, working with stu- what makes sense in particular Allstot says, “Terri has it all. She dents to find their way, new tech- labs. When the team has thought is technically talented with a rare nologies that will change the it out that well, it’s a lot easier for gift for leadership. Mark down this world, learning and laughing. I the faculty to jump on board. The prediction: She will be a university have been very lucky all through- team takes on a lot of the detail president in the future. She is that out my career to work with won- work which can be a stumbling rare star who is approachable and derful people who are passionate block if each faculty member is likable by all, mainly, I think, about what they do. These include left on their own.” because it is always clear being my graduate advisors, Gary Maki “Terri is natural leader. She is around her that she really loves and Dave Allstot, and my graduate creative, full of new and innova- what she does. She has a great students, undergraduates, the fac- tive ideas. She is down to earth, sense of humor that she uses effec- ulty and staff in my School and values people and that makes a tively in her presentations and in Ron Adams, OSU Engineering very nice work environment. In person. Most important, she has a Dean. I can't think of a day not terms of research and mentoring life. She is well balanced between filled with laughter!”

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ixteen outstanding members of SSCS have accepted the Soci- SSCS DLs Tour the IEEE Far East Sety’s invitation to join its Distin- guished Lecturer Program. They are Shanghai and Beijing Chapters Host Inaugural Programs on 15-18 November Dennis Fischette Katherine Olstein, SSCS Administrator, [email protected] Ian Galton Ali Hajimiri The first SSCS Distinguished Lecturer Tour took place in the Far East Tadahiro Kuroda (IEEE Region 10) on 15-18 November, 2006, immediately after the A- John R. Long SSCC. The Shanghai and Beijing chapters each hosted a segment of the Akira Matsuzawa tour, which was initiated by SSCS DL Program Chair C.K. Ken Yang Sreedhar Natarajan and coordinated by Dr. Zhihua Wang, Chair of SSCS-Beijing. The pro- Bram Nauta grams included presentations by Drs. Tom Lee, Vojin Oklobdzija, Betty Clark T. C. Nguyen Prince and Marcel Pelgrom. Mehmet Soyuer “The SSCS Far East DL Tour in Shanghai was very successful,” said Mircea R. Stan Dr. Ting-Ao Tang, SSCS-Shanghai chair. “When we announced this Toshiaki Masuhara activity, we received more than 100 return receipts asking to attend the Ken Uchida workshop. On the afternoon of November 16th, 180 crowded the Albert J. P. Theuwissen room.” Roland Thewes The Society is planning a second Distinguished Lecturer tour in Ian Young Europe (IEEE Region 8) for the fall of 2007.

Each will serve a two-year term, from 1 January 2007 through 31 December 2008. “The new additions to the DL list increase our representation in Asia and Europe to better serve the chapters in their respective communities,” said C. K. Ken Yang, SSCS Education and DL Program Chair. “The list of DLs covers a In Beijing, an appreciative audience gathered to hear SSCS DL’s Marcel Pelgrom broad range of current topics. and Betty Prince (left) and Tom Lee and Vojin Oklobdzija (at right). Dr. Zhihua Wang (center) hosted the event, which took place at Tsinghua University. Local chapters can leverage this resource for their activities and technical meetings,” he said. The Society’s DL Roster now totals 33 lecturers. It is available at sscs.org/Chapters/dl.htm.

Dennis Fischette is a Senior Member of the Technical Staff at Advanced Micro Devices (AMD) in Sunnyvale, CA. In 1986 he graduated from Cornell University, Ithaca, NY, with B.S. degree in Engineer- At Fudan University, Shanghai (from left): Professors Anquan Jiang, Huihua ing Physics and then studied the Yu, Yinyin Lin, and Ting-AoTang, with Vojin Oklobdzija, C.K. Ken Yang, Tom History of Science at the Universi- Lee, Betty Prince, and Prof. Zhiliang Hong.

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ty of California, Berkeley. From circuits. He has served on a corpo- niques, and the Guest Editorial 1988 to 1991 he worked for Inte- rate Board of Directors, on several Board of Transactions of Institute grated CMOS Systems Sunnyvale corporate Technical Advisory of Electronics, Information and on device and circuit modeling. Boards, as the Editor-in-Chief of Communication Engineers of From 1991 to 1996 he worked for the IEEE Transactions on Circuits Japan (IEICE). Hal Computer Systems, Campbell, and Systems II: Analog and Digital Dr. Hajimiri was selected to the CA on clock synthesizers and cir- Signal Processing, as a member of top 100 innovators (TR100) list and cuit design automation. the IEEE Solid-State Circuits Soci- is a Fellow of Okawa Foundation. Before joining AMD, he worked ety Administrative Committee, as a He is the recipient of Caltech's for Chromatic Research, Sunnyvale member of the IEEE Circuits and Graduate Students Council Teach- on clock synthesizers, D/A circuits, Systems Society Board of Gover- ing and Mentoring award as well as and memories. His technical inter- nors, and as a member of the IEEE Associated Students of Caltech ests include PLL and DLL design, International Solid-State Circuits Undergraduate Excellence in clock-and-data recovery, circuit Conference Technical Program Teaching Award. He was the Gold analysis software, and high-speed Committee. medal winner of the National IO circuits. He was a member of Physics Competition and the the ISSCC Digital Program Commit- Ali Hajimiri received Bronze Medal winner of the 21st tee from 2001-2006 and created an the B.S. degree in International Physics Olympiad, online course on PLL Design for Electronics Engi- Groningen, Netherlands. He was a the IEEE Expert Now program in neering from the co-recipient of the IEEE JSSC Best 2005. In his spare time, Dennis is Sharif University of Paper Award of 2004, the Interna- an active jazz musician who Technology, and the tional Solid-State Circuits Confer- recently performed in China and M.S. and Ph.D. ence (ISSCC) Jack Kilby Outstand- Vietnam. degrees in electrical engineering ing Paper Award, two times co- from the Stanford University in recipient of CICC's best paper Ian Galton received 1996 and 1998, respectively. awards, and a three times winner of the Sc.B. degree He has had appointments with the IBM faculty partnership award from Brown Univer- Philips Semiconductors, Sun as well as National Science Founda- sity in 1984, and the Microsystems, and Lucent Tech- tion CAREER award. He is a M.S. and Ph.D. nologies (Bell Labs) in the past. In cofounder of Axiom Microdevices degrees from the 1998, he joined the Faculty of the Inc. and member of SSCS AdCom. California Institute California Institute of Technology, of Technology in 1989 and 1992, Pasadena, where he is a Professor Tadahiro Kuroda respectively, all in electrical engi- of Electrical Engineering and the (M’88-SM’00-F’06) neering. Since 1996 he has been a director of Microelectronics Labora- received the Ph.D. professor of electrical engineering tory. His research interests are high- degree in electrical at the University of California, San speed and RF integrated circuits. engineering from the Diego where he teaches and con- Dr. Hajimiri is the author of The University of Tokyo, ducts research in the field of Design of Low Noise Oscillators Tokyo, Japan, in 1999. mixed-signal integrated circuits (Boston, MA: Kluwer, 1999) and In 1982, he joined Toshiba Cor- and systems for communications. holds several U.S. and European poration, where he designed Prior to 1996 he was with UC patents. He is a member of the CMOS SRAMs, gate arrays and Irvine, and prior to 1989 he was Technical Program Committee of standard cells. From 1988 to 1990, with Acuson and Mead Data Cen- the International Solid-State Cir- he was a Visiting Scholar with the tral. His research involves the cuits Conference (ISSCC). He has University of California, Berkeley, invention, analysis, and integrated also served as an Associate Editor where he conducted research in circuit implementation of critical of the IEEE Journal of Solid-State the field of VLSI CAD. In 1990, he communication system blocks Circuits (JSSC), an Associate Editor was back to Toshiba, and engaged such as data converters, frequency of IEEE Transactions on Circuits in the research and development synthesizers, and clock recovery and Systems (TCAS): Part-II, a of BiCMOS ASICs, ECL gate arrays, systems. In addition to his aca- member of the Technical Program high-speed CMOS LSIs for demic research, he regularly con- Committees of the International telecommunications, and low- sults at several semiconductor Conference on Computer Aided power CMOS LSIs for multimedia companies and teaches industry- Design (ICCAD), Guest Editor of and mobile applications. He oriented short courses on the the IEEE Transactions on invented a Variable Threshold-volt- design of mixed-signal integrated Microwave Theory and Tech- age CMOS (VTCMOS) technology

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to control VTH through substrate ary 2002, where his current tion (Center) in 1993, General Man- bias, and applied it to a DCT core research interests include: low- ager, Semiconductor Manufacturing processor and a gate-array in 1995. power transceiver circuitry for Technology Center, Semiconductor He also developed a Variable Sup- highly-integrated radios and elec- & IC Div. in 1997, and then became ply-voltage scheme using an tronics design for high-speed data Senior Chief Engineer, Semiconduc- embedded DC-DC converter, and communications. Professor Long tor Group, Hitachi. In 2001, he employed it to a microprocessor currently serves on the program assumed his current position, Exec- core and an MPEG-4 chip for the committees of the ISSCC, ESSCIRC, utive Director, MIRAI Project, Asso- first time in the world in 1997. In IEEE-BCTM and GAAS 2004, and is ciation of Super-Advanced Electron- 2000, he moved to Keio University, a past Associate Editor of the IEEE ics Technologies (ASET).He is a Yokohama, Japan, where he has Journal of Solid-State Circuits. member of IEEE and IEICE, Japan. been a professor since 2002. He He became a fellow of IEEE in 1994 has been a Visiting Professor at Toshiaki Masuhara with the citation, ”For contribution Hiroshima University, Japan, and (S768-M’69-SM’90- in the invention and the develop- the University of California, Berke- Fellow’94), Associa- ment of NMOS circuits and high- ley. His research interests include tion of Super- speed CMOS memories”. He was low-power, high-speed CMOS Advanced Electron- the program co-chair and the chair design for wireless and wireline ics Technologies in 1992-, 1993-, and general co-chair communications, human computer (ASET), was born on and chair in 1996- and 1997-VLSI interactions, and ubiquitous elec- Mar. 5, 1945 in Osaka, Japan. He Circuit Symposium. He was an tronics. He has published more obtained B.S., M.S. and Ph.D. elected member of the Administra- than 200 technical publications, degrees in Electrical Engineering tive Committee, SSCS from 1998 to including 50 invited papers, and 18 from Kyoto University, Kyoto, Japan 2000.He received IEEE Solid-State books/chapters, and has filed in 1967, 1969 and in 1977, respec- Circuit Technical Field Award on his more than 100 patents. tively. From 1969 to 1974, he was a contribution to NMOS depletion- Dr. Kuroda served as the Gener- member of the technical staff, 3rd load circuits and the development al Chairman for the Symposium on and 7th Department at Hitachi Cen- of high speed CMOS memories in VLSI Circuits, the Vice Chairman tral Research Laboratory(CRL), 1990 and the IEEE third Millennium for ASP-DAC, sub-committee Kokubunji, Tokyo, Japan, where he Medal in 2000. He has received a chairs for A-SSCC, ICCAD, and worked on depletion-load NMOS Significant Invention Award, Japan SSDM, and program committee integrated circuits and on modeling in 1994, four Significant Invention members for the Symposium on of sub-threshold characteristics of Awards, Tokyo, Japan in 1984, 1985, VLSI Circuits, CICC, DAC, ASP- MOS transistors. From 1974 to 1975, 1988 and 1992, Significant Invention DAC, ISLPED, SSDM, ISQED, and he was a special student, Depart- Awards, Yamanashi, Japan in 1995 other international conferences. ment of Electrical Engineering and and Gumma, Japan in 1996. He is a recipient of the 2005 IEEE Computer Science, University of System LSI Award, the 2005 P&I California, Berkeley where he Akira Matsuzawa Patent of the Year Award, and the worked on double-diffused MOS received B.S., M.S., 2006 LSI IP Design Award. He is an transistors and a new CMOS and ph. D. degrees in IEEE Fellow and an IEEE SSCS Dis- process. In 1975, he returned to electronics engineer- tinguished Lecturer. Hitachi CRL and worked on new ing from Tohoku high speed CMOS SRAM. In 1987, University, Sendai, John R. Long re- he became department manager, Japan, in 1976, 1978, ceived the M.Eng. 7th Dept., Hitachi CRL, developing and 1997 respectively. In 1978, he and Ph.D. degrees memories, microprocessors, digital joined Matsushita Electric Industrial in Electronics from signal processors and high frequen- Co., Ltd. Since then, he has been Carleton University, cy silicon devices. He then became working on research and develop- Canada in 1992 and the manager of the 1st Dept. in ment of analog and Mixed Signal LSI 1996, respectively. 1990, performing research on high technologies; ultra-high speed He worked for 10 years at Bell- speed GaAs and bipolar ICs and ADCs, RF CMOS circuits, and digital Northern Research, Ottawa (now materials. From 1991 to 1993, he read-channel technologies for DVD Nortel Networks) designing ASICs was in Telecommunications Divi- systems. From 1997 to 2003, he was for Gbit/s fibre systems, and for 5 sion, Hitachi, where he was respon- a general manager in advanced LSI years as a faculty member at the sible for the design of telecom technology development center. On University of Toronto. He joined ICs.He became General Manager, April 2003, he joined Tokyo Institute the faculty at the TU Delft in Janu- Technology Development Opera- of Technology and he is a professor

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on physical electronics. Currently he been a leading advocate to inno- products based upon MEMS tech- is researching in mixed signal tech- vate and promote new memory nology, with an initial focus on the nologies. He has published 30 tech- technologies in the industry and is very vibrating micromechanical nical journal papers and 50 interna- working with many academic and resonators pioneered by his tional conference papers. He is co- industry organisations to promote research in past years. He served author of 9 books. He holds 34 reg- futuristic memory technologies. Mr. as Vice President and Acting Chief istered Japan patents and 65 US and Natarajan obtained his Master’s Technology Officer (CTO) of Dis- EPC patents. He received the IR100 degree in computer engineering cera from 2001 to mid-2002. award in 1983, the R&D100 award from University of Southwestern, In mid-2002, Prof. Nguyen went on and the Remarkable Invention Lafayette, LA. He is a IEEE Distin- leave from the University of Michigan award in 1994, and the ISSCC guished Lecturer for 2007-2008 and to join the Microsystems Technology evening panel award in 2003 and a Senior member for the Institute of Office (MTO) of DARPA in Arlington, 2005. He now serves SSCS AdCom Electrical and Electrical Engineers. Virginia, where he served as a Pro- members and he is an IEEE Fellow gram Manager in MEMS technology. since 2002. Clark T.-C. Nguyen At DARPA, from mid-2002 through received the B.S., 2005, Prof. Nguyen created and man- Sreedhar Natara- M.S., and Ph.D. aged a diverse set of programs that jan is currently serv- degrees from the included Microelectromechanical Sys- ing as the Founder University of Califor- tems (MEMS), Micro Power Genera- & CEO of Emerging nia at Berkeley in tion (MPG), Chip-Scale Atomic Clock Memory Technolo- 1989, 1991, and (CSAC), MEMS Exchange (MX), Harsh gies (EMT) Inc. He 1994, respectively, all in Electrical Environment Robust Micromechani- founded EMT in Engineering and Computer Sci- cal Technology (HERMIT), Micro Gas Dec 2004, which in a short period ences. In 1995, he joined the faculty Analyzers (MGA), Radio Isotope has grown to become a successful of the Department of Electrical Engi- Micropower Sources (RIMS), RF leading design services and memo- neering and Computer Science at MEMS Improvement (RFMIP), Navi- ry IP provider under his leadership. the University of Michigan, Ann gation-Grade Integrated Micro Gyro- Prior to EMT, his industry experi- Arbor, to which he has very recent- scopes (NGIMG), and Micro Cryo- ence comes from working at MoSys, ly returned after a 3.5 year leave in genic Coolers (MCC). Texas Instruments and Paradigm Washington, DC, where he served Technologies in the area of SRAM, as the MEMS Program Manager in Bram Nauta was DRAM, Memory Compilers and SOI. the Microsystems Technology Office born in Hengelo, Mr. Natarajan serves on the Adviso- (MTO) of DARPA. His technical The Netherlands, in ry Board of Diablo Technologies interests at Michigan focus on micro 1964. In 1987 he Inc, Solido Design Automation and electromechanical systems (MEMS) received the M.Sc. HS Memory Inc. He also serves on and include integrated vibrating degree (cum laude) various international conference micromechanical signal processors in Electrical Engi- technical committees like ISSCC, and sensors, merged circuit/micro- neering from the University of CICC, VLSI, ESSCIRC, ISLPED, SOC mechanical technologies, RF com- Twente, Enschede, The Nether- and VLSI Symposium. He co- munication architectures, and inte- lands. In 1991 he received the authored the book “SOI Design: grated circuit design and technolo- Ph.D. degree from the same uni- Analog, Memory and Digital gy. Prof. Nguyen and his students at versity on the subject of analog Design” – Dec 2001, Kluwer Acade- Michigan have garnered numerous CMOS filters for very high frequen- mic Publishers and is also the recip- Best Paper Awards at prestigious cies. In 1991 he joined the Mixed- ient of the IEEE Circuits and Systems conferences, including the 1998 and Signal Circuits and Systems Depart- Outstanding Service Award'01. 2003 IEEE Int. Electron Devices ment of Philips Research, Eind- Dr. Natarajan was named among Meetings, the 2004 IEEE Ultrasonics hoven, The Netherlands, where he ‘Top 40 under 40’ individuals by Symposium, the 2004 DARPA Tech worked on high speed AD con- the Ottawa Business Journal in Conference, the 2004 IEEE Custom verters. From 1994 he led a 2005. This awards program honors Integrated Circuits Conference, the research group in the same depart- individuals throughout the Ottawa 2005 IEEE Int. Solid-State Circuits ment, working on analog key business community that embody Conference, and the 2005 IEEE Fre- modules. In 1998 he returned to the region’s entrepreneurial spirit quency Control Symposium. the University of Twente, as full and business acumen, while at the In 2001, Prof. Nguyen founded professor heading the IC Design same time balancing community Discera, Inc., a company aimed at group in the MESA+ Research and charitable involvement. He has commercializing communication Institute and department of Electri-

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cal Engineering. His current Research Center. Dr. Soyuer has best paper awards at GLSVLSI research interest is analog CMOS authored numerous papers in the 2006, ISCA 2003 and SHAMAN circuits for transceivers. He is also areas of analog, mixed-signal, RF, 2002. He is the chair of the VLSI part-time consultant in industry microwave, and nonlinear elec- Systems and Applications Techni- and in 2001 he co-founded Chip tronic circuit design, and he is an cal Committee (VSA-TC) of IEEE Design Works. His Ph.D. thesis inventor and co-inventor of eight CAS, was general chair for ISLPED was published as a book: Analog U.S. patents. Since 1997, he has 2006, technical program chair for CMOS Filters for Very High Fre- been a technical program commit- ISLPED 2005, general chair for quencies, Kluwer, Boston, MA, tee member of the International GLSVLSI 2003, and has been on 1993. He holds 8 patents in circuit Solid-State Circuits Conference technical committees for numer- design and he received the "Shell (ISSCC). He was an Associate Edi- ous conferences. Study Tour Award" for his Ph.D. tor of the IEEE Journal of Solid- He has been an Associate Editor Work. From 1997-1999 he served State Circuits from 1998 through for the IEEE Transactions on Cir- as Associate Editor of IEEE Trans- 2000, and was one of the Guest cuits and Systems Systems since actions on Circuits and Systems -II; Editors for the December 2003 2004 and for the IEEE Transactions Analog and Digital Signal Process- Special ISSCC Issue. Dr. Soyuer on VLSI Systems in 2001-2003. He ing, and in 1998 he served as chaired the Analog, MEMS and has also been a Guest Editor for Guest Editor for IEEE Journal of Mixed-Signal Electronics Commit- the IEEE Computer special issue Solid-State Circuits. In 2001 he tee of the International Sympo- on Power-Aware Computing in became Associate Editor for IEEE sium on Low Power Electronics December 2003 and a Distin- Journal of Solid –State Circuits. and Design (ISLPED) in 2001. He guished Lecturer for the IEEE Cir- was also a technical program com- cuits and Systems Society for 2004- Mehmet Soyuer mittee member of the Topical 2005. Prof. Stan is a senior member received the B.S. Meeting on Silicon Monolithic Inte- of the IEEE, a member of ACM, and M.S. degrees in grated Circuits in RF Systems IET, and also of Eta Kappa Nu, Phi electrical engineer- (SiRF) in 2004 and 2006. Dr. Kappa Phi and Sigma Xi. ing from the Middle Soyuer is a senior member of IEEE. East Technical Uni- Albert J.P. Theuwis- versity, Ankara, Mircea R. Stan sen was born in Turkey, in 1976 and 1978. He received the Ph.D. Maaseik, Belgium on received the Ph.D. degree in elec- and M.S. degrees in December 20, 1954. trical engineering from the Univer- Electrical and Com- He received the sity of California at Berkeley in puter Engineering degree in electrical 1988, subsequently joining IBM at from the University engineering from the Thomas J. Watson Research of Massachusetts at the K.U. Leuven, Belgium in 1977. Center, Yorktown Heights, NY as a Amherst and the Diploma in Elec- His thesis work was based on the Research Staff Member. His work tronics and Communications from development of supporting hard- has involved high-frequency Politehnica University in Bucharest, ware around a linear CCD image mixed-signal integrated circuit Romania. sensor. designs, in particular monolithic Since 1996 he has been with the From 1977 to 1983, his work at phase-locked-loop designs for Department of Electrical and Com- the ESAT-laboratory of the K.U. clock and data recovery, clock puter Engineering at the Universi- Leuven focused on semiconductor multiplication, and frequency syn- ty of Virginia, where he is now an technology for linear CCD image thesis using silicon and SiGe tech- associate professor. Prof. Stan is sensors. He received the Ph.D. nologies. At IBM Thomas J. Watson teaching and doing research in the degree in electrical engineering in Research Center, Dr. Soyuer man- areas of high-performance low- 1983. His dissertation was on the aged the Mixed-Signal Communi- power VLSI, temperature-aware implementation of transparent cations Integrated-Circuit Design circuits and architecture, embed- conductive layers as gate material group from 1997 to 2000. He was ded systems, and nanoelectronics. in the CCD technology. the Senior Manager of the Commu- He has more than eight years of In 1983, he joined the Micro- nication Circuits and Systems industrial experience, has been a Circuits Division of the Philips Department from 2000 to 2006. In visiting faculty at UC Berkeley in Research Laboratories in Eind- March 2006, he has been promot- 2004-2005, at IBM in 2000, and at hoven, the Netherlands as a mem- ed to the position of Department Intel in 2002 and 1999. He has ber of the scientific staff. Since Group Manager, Communication received the NSF CAREER award that time he was involved in Technologies, at Thomas J. Watson in 1997 and was a co-author on research in the field of solid-state

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image sensing, which resulted in and coaches PhD students in their CMOS circuit design. Since 2006, the project leadership of respec- research on CMOS image sensors. he is heading a department devel- tively SDTV- and HDTV-imagers. In April 2002, he joined DALSA oping DRAM Core Circuitry at In 1991 he became Department Corp. to act as the company’s Qimonda. Head of the division Imaging Chief Technology Officer. In Sep- He has authored or co-authored Devices, including CCD as well tember 2004 he retired as CTO and some 120 publications including as CMOS solid-state imaging became Chief Scientist of DALSA book chapters, tutorials, invited activities. Semiconductors. This shift allows papers, etc., and he gave lectures He is author or coauthor of him to focus more on the field of and courses at universities. He many technical papers in the solid- training and teaching solid-state served as a member of the techni- state imaging field and issued sev- image sensor technology. cal program committees of the eral patents. In 1988, 1989, 1995 In 2005 he founded ETETIS International Reliability Physics and 1996 he was a member of the (European Technical Expert Team Symposium (IRPS), and of the International Electron Devices on Image Sensors), a non-profit European Symposium on Reliabili- Meeting paper selection commit- organization to promote European ty of Electron Devices, Failure tee. He was co-editor of the IEEE R&D activities in the field of solid- Physics and Analysis (ESREF). He Transactions on Electron Devices state image sensors. is a member of the technical pro- special issues on Solid-State Image He is member of editorial board gram committees of the Interna- Sensors, May 1991, October 1997 of the magazine “Photonics Spec- tional Solid-State Circuits Confer- and January 2003, and of IEEE tra”, an IEEE Fellow and member ence (ISSCC), of the International Micro special issue on Digital of SPIE. Electron Device Meeting (IEDM), Imaging, Nov./Dec. 1998. and of the European Solid State He acted as general chairman of Roland Thewes was Device Research Conference (ESS- the IEEE International Workshop on born in Marl, Ger- DERC). Moreover, in 2004, he Charge-Coupled Devices and many, in 1962. He joined the IEEE EDS VLSI Technol- Advanced Image Sensors in 1997 received the Dipl.- ogy and Circuits Committee. and in 2003. He is member of the Ing. degree and the Dr. Thewes is a member of the Steering Committee of the afore- Dr.-Ing. degree in IEEE and of the German Associa- mentioned workshop and founder Electrical Engineer- tion of Electrical Engineers (VDE). of the Walter Kosonocky Award, ing from the University of Dort- which highlights the best paper in mund, Dortmund, Germany, in Ken Uchida was the field of solid-state image sensors. 1990 and 1995, respectively. From born in Cambridge, During several years he was a 1990-1995, he worked in a cooper- MA in 1971. He member of the technical commit- ative program between the Siemens received B.S. degree tee of the European Solid-State Research Laboratories in Munich in physics, M.S. and Device Research Conference and and the University of Dortmund in Ph.D. degrees in of the European Solid-State Circuits the field of hot-carrier degradation applied physics all Conference. in analog CMOS circuits. from the University of Tokyo, Since 1999 he is a member of Since 1994 he was with the Tokyo, Japan, in 1993, 1995, and the technical committee of the Research Laboratories of Siemens 2002, respectively. In 1995, he International Solid-State Circuits AG and Infineon Technologies, joined the Research and Develop- Conference. For the same confer- where he was active in the design ment Center, Toshiba Corporation, ence he acted as secretary, vice- of non-volatile memories and in Kawasaki, Japan. He has studied chair and chair in the European the field of reliability and yield of carrier transport properties in ISSCC Committee and he is a mem- analog CMOS circuits. From 1997- nano-scaled devices such as Sin- ber of the overall ISSCC Executive 1999, he managed projects in the gle-Electron Devices, Schottky Committee. fields of design for manufacturabil- source/drain MOSFETs, Ultrathin- In 1995, he authored a textbook ity, reliability, analog device per- body SOI MOSFETs, Strained Silicon “Solid-State Imaging with Charge-Cou- formance, and analog circuit MOSFETs, and Carbon Nanotube pled Devices”. In 1998 he became an design. From 2000-2005, he was Transistors. He developed the IEEE Distinguished Lecturer. responsible for the Lab on Mixed- physics-based compact model of In March 2001, he became part- Signal Circuits of Corporate single-electron transistors and the time professor at the Delft Univer- Research of Infineon Technologies design scheme of single-electron sity of Technology, the Nether- focusing on CMOS-based bio-sen- logic circuits. He investigated the lands. At this University he teach- sors, device physics-related circuit physical mechanisms of mobility es courses in solid-state imaging design, and advanced analog enhancement in uniaxial stressed

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MOSFETs and clarified the impor- ty of Melbourne. He Loops for microprocessor clock- tance of the effective mass change. received the Ph.D. in ing and high speed I/O and In addition, he experimentally Electrical Engineer- mixed-signal RF CMOS circuits demonstrated the effectiveness of ing from the Univer- for communications. subband structure engineering in sity of California, He was a member of the Pro- ultrathin-body SOI MOSFETs. Dr. Berkeley, in 1978, gram Committee for the Sympo- Uchida is a member of the Japan where he was one of sium on VLSI Circuits from 1991 to Society of Applied Physics and IEEE the pioneers of the switched capaci- 1996, serving as the Program Com- Electron Devices Society. He won tor filter in MOS technology. mittee Co-Chair/Chairman in 1995 the 2003 IEEE EDS Paul Rappaport In 1983 he joined the Technol- and 1996, and the Symposium Co- Award for his work on single-elec- ogy Development group at Intel Chair/Chairman in 1997/1998. He tron devices and 2005 Young Scien- Corporation, where he is cur- currently serves on the Executive tist Award from Ministry of Educa- rently an Intel Senior Fellow and Committee of the VLSI Symposia. tion, Culture, Sports, Science and Director of Advanced Circuits Since 1992 he has been a member Technology of Japan. and Technology Integration. His of the ISSCC Technical Program technical contributions have Committee, serving as the Digital Ian Young was born in Melbourne, been recognized in the design of Subcommittee Chairman from Australia. He received the BSEE in DRAMs and SRAMs, process 1997 through 2003, Technical Pro- 1972, and the M. Eng. Science in technology development and gram Committee Vice-chair in 2004 1975, specialized in Microwave microprocessor implementations, and Chair in 2005. Dr Young is an Communications, from the Universi- the design of Phase Locked IEEE Fellow.

Congratulations New Senior Members 22 Elected in November

Alexandre Acovic Switzerland Section Antonio Leischner Eastern Idaho Section David Alexander Albuquerque Section Carl Lemonds Central Texas Section John Carpenter Melbourne Section Xiaopeng Li Dallas Section Gian-Franco Dalla Betta Italy Section Zhongmin Li Eastern Idaho Section Mark Durlam Phoenix Section Bjarne Malsnes Norway Section Luca Fasoli Santa Clara Valley Section Vasilis Papanikolaou Toronto Section Alkiviades Hatzopoulos Greece Section Luis Serrano Spain Section Stephen Horne Central Texas Section Chun-Meng Su Hong Kong Section William Hue Oregon Section Svein Tunheim Norway Section Tom Kjode Norway Section Walter Vollenweider Switzerland Section Chang-Ho Lee Atlanta Section Ming Zang Twin Cities Section TOOLS: How to Write Readable Reports and Winning Proposals Part 2: Structure Your Reports to Please Your Reader By Peter and Cheryl Reimold, www.allaboutcommunication.com his article is reprinted from can you shape weeks of work into a the May/June 2002 issue of single document? The key is to aim Tthe IEEE Professional Com- for ease of reading. The structure of munication Society Newsletter, vol. your report should enable readers to 46, Number 3, pages 15-16 with the get what they want as quickly and permission of the authors and Rudy completely as possible. Here are two Joenk, PCS newsletter editor. ways to do that. One of the most daunting tasks of The scientific format is good if report writing is organization. How you are addressing peers who may

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PEOPLE

want to evaluate the validity of your them only that. sure the dog is outside the approach. It follows a logical pro- The approach/method opens kitchen. gression, from an overview (summa- with a summary of the key points of The appendixes consist of materi- ry) to the background (introduc- the method—points that could al that is not critical for understand- tion), to your method, to a discus- interest both management and tech- ing your report but might be useful sion of anything interesting that nical readers. The rest of the section in the future. Make sure that each occurred, and then to your results. tells your technical readers how you page has enough information on it The conclusions and recommenda- proceeded. to make it self-explanatory. tions grow directly out of the results. The discussion requires informa- Finally, here are two points that The management format uses tive subheadings. Use a clear sub- apply to all sections: the same categories but rearranges head for each topic you explore. 1. In each section and subsection, them to allow general management Open each topic with a summary move from the most to the readers to get the information they paragraph that states your main least important information, want in the beginning, without hav- message. Then consider which read- unless some other logical ing to read detailed sections. ers will be most interested in that scheme (e.g., chronology, left You may not always need a sec- topic. Note what questions they to right, top to bottom, causal tion on method; this depends on the would have and try to answer them. sequence) clearly makes the nature of your work and your read- If you have more to tell, state it after section easier to understand. ership. You may decide to give a you have answered their questions, 2. Once you introduce several more specific title to the discussion or put it in an appendix. items in a certain order, stick to section if it covers only one topic. The results state simply what that order in the rest of the Otherwise, these sections work for you found. It is best to present them report. most technical reports. as a bulleted list. (This stops you Follow these simple rules, and The summary provides the from adding long interpretations, your readers will thank you for essence of your report, preferably in which don’t belong here.) For making your report easily accessi- nontechnical terms. It should give example: ble and readable. general answers to all your readers’ • The five-pound roast was no Cheryl and Peter Reimold have most urgent questions, but the pri- longer on the counter. been teaching communication mary reader here is usually the • The dog was under the table, skills to engineers, scientists, and executive. Think broad brush looking unwell. business people for 20 years. Their strokes. A good outline for the The conclusions are your deduc- latest book, “the Short Road to Great opening summary is the PAW: Pur- tions from the results. They, too, Presentations” (Wiley, 2003), is pose, Achievement, What Next. For work well as a bulleted list. They available in bookstores and from a discussion of the PAW, see the first should grow clearly out of the Amazon.com. Their consulting column in this series (May/June results. For example: firm, PERC Communications (1 2002 Newsletter, p. 10). • The dog ate five pounds of raw 914 725 1024), [email protected]), The introduction explains what beef. offers business consulting and writ- led to the work you did. It is an The recommendations state what ing services as well as customized amplification of the purpose stated to do next. They should grow direct- in-house courses on writing, pres- in the summary. To keep your intro- ly out of your conclusions. For entation skills, and on-the-job com- duction brief and interesting, consid- example: munication skills. Visit their Web er your readers. How much back- • When preparing roast beef, site at www.allaboutcommunica- ground do they want and need? Tell close the kitchen door, making tion.com.”

68 IEEE SSCS NEWSLETTER Winter 2007 sscs_NL0107 1/8/07 9:58 AM Page 69

CHAPTERS SSCS Awards $35,000 in Chapter Subsides Katherine Olstein, SSCS Administrator, [email protected]

SCS has awarded a record speakers. The Bangalore chapter tions and Computer Science” $35,603.96 in subsidies to a subsidy will also help to fund the (TCSET) conference and the Inter- Srecord 30 chapters for 2007- 10th VLSI Design and Test Work- national Seminar/Workshop on 2008. The maximum allotment was shop in cooperation with the VLSI Direct and Inverse Problems of doubled, in an AdCom vote last Society of India on 10-13 August. Electromagnetic and Acoustic Wave August, from $1000 to $2000 for single West Ukraine is planning Theory (DIPED). The International and new joint chapters, and from $500 “Pidstryhach Readings,” a Regional Conference on Microelectronics to $1000 for established joint chapters. Conference of Students and Young (MIEL), sponsored by SSCS/ED-Ser- Chapter subsidy awards are used Scientists, and will also use SSCS bia Montenegro with the aid of SSCS primarily to fund distinguished lec- subsidy funds to sponsor awards at monies, annually draws an audi- turer seminars, chapter-level con- the student scientific congress of ence from over 30 countries in the ferences and short courses and the Institute of Telecommunica- spring. In Germany, two Multi Pro- workshops. They also underwrite tions, Radioelectronics, and Elec- ject Chip Workshops are held every membership promotion, network- tronic Engineering. SSCS-Sofia will year with the help of subsidy funds. ing, and web development. conduct a competition in electron- Next year, the Novosibirsk Joint The chief events to be subsi- ics design for high school students chapter will cosponsor the annual dized next year exemplify the and support student activities at conference of the Russian A.S. range of benefits that chapters pro- the Technical University of Varna. Popov Radio Engineering Society. vide to local and regional IC pro- In Novosibirsk, the SSCS student fessionals and students. chapter and Novosibirsk-SSCS/EDS Chapter-Sponsored Techni- together sponsor the annual Inter- cal Meetings Educate Local Chapter Workshops Foster national Workshop and Tutorial on Communities Local Business Initiatives Electron Devices and materials Vancouver will use its first-ever In Shanghai, many IC design com- (EDM). This event will take place subsidy award for five talks featur- panies have sprung up, especially in for the eighth time in July. ing three local and two invited SOC design and manufacturing. The Society’s new chapter in speakers. The chapter hopes to Therefore, the chapter is planning Pavia, Italy will use the SSCS sub- double its membership during 2007 two seminars for spring, 2007 to sidy to fund two two-day short on the basis of these meetings and introduce new methodologies to the courses in April and June on an upgraded website. The new IC community and to strengthen the switched-capacitor filters, MEMS Phoenix chapter is planning a local relationship between academia and technology, data converters and workshop in mid-February. SSCS- industry. As many as eighty atten- microsensor interfaces for telecom, Ireland’s subsidy will contribute dees are expected at each event. sigma-delta converters, and CMOS towards the IEEE International About 30 engineers from indus- off-chip drivers. The courses will be Analog VLSI Workshop in Cork. try and academia will come togeth- approved for Ph.D. students by the SSCS-Hong Kong will present a er in a two-day workshop spon- Microelectronics PhD Course Advi- “Symposium on Solid-State Devices sored by the Finland/ Estonia chap- sory Board at the University of and Novel Techniques for Biosens- ter on 19-20 August, 2007. More Pavia, and will also serve students ing Applications” next April. And information about this event, the from the Polytechnic University of the Novosibirsk Joint chapter will seventh in a series, may be found Milan and the University of Genova sponsor the first Russian IEEE Sem- at http://isc.dcc.ttu.ee/ws.htm. and Parma, among other schools. inar on Solid-State Sensors, Actua- tors and Microsystems (MicroSys Chapter Seminars Enhance Chapter-Sponsored Annual ‘2007) in December. It will also Student Skills Conferences Promote host a seminar on Nanotechnology SSCS-Bangalore, a chapter with Regional Advancements in Electronics and participate in an 125 members, will devote SSCS Sponsored by SSCS-Central Ukraine All-Russia Chapter Chairs Congress. subsidy funds to two one-day every year and aided by SSCS sub- More information about the SSCS workshops for undergraduate and sidy funds, the Crimean Microwave Chapter Subsidies may be found at: graduate students on advances and Conference (CriMiCo) regularly sscs.org/Chapters/subsidy.htm. issues in devices and circuits. Each attracts 350 attendees in the fall. Information about the SSCS Extra will take place at a local engineer- The West Ukraine chapter organizes Chapter Subsidy Program may be ing college and involve faculty and the annual “Modern Problems of found at: sscs.org/Chapters/sub- students in addition to invited Radio Engineering, Telecommunica- sidy-extra.htm.

Winter 2007 IEEE SSCS NEWSLETTER 69 sscs_NL0107 1/8/07 9:58 AM Page 70

CHAPTERS Far East Chapters Meet in Hangzhou, China Inaugural SSCS Regional Meeting on 15 November, 2006 Jan Van der Spiegel, Chapters Committee Chair, [email protected]

he first SSCS regional chap- Seoul Chapter (J. Chung and S-I. Lim) important role chapters play in bring- ters’ meeting was held in con- Singapore Chapter (Y-P. Xu) ing educational and professional Tjunction with the A-SSCC in Shanghai (T.A. Tang) and benefits to the local membership. Hangzhou, China on 15 November, Taipei Chapter (H-S. Lin). Professor Van der Spiegel gave an 2006. The goal of the Far East meet- Several SSCS Society representa- overview of SSCS Chapter growth ing in IEEE Region 10 was to bring tives attended: R. Jaeger (President and activities in Region 10. Professor together chapter officers, society of the SSCS), Jan Van der Spiegel Ken Yang talked about the Distin- representatives and regional leaders (Chapters Chair), Ken Yang (Chair guished Lecture Program and the DL to share experiences about best of the Education Committee) and tour in Region 10 immediately fol- chapter practices, to provide infor- Anne O’Neill (Executive Director). lowing the A-SSCC, on 15-18 Novem- mation on chapter support services, In addition, three Far East digni- ber. Anne O’Neill reviewed adminis- and to stimulate further chapter taries were present: Nicky Lu (A- trative aspects, educational opportu- development in Asia. The meeting SSCC Steering committee and nities and financial aspects of chap- was highly successful and resulted Technical Program Co-Chair), C. ters. During the remainder of the in a good dialogue among chapter K. Chang (A-SSCC Steering Com- meeting, chapter representatives and society representatives. mittee), and X. Yan (Dean, EE Col- gave brief overviews of their respec- Professor Zhihua Wang of the lege of Zhenjian University). Also, tive chapter activities. The meeting Beijing Chapter hosted the event two Distinguished Lecturers partic- concluded with a boat tour on the and made the local arrangements ipated: Betty Prince and Vojin beautiful West Lake, followed by a which ensured a very smooth and Oklobdzija. traditional Chinese dinner. well run meeting. Six chapters After the luncheon, Professor R. The Society plans to hold a sec- were represented: Jaeger welcomed all participants, ond regional chapter meeting in Beijing Chapter (Prof. Z. Wang) congratulated the chapter chairs on September, 2007 in conjunction Hong Kong Chapter (K-P. Pun) an outstanding job and stressed the with ESSCIRC.

From left, Kong-Pang Pun of The Chinese University of Hong Kong, Voijin Oklobdzija of University of Sydney , Betty Prince of Memory Strategies International, C.K. Ken Yang of UCLA, Yong Ping Xu of the National University of Singapore, Zhihua Wang of Tsinghua University, Ting-Ao Tang of Fudan University, Richard C. Jaeger of Auburn University, Anne O’Neill of IEEE SSCS, Andy Jinyong Chung of Puhang University of Science and Technology, Jan Van der Spiegel of Uni- versity of Pennsyvlania, C. K. Wang of National Taiwan University, Nicky Lu, of Etron Technology, Shin Il Lim of Korea’s Ministry of Commerce, Industry and Energy, and Hsung- Hsien Lin of National Taiwan University.

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V. Oklobdzija Offers IEEE DL Talk and Keynote Address to PEECS Symposium in Western Australia Microprocessors in the Past and Future Explored at November Meetings By Adam Osseiran, Edith Cowan University, [email protected]

rofessor Vojin Oklobdzija, an IEEE Fellow and Distin- Pguished Lecturer of the IEEE Solid-State Circuits Society gave a seminar entitled “Future of Micro- processors: Retrospective and Challenges” to the electronic and computer communities in West- ern Australia on Monday, 6 November, 2006. The venue was the Innovation Centre WA at the Technology Park in Bentley. Twenty five researchers and professionals from Perth attended the From left, Dr. Vojin Oklobdzija, Dr. Adam Ossieran, and Dr. Lance Fung. lecture. In his talk, Professor Oklobdz- continued outside at a reception in growth. He then outlined major ija presented a retrospective of his honor provided by the IEEE milestones and achievements in modern microprocessor develop- local section. computer development and con- ment. He addressed advances in On the next day, Professor tinued by showing trends and enabling technology that have Oklobdzija gave the keynote sharing his view on where growth brought unprecedented growth address "Directions in Computer and expansion in this area may be and gave a perspective for future Engineering" at the 7th Post Grad- expected. At the end, he offered development. The features which uate Electrical Engineering Com- some recommendations for the have enabled the development puter Symposium (PEECS) for university computer engineering of modern microprocessors, researchers and postgraduates programs. guiding principles and contribu- from the four Western Australian The visit of Professor Oklobdz- tions made by modern micro- Universities. The Symposium was ija to Western Australia conclud- processor architecture were dis- organized by Associate Professor ed with a discussion about a pro- cussed, as well as the move into Lance Fung, who is the IEEE West- posal to initiate a new joint IEEE super-scalars with respect to per- ern Australia Section Chair. More chapter of SSCS and EDS, which formance and implementation than 100 participants filled the should become two distinct difficulties. auditorium. chapters later. Current develop- Professor Oklobdzija then Professor Oklobdzija put the ments in the research communi- addressed the one billion transistor computer engineering discipline ties in Western Australia in the challenge and the impact of the into a historical perspective and fields of microelectronics, pho- computer entry into consumer showed how computers have tonics, solid states and electron market, representing new poten- seen an unprecedented expansion devices with new nanotechnolo- tials and new challenges. An inter- since the first electronic comput- gy and nanomaterial for applica- esting discussion between Profes- ers were built some 50 years ago. tions such as military, medical, sor Oklobdzija and the partici- He later explained how comput- and general sensing applications pants, and among the participants ers are playing a major part in our justify the establishment of a new themselves, followed the talk and lives and are fuelling economic IEEE chapter.

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CHAPTERS Denver Hosts Technical Seminars on Cutting-Edge CMOS Technology and High-Speed Test Alvin Loke, Denver Chapter Chair, [email protected], Bob Barnes, Denver Chapter Vice Chair & Treasurer, [email protected], Tin Tin Wee, Denver Chapter Secretary & Webmaster, [email protected]

n the past year, the Denver device mismatch and allow for SSCS Chapter hosted eight ultra-low voltage operation. Prof. Imonthly seminars, including Boris Murmann was the next four by SSCS Distinguished Lectur- speaker, coming from Stanford ers. These talks spanned a variety University to discuss the impor- of exciting developments in IC tance of digital techniques to com- design, cutting-edge CMOS tech- pensate for analog limitations, nology, and high-speed test. such as nonlinearity and variabili- In the first seminar of 2006, Dr. ty, in sub-100nm CMOS. Victor Chan of IBM gave a very In August, Prof. Behzad Razavi informative overview of state-of- visited from the University of Cali- the-art strain and substrate engi- fornia at Los Angeles. His much neering techniques to enhance anticipated seminar covered some channel mobility in bulk and SOI Alvin Loke, Denver Chapter Chair, exciting new developments on the CMOS. In February, Dr. Osvaldo presented an award of appreciation 60GHz RF CMOS transceiver front to Dr. Pelgrom. Buccafusca of Avago Technolo- and discussed design and modeling gies, who is also the Chair of the at the Chapter’s website. challenges in that domain. Not sur- IEEE Centennial Subsection that Dr. Marcel Pelgrom of Philips prisingly, Prof. Razavi’s renowned covers northern Colorado and Research visited Fort Collins in authorship drew quite a trail for southern Wyoming, described the May to deliver our first Distin- autographs. Thanks to members-at- challenges and implementation of guished Lecture of the year. A pio- large Herman Pang and Michael a very high-speed optical sampling neering expert on transistor vari- Gildorf of Avago Technologies for oscilloscope for characterization of ability, he delivered an insightful making possible our first ever semi- optical serial links. Adam Healey talk on the analog challenges asso- nar recorded on DVD. The DVD of Agere Systems, Chair of the ciated with nanometer CMOS. will be available to chapters, upon IEEE 802.3ap Standards Commit- Given its relevant nature, Dr. Pel- request. tee, built on this theme with a dis- grom's seminar drew a chapter Following a social event in cussion of 10 Gigabit Ethernet over record attendance of 120! November, the year ended with a backplane interconnects. This The next DL seminar was given ninth lecture by Sam Naffziger of topic is of significant interest to the by Dr. Kiyoo Itoh of Hitachi Cen- Advanced Micro Devices, who many Fort Collins IC designers tral Research Laboratory, who spoke on high-performance proces- dealing with high-speed electrical spoke about ultra-low voltage sors in a power-limited world. Fort data links. Stefan Rusu presented nano-scale embedded RAMs. Dr. the next talk on Intel’s Dual-Core Itoh emphasized the importance of Xeon® Processor. Abstracts and fully-depleted SOI technology as slides for all lectures are available an enabling solution to overcome

The Society distributed this DVD as a technical treat to attendees at the The Distinguished Lecturer seminar by Dr. Marcel Pelgrom attracted an audi- Society’s Far East Chapters Luncheon ence of 120 at Fort Collins, CO on 11 May 2006. and Meeting in November.

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Herman Pang (far left) and Mikail Gilsdor (second from right, second row) video taped Dr. Razavi’s talk on 1 August, 2006. Dr. Razavi is eighth from right, front row. A. Loke and Tin Tin Wee, Chapter Secretary and Webmaster, are to his right.

Collins has quickly become a having been overwhelmed by his tant places and undoubtedly busy hotbed of leading-edge micro- responsibilities at LSI Logic. We schedules to support our humble processor activity with AMD recent- wish to extend our best wishes to service to the northern Colorado ly opening its brand new Mile High him and heartfelt thanks for his design community. Finally, we Design Center to match Intel’s instrumental leadership and com- welcome Bruce Doyle who recent- established presence in Itanium mitment to grow this young chap- ly joined the existing officer team. development. ter for several years soon after its Please visit ewh.ieee.org/r5/den- We regret to announce that Past inception in late 2002. We are also ver/sscs/ for more information, Chair Dr. Don McGrath decided to grateful to our past speakers, espe- including past presentation slides, step aside from chapter activities, cially those who traveled from dis- about our chapter events.

Winter 2007 IEEE SSCS NEWSLETTER 73 sscs_NL0107 1/8/07 9:58 AM Page 74

CONFERENCES The Second A-SSCC Considers Challenges for the e-Life

ment and demonstration of the fabricated integrated circuit. The papers, co-authors, and abstracts are listed below.

(I) A TCAM-based Periodic Event Generator for Multi-Node Manage- ment in the Body Sensor Network Sungdae Choi, Kyomin Sohn, Jooy- oung Kim, Jerald Yoo and Hoi-Jun Yoo (KAIST)

A low-power periodic events generation is essential for a node con- troller in the network system with centralized control and the timer interrupt generation for various Gathered for the opening plenary of the A-SSCC in Hangzhou are(l-r) Prof devices in a CPU. The proposed Tadahiro Kuroda of Keo University and Chair of the Invited Program Commit- TCAM-based periodic event gener- tee, Nicky Lu of Etron Technology and Chair of Conference Industry Program, Richard C. Jaeger of Auburn University and President SSCS, Richard Chang, the ator manages the issuing events President of Semiconductor Manufacturing International Corporation and with the programmed value and Chair of the Technical Program, and C.K. Wang of National Taiwan University the number of the events is equal and Conference Steering Committee Chair. to the number of the word line of the TCAM block. The NAND-type he successful Asian Solid- ISSCC poster session. The A-SSCC TCAM cell operates with as low as State Circuits Conference in student design contest finalists 0.6V supply voltage and the low- TNovember, 2006 in Hangzhou, are selected from regular accept- energy match line precharge China was organized with a core of ed papers that are authored by reduces the search line transition 107 papers selected by an interna- students. Only the realized which causes most of the search tional program committee. The designs, not simply simulations, energy dissipation. The imple- acceptance rate was 32% with a con- are selected and invited to mented event generator consumes ference audience of 260 registered demonstrate the operation of the 184-nJ energy to schedule events attendees. CK Wang, the Steering chips on-site. It is not a contest of 255 nodes for 24-hours, which is Committee chair of A-SSCC, report- with a single specification or less than 10% of energy consump- ed that the conference was quite application, but rather a contest tion of conventional hardware successful both “in terms of paper for the completeness of develop- timer blocks. quality and foreign attendees with 82 from Japan, 48 from Taiwan, and 39 from Korea.” Prof Wei of Tsinghua University and local host felt that it was the first high quality and world class conference held in China. The tutorials that began the conference were open at no cost to any students in attendance. Three papers, announced as winners of the Student Design Contest, were awarded at A-SSCC. The competition, in cooperation with the ISSCC, includes trans- Winners of the A-SSCC 2006 student design contest were (from left) first, Sung- portation for the lead student dae Choi of KAIST, Seoul, second Mr. Yusaku Ito of the Tokyo Institute of Tech- researcher to the ISSCC February nology, and third Mr. Simone Gambini Simone Gambini and Jan Rabaey of the 2007 in San Francisco, for the University of California at Berkeley. Presenting the awards is Prof. Hoi-Jun papers to be included in the Yoo, Chair of Design Contest.

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CONFERENCES

(2) A 0.98 to 6.6 GHz Tunable exhibit 0.98-to-6.6GHz continuous the device achieves 6 bits of reso- Wideband VCO in a 180 nm frequency tuning with -206dBc/Hz lution at 1.5 MS/s output rate, CMOS Technology for Reconfig- of FoMt which is fabricated by using while drawing 28 microamps from urable Radio Transceiver a 0.18um CMOS process. The fre- a low 0.5 V supply, corresponding Yusaku Ito, Hirotaka Sugawara, quency tuning range (FTR) is 149%, to a Figure of Merit (FOM) of Kenichi Okada and Kazuya Masu and the chip area is 800µm x 540µm. .25pJ/conversion step. Low-density (Tokyo Institute of Technology) metal5-metal6 capacitors guarantee (3) A 1.5MS/s 6-bit ADC with feedback DAC linearity while min- This paper proposes a novel wide- 0.5V supply imizing input capacitance, while band voltage-controlled oscillator Simone Gambini and Jan Rabaey the use of a passive sample and (VCO) for multi-band transceivers. (University of California at Berkeley) hold, combined with a class-AB The proposed VCO has a core LC- comparator reduce analog power VCO and a tuning-range extension A moderate resolution analog-to- dissipation to 4 microWatts (30% of circuit, which consists of switches, a digital converter targeting wireless the total). The analog core is oper- mixer, dividers, and variable gain sensor networks applications is ational for supply values as low as combiners with a spurious rejection presented. Employing a succes- .3V, even though sampling rate is technique. The experimental results sive-approximation architecture, reduced to 175kS/s. Invitation from the ISSCC 2007 Technical Program Chair would like to invite you to attend parameter variability in today’s the 54th ISSCC which will be held nanoscale technologies requires a Iin San Francisco on February 11- global optimization among the four 15, 2007. The conference theme is dimensions of IC design. “The 4 Dimensions of IC Innova- There are also the traditional tion,” in recognition of the emerging evening sessions. One of the synergisms between the various evening panels will discuss the aspects of integrated circuit realiza- “ultimate limits of ICs” while tion. There will be 243 outstanding another will deal with “digital RF”. papers distributed over 31 technical The panels bring together experts sessions covering advances in ana- and visionaries who share their log and digital circuits, data convert- views with the participants. In ers, imagers, display and MEMS, addition, seven special topics ses- memories, RF building blocks, tech- year, there are ten Tutorials, seven sions will provide an opportunity nology directions, and wireless and Design Forums, and one Short to learn about an emerging topic wireline communications. A com- Course. This year’s short course in a relaxed setting. mon theme among many of the deals with the popular topic of As you can see, the upcoming papers is how to control power con- “analog, mixed-signal, and RF cir- ISSCC continues its tradition of sumption in deep-submicron tech- cuit design in nanometer CMOS”. presenting the best in solid-state nologies while pushing for higher There are also three excellent circuits and providing an opportu- performance and functionality. This plenary presentations. Morris nity to learn about the latest requires careful optimization among Chang of TSMC will talk about the developments through its rich the four dimensions of IC design future and the challenges of silicon choice of educational activities. In (technology, devices, circuits, and foundries and how foundries will addition, the ISSCC is a great architecture). Several papers will continue to be a driving force for avenue to network, meet old col- present new approaches or circuits the semiconductor industry by pro- leagues and make new friends. I for dealing with the power issue, viding advanced technologies. The am sure you’ll enjoy the ISSCC while other papers will set new per- second plenary presentation by and I hope to be able to welcome formance records. Lewis Counts of Analog Devices you in San Francisco. Besides the regular paper ses- will focus on analog and mixed- sions, the ISSCC will offer a wide mode circuit innovation in the Jan Van der Spiegel variety of high-quality educational nanoscale regime. The third talk by Technical Program Chair, ISSCC programs, adding to the already Dr. Joel Hartmann of Crolles2 2007 significant value of the ISSCC. This Alliance will explain how increased [email protected]

Winter 2007 IEEE SSCS NEWSLETTER 75 sscs_NL0107 1/8/07 9:58 AM Page 76

CONFERENCES Solid-State Circuits Conference Will Focus on Nano-Era Synergy ISSCC 2007 to Meet on 11-15 February in San Francisco Katherine Olstein, SSCS Administrator, [email protected]

ynergy between various plays. Special topic sessions in son (UC, San Diego) and Jan Cran- dimensions of integrated cir- three of these technical areas will inckx (IMEC, Belgium), who will Scuits in the nano-electronic be “Last-Mile Access Options: explore challenges and trends in era will be the theme of ISSCC PON/DLS/Cable/ Wireless,” “Secure CMOS in scaling technologies: 2007. ISSCC is the flagship confer- Digital Systems,” and “Implantable As CMOS chip technologies ence of the Solid-State Circuits and Prosthetic Devices: Life-Chang- scale to finer line widths, smaller Society. ing Circuits.” The Wireless session devices, and lower voltages, ana- will include a panel discussion enti- log circuit targets are harder to Balance Among Process, Circuit, tled “Digital RF– A Fundamentally- achieve due to larger device mis- Architecture, and System Technology New Technology, or Just Marketing match, non-ideal device character- Advances Required for Innovation Hype?” and a forum, “Giraffe: istics, and limited voltage swing. At Pushed by the continued growth of Power Amplifiers and Transmitter the same time, scaled technologies Moore’s Law, integrated circuits Architectures.” There will also be a reduce power and area, while have evolved from the micro-elec- tutorial within each area. increasing performance and lower- tronic into the nano-electronic era. In the area of data converters ing cost for digital circuits every This transition has created tremen- we notice a shift into the 90nm year. These trends lead to the dis- dous opportunities for higher-den- regime with 1-1.2V supply voltage placement of high linearity, highly sity, higher-performance, lower- giving rise to higher performance accurate analog circuits by lower power circuits and systems result- and lower power consumption for performance analog circuits. How- ing in cost-effective solutions for multimode operations. The papers ever, digital signal processing tech- ubiquitous communications, com- in the digital arena showcase 65nm niques come to the rescue, result- putation, sensing, display, con- technologies at clocking speed up ing in better performance, at lower sumer electronics, and multimedia. to 5GHz. Power management cost and shorter design time. However, the advent of the nano- receives special attention among “Circuit Design in the Year 2012” era has blurred the traditional the high performance digital will be presented by David Frank boundaries between the four papers. Circuits make further (IBM, TJ Watson, Yorktown Heights, dimensions of IC innovation (tech- inroads into the medical area with NY), Hae-Seung Lee (MIT), Marcel nology, devices, circuits, and sys- implantable brain probes, multi- Pelgrom (Philips Research, Eind- tem architecture). As a result, inno- channel high-resolution retinal hoven, The Netherlands) and vation in solid-state circuits requires prosthesis. CMOS imagers witness Borivoje Nikolic (UC, Berkeley). an intricate balance among continued shrinking of the pixel This special-topic-session will pro- advances in process, circuit, archi- size while improving performance, vide a thorough overview of special tecture and system technology. competing with CCD type of circuit design considerations which imagers. Papers in the area of will accommodate sub-32nm device Novel Circuit Concepts and Four- Technology Direction will show- idiosyncrasies. Four experts will Dimension Interrelationships case the next-generation, post- share their insight into issues con- Selected for Technical Program CMOS technologies and systems. fronting microprocessor and mixed- Paper proposals for novel circuit signal design in 2012 and offer concepts and systems and explo- Special-Topic Sessions on Next- potential solutions. rations of the interrelationships Generation Circuit Design among the four dimensions of IC On Sunday evening before the first Short Course for Entry-Level and innovation were especially sought day of the Conference, two special- Experienced Nanometer CMOS for the Conference. topic seminars addressing next-gen- Designers Within the resulting technical eration circuit-design challenges A Short Course organized by Ian program of 234 papers, fifty percent will be open to all attendees. Galton entitled “Analog, Mixed-Sig- are devoted in nearly equal propor- “Digitally Enhanced Analog and nal and RF Circuit Design in tions to wireline, digital, wireless, RF” will include four talks by Boris Nanometer CMOS” will be offered and the combined category of Murmann (Stanford University), twice, with staggered starting times. imagers, medical, MEMS and dis- Steve Lewis (UC, Davis), Larry Lar- Instructors Matt Miller (Freescale

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CONFERENCES

Semiconductor), Bram Nauta (Uni- ous industry experience may be tion in each IC generation, they versity of Twente, The Nether- more difficult to attain in the must also operate under physical lands), Robert Bogdan Staszewski future, simply because revenue constraints that, until recently, (Texas Instruments), and Michel S. growth of the semiconductor IC have been secondary in the digital J. Steyaert (Katholieke Universiteit, industry (as a whole) has slowed world. Leuven, Belgium) will each give a since 2000, and will continue to do From the advent of the first ana- lecture. so. Additionally, the penetration of log IC, analog designers have In this one-day session they will the CMOS-logic market by the exploited the potential of process explain the fundamental limitations foundry industry cannot continue technology to develop circuits that faced by those designing critical unabated indefinitely; saturation minimize the impact of variation in communication system blocks such should be anticipated in the future. process parameters on product as amplifiers, mixers, data convert- The second challenge for the performance. While process scaling ers, and phase-locked loops in foundry industry is to maintain has enabled the development of a nanometer CMOS, and present profitability: The growth of the wide variety of products, from cell- state-of-the-art circuit and system- industry has attracted many com- phones to advanced medical-imag- level techniques for addressing panies to offer foundry services. ing systems, the success of these these limitations. A DVD including Consequently, competition be- products depends in large measure (1) The visuals of the four Short- tween these companies increases on their ease of use, and seamless Course presentations in PDF for- the potential for commoditization connection to wireless and wired mat; (2) Audio recordings of the of foundry services, where many networks. Analog and mixed-signal presentations along with written foundries, with apparently similar subsystems, including display driv- transcriptions; (3) Bibliographies of (but substantively different) servers, and WLAN and cellular radios, background papers for all four pre- ices, compete on the basis of support these critical interfaces. sentations; and (4) PDF copies of price alone. The downward scaling of supply selected relevant background The foundry industry must voltage in deep submicron CMOS material and important papers in respond to these challenges by two (now at 1V), may limit dynamic the field (10 to 20 papers per pres- means: expanding into new IC- range, forcing some analog func- entation) may be purchased at reg- product markets enabled by the tions to be implemented on other istration time, or at the on-site reg- cost reduction and performance processes, but it has also enabled istration desk. A substantial price increases resulting from technology new circuit architectures that gain reduction is offered to those who scaling; and by penetrating seg- back dynamic range. attend the course. ments of the IC market that are cur- The creative combination of rently not involved in foundry rela- process, design, and system archi- Plenary Session tionships, by broadening the range tecture in providing robust solu- At the opening of the conference, of technologies that are offered. In tions for demanding applications, three invited speakers from indus- the future, circuit designers can will prove to be even more crucial try will examine key considera- expect, therefore, to be able to in the future. Such solutions will tions and offer roadmaps for tech- access process technologies tuned be essential in meeting the chal- nical innovation. in various ways: For memory, ana- lenges posed by the physical reali- “Foundry Future: Challenges in log, high-performance-logic, or ties of deep- submicron design in the 21st Century” will be the topic of image-sensor applications, as well achieving gigahertz speeds, mini- Morris Chang, Founding Chairman, as for CMOS logic. mizing power consumption, and Taiwan Semiconductor Manufactur- Lewis Counts, Vice-President of integrating multiple functions in ing Corporation, Hsinchu, Taiwan. Analog Technology and Fellow smaller packages. The foundry business-model is Analog Devices, Wilmington, MA, Joel Hartmann, Director, Crolles2 an important positive influence on will discuss “Analog and Mixed-Sig- Alliance, STMicroelectronics, Crolles, the health of the overall IC indus- nal Innovation: The Process-Circuit- France will explore the intricate bal- try. Therefore, it is critically neces- System-Application Interaction.” ance that will increasingly be sary to scan the future for potential Innovation in analog and mixed- required among process, device, issues that might inhibit foundry- signal electronics becomes increas- circuit, and system aspects of industry growth. ingly more important to the con- design in “Toward a New Nanoelec- In order to ensure continued tinued growth of the IC industry. tronic Cosmology.” expansion, the foundry industry While technologists working in the Gone forever are the days of must address two significant chal- analog and mixed-signal arena smooth roadmap scaling, with its lenges: The first and foremost chal- share, with their digital counter- more-or-less-simple design rules, lenge is business growth: We antic- parts, the overarching goal of adequate supply voltages, and ipate that growth matching previ- reducing power and cost-per-func- unimpeded circuit shrinkage. As

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CONFERENCES

scaling moved ahead to nanometer causes is urgently required to guide (GDfM) unifies current Design-for- dimensions, things changed: the right choices at all levels. Con- Manufacturability (DfM), Manufac- Devices became more difficult to ceptually, such understanding will turing-for-Design (MfD), and predict, and global performance lead to acceptable levels of perform- Design-for-Yield (DfY), coupling degraded due to leakage and dis- ance, manufacturability, and yield, at all of the above-mentioned dimen- persion. One of the consequences ever-decreasing feature sizes. Mean- sions within a new space where of this deteriorating situation has while, the increased parameter vari- their inter-dependence is revealed been that increased parameter ability observed today, as one tech- and exploited. Tightly coupled variability has led to a significant nology node invites the next, reveals physical-electrical-mechanical- mismatch between simulation and the tight coupling of the four seem- process modeling and simulation, actual measurement results, at all ingly- independent dimensions of will allow early detection of the levels. While many of these effects design, motivating the need to con- impact of design choices at all lev- have already been well known to figure a new nano-cosmology, one els. This creates a 4D knowledge analog designers, the surprise, in which global optimization results continuum reminiscent of the ideas now, is that they are more broadly only from an intricate balance of General Relativity, ones important, even in digital design, between the Process, Device, Cir- extremely rich in consequences for where previously available noise cuit, and System aspects of design. the future of nanoelectronic design. margins have almost disappeared. In this new nano-cosmology, the More information about ISSCC Clearly, deep understanding and emerging concept of Generalized 2007 may be found at: modeling of all underlying physical Design-for-Manufacturability http://www.isscc.org/isscc/. Advances in Analogue Circuit Design Conference (AACD) Will Convene on 27-29 March 2007 16th Annual Workshop to Showcase European Expertise in Semiconductor Design Applications Jan Craninckx, Chair, SSCS-Benelux, [email protected], Jan Sevenhans, SSCS Region 8 Representative, [email protected], Jan Van der Spiegel, SSCS Chapters Chair, [email protected]

he 16th annual AACD work- Ends (Wed 28 March) University, Leuven shop will be held on 27 – 29 • Integrated PA’s from Wire line • Arthur Van Roermund, Eind- TMarch, 2007 in the Hotel to RF (Thu 29 March) hoven University of Tech- Thermae Palace at the beautiful A panel discussion will be nology. beach resort of Oostende, Belgium. organized every evening on the Europe has expertise in a rich SSCS is a technical cosponsor of this topic of the day to ensure a lively variety of semiconductor design conference. interaction with the audience. The applications: high-reliability and The Thermae Palace, a unique AACD technical program commit- high-voltage automotive, medical seaside hotel in Art Deco style, is tee for 2007 consists of for hearing aids and bio sensors, conveniently located within walk- • Herman Casier, AMI Semicon- space radiation hard circuits and ing distance of the bustling Oost- ductor Fellow, Belgium telecom mixed signal and multi- ende city centre. • Michiel Steyaert, Catholic media, among others. The three-day workshop will Each year, a European company feature 18 excellent speakers on takes the initiative to support the the following topics: AACD local and logistic organiza- • Sensors, Actuators and Power tion to give the technical program Drivers for the Automotive committee leaders a free hand to and Industrial Environment invite the best international speak- (Tue 27 March) ers for this three-day summary of • Very High Frequency Front advances in analogue circuit

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design. This year, the AACD local organisation is supported by the Communication High Voltage Prod- uct group of AMI Semiconductor in Belgium, represented by Jan Sev- enhans PhD, IEEE fellow, and technically co-sponsored by IMEC, Leu- ven, Belgium in cooperation with the SSCS-Benelux chapter. Willy Sansen (KU Leuven), Jan Huijsing (TU Delft) and Rudy Van de Plassche (Broadcom) started the AACD annual workshop in 1992 with the goal of bringing together analog circuit From left, Jan Van der Spiegel, SSCS Chapters Chair (University of Pennsylva- design experts in Europe. The nia), Jan Craninckx, SSCS-Benelux Chair (IMEC, Belgium), and Jan Sevenhans, proceedings with full paper con- SSCS Region 8 Representative (AMI Semiconductor). tributions have been published each year summarizing the state of the art. Over the past 15 years, the AACD workshop has covered timely topics such as biomedical circuits and sensors, telecom wireline copper and fiber optics, wireless public and LAN mixed signal systems on a chip, RF and baseband analogue radio circuits in bipolar and CMOS technologies, DSL drivers, A/D & D/A converters, low noise amplifiers, etc. It has taken place in From left, Dr. Van De Plassche, Dr. Sansen and Dr. Huijsing at the inaugural AACD conference in Scheveningen, The Netherlands, 1992. Scheveningen, Leuven, Eind- hoven, Villach, Lausanne, Como, come a large group of silicon cir- other applications for this 16th Copenhagen, Nice, Munich, cuit and technology engineers and AACD! Noordwijk, Spa, Graz, Montreux, researchers involved in analogue More information may be found Limerick and Maastricht. and RF IC design in automotive, at www.aacd.ws/ and aacd2007@ It will be our pleasure to wel- telecom and all industrial and amis.com

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SSCS NEWS Corcoran, Kornegay, H. S.Lee, T. Lee, and Van der Spiegel Elected to SSCS AdCom

John J. Kevin Hae-Seung Thomas H. Jan Van der Corcoran Kornegay (Harry) Lee Lee Spiegel

he SSCS membership re-elected five members to the ISSCC in February and again in the summer. the Solid-State Circuits Society Administrative The AdCom is responsible for overseeing Society TCommittee (AdCom) for terms beginning 1 Jan- technical activities, conferences and publications, and uary, 2007. for initiating, developing and managing all Society Jan Van der Spiegel and Thomas H. Lee were elect- activities. Stephen H. Lewis, SSCS past president and ed for a second term, and Kevin Kornegay and Hae- chair of the nominating committee, said that it recruit- Seung (Harry) Lee were elected as new members. The ed individuals with a broad understanding of the field election also returned John J. Corcoran to the AdCom and its working engineers. after a year off. Biographies of the 2007 AdCom members were pub- The AdCom includes fifteen members elected by lished in the July Newsletter and are available on line. the membership at large, with 5 members elected each www.ieee.org/portal/pages/sscs/06July/AcCom_Can- year for a 3-year term. They meet twice a year, before didates06.html Design Council Newsletter Completes Inaugural Year

he year-old IEEE Council on standalone version is distributed Electronic Design Automation online as well as in paper form at T(CEDA) updates interested major CEDA events. The editors are readers with its quarterly CEDA Cur- Karti Mayaram ([email protected] rents Newsletter. SSCS is one of six state.edu) and Preeti Ranjan Panda founding member societies of the ([email protected]); Nanette Collins IEEE Council, which is best known ([email protected]) also serves as for sponsoring the Design Automa- support for IEEE CEDA’s broader out- tion Conference. In this first year of reach activities. publishing CEDA Currents Newsletter, In addition to Currents Newslet- articles covered Logic Synthesis com- ter, CEDA also publishes IEEE petition at IWLS, an interview with Transactions on Computer Aided Robert Brayton, and opinion pieces Design which features in-depth on the state and need for formal technical articles for the re- verification. searchers, and the Design & Test The Currents Newsletter is avail- magazine which features technical able in two formats, on line at articles that have direct impact on www.ieee-ceda.org, and as an industrial practice. embedded department within IEEE Design & Test, abridged and edited to conform to the Founding of CEDA publishing guidelines of that IEEE Computer Society The Solid-State Circuits Society is a founding member magazine. The standalone version of the newsletter of the IEEE Council on Electronic Design Automation carries content additional to the D&T embedded cov- (CEDA). The SSCSC AdCom voted its support in Feb- erage; a column related to interviews, opinions, ruary 2005. Bryan Ackland and Jan Rabaey serve as counter-opinions and matters of general interest to SSCS Representatives on the new CEDA governing the community. In addition, since the standalone ver- body whose President is Al Dunlop. sion is published at a shorter schedule, it accommo- As a subject area, design automation has been dates last minute listing of events and news. The spread across a number of technical activities within

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SSCS NEWS

the IEEE. These activities range from monolithic cir- effective January 2006. Within IEEE Technical Activi- cuits to large information-processing systems. Within ties, a council like CEDA represents an organization the context of electronic systems, computer-aided with member societies. CEDA has six IEEE member design (CAD) was synonymous with circuit simulation societies: Antennas and Propagation; Circuits and Sys- when it started as a discipline in the ‘60s. Now, CAD tems; Computer; Electron Devices; Microwave Theory deals with a much broader set of concerns. Those and Techniques; and Solid-State Circuits. As with any issues continue to evolve with technological advances IEEE technical activity, the ultimate goal is to advance in materials, processing, devices, and circuits. Gener- the profession through a variety of technical activities ally, they’re put under the umbrella of electronic from conferences and publications to standards. To design automation (EDA). serve members who are spread across various mem- On one side of the spectrum, the physical design of ber societies, CEDA brings together several important electronic circuits requires both deep knowledge and resources. It provides conferences and publications to interaction with specialists on solid-state circuits and its technical community. As of this writing, the co- more broadly electronic devices. Yet the ubiquitous sponsored conferences include DAC, ICCAD, and presence of programmable processor cores in integrated Design and Test in Europe (DATE). CEDA enjoys spe- circuits has shifted much CAD work into the design of cial relationships with focused technical activities, embedded software and hardware/software co-design-- such as DATC and TTTC in the Computer Society and areas that are traditionally covered by computer scien- CANDE within the Circuits and Systems Society. tists. By combining theory and practice, CAD is a key CEDA also is participating in the DARPA/MTO activi- technology that boasts its own thriving industry. It also ties in building the roadmap for electronic systems is a driver for the much larger semiconductor and elec- Rajesh K. Gupta, the Vice President of Publications tronic systems industry. It was natural for such an activ- for CEDA says, “Clearly, we’re pleased to receive such ity to have a diversified footprint within the IEEE as a broad support and community momentum toward technical organization. The range of CAD activities building this new Council. We also are humbled by enabled the IEEE to benefit from the significant cross- the challenges facing the community, which must fertilization of ideas from various mathematical and engi- match the pace of innovation by rapidly drawing new neering optimizations and practices. As an organized talent and entrepreneurship to the field. We need to activity, however, it was much harder for the organiza- engender technical activities that excite and challenge tion to serve its members with information on interrelat- our audience and readership to new capabilities and ed advances and publications. The recognition of major opportunities. From this promising start, we hope to advances was often secondary to major society activities. build years of exciting innovation and invention in CEDA was ratified by IEEE as a Technical Council electronic design automation.”

IEEE Undergraduate Teaching Award Nomination Deadline - January 31st

he IEEE Undergraduate Teaching Award Selection criteria include such contributions is a Technical Field Award of the Insti- as curriculum development, authorship of Ttute established by the Board of course materials, involvement with stu- Directors in 1990 to honor teachers of elec- dents and faculty in advisory capacities, as trical and electronics engineering and the well as ‘attracting students to engineering related disciplines, ‘for inspirational teach- and scientific professions, and preparing ing of undergraduate students in the fields them for effective careers in engineering of interest of the IEEE.’ and the sciences.’ A primary goal of the IEEE is to ensure that Recipient selection is administered by the the Institute Awards Program provides due recog- IEEE Awards Board through the Technical Field nition for superior achievement in the engineering Awards Council. It is presented to an individual only. profession. To that end, and in response to the The award consists of a bronze medal, certificate desire of the membership, the Awards Board, and and honorarium. Board of Directors that the field of education be For a nomination form, list of past recipients and more broadly recognized, this award for undergrad- committee roster see: uate teaching was added to the Awards Program. www.ieee.org/awards/sums/ungrad.xml

Winter 2007 IEEE SSCS NEWSLETTER 81 sscs_NL0107 1/8/07 9:59 AM Page 82

SSCS NEWS IEEE Leon K. Kirchmayer Graduate Teaching Award Nomination Deadline - 31 January

he IEEE Graduate Teaching Award is a ‘attracting students to engineering and scien- Technical Field Award established by tific professions, and preparing them for Tthe Board of Directors in 1990 and effective careers in engineering and the renamed in honor of Leon K. Kirchmay- sciences.’ er in 2002. Dr. Kirchmayer was well Recipient selection is administered known and revered throughout the by the IEEE Awards Board through the world for his commitment to students Technical Field Awards Council. It is and education. awarded to an individual only. This award honors teachers of electri- In the evaluation process, the follow- cal and electronics engineering and the ing criteria are considered: excellence in related disciplines, ‘for inspirational teaching of teaching graduate students, curriculum devel- graduate students in the IEEE fields of interest.’ opment with the inclusion of current research and A primary goal of the IEEE is to ensure that the development knowledge that reflects the state of the Institute Awards Program provides due recognition art in courses, authorship of course material for grad- for superior achievement in the engineering profes- uate students; and involvement with and direction of sion. To that end, and in response to the desire of the students to prepare them for effective careers in engi- membership, the Awards Board, and Board of Direc- neering and the sciences, and the quality of the nom- tors that the field of education be more broadly rec- ination. ognized, this award for graduate teaching was added The award consists of a bronze medal, certificate to the Awards Program. Selection criteria include and honorarium. such contributions as curriculum development, For nomination form, list of past recipients and a authorship of course materials, involvement with stu- committee roster: dents and faculty in advisory capacities, as well as www.ieee.org/awards/sums/gradtch.xml

Call for Nominations: SSCS Predoctoral Fellowships 2007 – 2008 Due Date is 1 May, 2007

ominations for the Society’s Predoctoral Fellow- authored or co-authored. A copy of each publication ships in solid-state circuits are due on 1 May, is desirable. Work that must be done to complete the N2007 for the academic year 2007-2008. The one- graduate program of study should be explained -- year awards will include a stipend of $15,000, tuition why it is important, and what is novel about its and fees up to a maximum of $8,000, and a grant of approach -- as well as the importance of SSCS pre- $2,000 to the department in which the recipient is reg- doctoral fellowship support toward completion of the istered. A maximum of two awards will be made. doctoral degree. Applicants must have completed at least one year Letters of Recommendation - At least two letters of graduate study, be in a Ph.D. program in the area of recommendation are required; one should be from of solid-state circuits, and be a member of IEEE. the principal advisor. These letters should address The award will be made on the basis of academic academic record, accomplishments and promise, record and promise, dissertation research program, graduate study research program, and need. and need. Deadline: 1 May 2007 Applications should be in electronic format and Please email your application materials to: must include the following items: [email protected]. A Short (one-page) Biography - including IEEE Electronic file submission is preferred but if paper membership number. files are all you can provide, either fax them to +1 Academic Records - including a copy of all rele- 732-981-3401 or mail to: vant undergraduate and graduate transcripts. IEEE-SSCS Executive Office Graduate Study Plans - including a summary of Predoctoral Fellowship what has been completed and what is planned (about 445 Hoes Lane 2 pages is appropriate), plus a list of any publications Piscataway, NJ 08854

82 IEEE SSCS NEWSLETTER Winter 2007 sscs_NL0107 1/8/07 9:59 AM Page 83

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SSCS EVENTS CALENDAR Also posted on www.sscs.org/meetings SSCS SPONSORED MEETINGS Bangalore, India 2007 Radio Frequency Integrated 2007 ISSCC International Solid-State Paper deadline: Passed Circuits Symposium Circuits Conference Contact: VLSI Secretariat: www.rfic2007.org www.isscc.org [email protected] 3–8 June 2007 11– 15 February 2006 Honolulu, Hawaii San Francisco Marriott Hotel, San Francisco, Advances in Analogue Circuit Design Paper deadline: 8 January 2007 CA, USA (AACD) Conference Contact: Dr. Luciano Boglione Paper deadline: Passed Contact: Courtesy Associates, www.aacd.ws/ [email protected] [email protected] 27–29 March, 2007 Oostende, Belgium. 2007 Design Automation Conference 2007 Symposium on VLSI Circuits Paper deadline: TBD www.dac.com www.vlsisymposium.org Contact: [email protected] 4–8 June 2007 14–16 June 2007 Kyoto, Japan San Diego, CA, USA Paper deadline: 10 January 2007 2007 Design, Automation and Test in Paper deadline: Passed Contact: Phyllis Mahoney, Europe Contact: Kevin Lepine, Conference Manager [email protected] www.date-conference.com/conference/next.htm [email protected] or Business Center for Academic Societies, 16–20 April, 2007 Japan, [email protected] Acropolis, Nice, France 2007 IEEE Symposium on VLSI Circuits Paper deadline: Passed www.vlsisymposium.org 2007 Custom Integrated Circuits Contact: [email protected] 14 Jun - 16 Jun 2007 Conference Kyoto, Japan http://www.ieee-cicc.org/ 2007 International Symposium on VLSI Paper Deadline: 10 January 2007 16–19 September 2007 San Jose, CA, USA Technology, Systems and Applications Contact: Ms. Phyllis W. Mahoney Paper deadline: TBD (VLSI-TSA) [email protected] Contact: Ms. Melissa Widerkehr vlsidat.itri.org.tw [email protected] 25 Apr - 27 Apr 2007 ESSCIRC/ESSDERC 2007 - 37th European Solid Hsinchu, Taiwan State Circuits/Device Research Conferences www.essscirc.org 2007 A-SSCC Asia Solid-State Circuits Con- Paper Deadline: Passed ference 11 Sep - 13 Sep 2007 www.a-sscc.org/ Contact: Ms. Stacey C.P. Hsieh Munich, Germany 12–14 November 2007 [email protected] Paper Deadline: 7 April 2007 Seoul, Korea Contact: Mr. Philip Teichmann [email protected] Paper deadline: TBD 2007 International Symposium on VLSI Contact: [email protected] Design, Automation and Test (VLSI-DAT) 2007 IEEE Bipolar/BiCMOS Circuits and vlsidat.itri.org.tw Technology SSCS PROVIDES TECHNICAL 25 Apr - 27 Apr 2007 Meeting - BCTM CO-SPONSORSHIP Hsinchu, Taiwan 30 Sep - 02 Oct 2007 2007 International Conference on VLSI Paper Deadline: Passed Boston Marriott Long Wharf, Boston, MA Design Paper Deadline: TBD Contact: Elodie J.F. Ho www.vlsiconference.com/ Contact: Ms. Janice Jopke [email protected] [email protected] 6–10 January 2007

IEEE SOLID-STATE CIRCUITS SOCIETY NEWSLETTER is published three times per year, January, May, and September by the Solid-State Circuits Society of The Institute of Electrical and Electronics Engineers, Inc. Headquarters: 3 Park Avenue, 17th Floor, New York, NY 10016-5997. $1 per member per year (included in society fee) for each member of the Solid-State Circuits Society. This newsletter is printed in the U.S.A. Postmaster: Send address changes to IEEE Solid-State Circuits Society Newsletter, IEEE, 445 Hoes Lane, Piscataway, NJ 08854. ©2006 IEEE. Permission to copy without fee all or part of any materi- To maintain all your IEEE and SSCS al without a copyright notice is granted provided that the copies are not made or distributed for direct subscriptions, email address corrections to commercial advantage and the title of publication and its date appear on each copy. To copy material [email protected] with a copyright notice requires specific permission. Please direct all inquiries or requests to IEEE Copy- To make sure you receive an email alert, keep rights Manager, IEEE Service Center, 445 Hoes Lane, Piscataway, NJ 08854. Tel: +1 732 562 3966. your email address current at sscs.org/e-news

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