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Fast Integrated Tools for Circuit Design with Fpgas Z Stephan W Fast Integrated Tools for Circuit Design with FPGAs z Stephan W. Gehring y , Stefan H.-M. Ludwig Institute for Computer Systems Swiss Federal Institute of Technology (ETH) Zurich,¨ Switzerland [email protected], [email protected] t Abstrac desiring complete control over the circuit implementation and of- fers a highly interactive and fast design cycle. It consists of an To implement high-density and high-speed FPGA circuits, design- architecture-independent framework (front-end) which is comple- ers need tight control over the circuit implementation process. How- mented by architecture-dependent back-ends. This enhances tool ever, current design tools are unsuited for this purpose as they lack maintenance as the framework is reused for each back-end. A com- fast turnaround times, interactiveness, and integration. We present plete back-end including layout synthesis has been developed for a system for the Xilinx XC6200 FPGA, which addresses these is- the Xilinx XC6200 architecture [23]. A further back-end for the sues. It consists of a suite of tightly integrated tools for the XC6200 Atmel AT6000 architecture [3] exists which comprises a layout ed- architecture centered around an architecture-independent tool frame- itor for manual circuit implementation and a bitstream generator. work. The system lets the designer easily intervene at various In the following, we first describe how the tight integration stages of the design process and features design cycle times (from of our tools is achieved. Then we explain how the designer can an HDL specification to a complete layout) in the order of seconds. influence the implementation process and discuss the techniques used to achieve the necessary speedy design cycle. We support our claims by measurements and compare our system with the vendor- Intro duction 1 supplied development system for the XC6200. A more detailed Fully automatic circuit synthesis from an HDL description is a presentation of the described system can be found in [8] and [14]. difficult and computationally intensive task, especially for Field- To ol Integrat ion Programmable Gate Arrays (FPGAs). Ideally, circuits are mapped, 2 placed and routed without human intervention. However, to im- plement high-density or high-speed circuits with FPGAs, today’s One of the major goals of this work was to tightly integrate the designers are faced with the need to manually intervene in the de- various circuit design tools into a single development environment. sign process and reiterate the implementation cycle until the circuit Traditionally, the tools used in the circuit design process are very implementation meets the requirements [4, 20]. Unfortunately, de- loosely coupled and are often developed by a variety of independent signers cannot expect much support from current design tools as the companies. For instance, the tools used to capture designs may latter do not support fast iterative design cycles and offer only lim- come from a CAD tool developer, while the layout synthesis and ited interactivity. This effectively hinders the designer from con- bitstream generation tools are provided by the chip manufacturer. trolling the implementation process. Typically, tool communication is achieved by exchanging disk files Developers of circuit design tools face yet a different problem: containing the design data in standard formats. the still growing number of new FPGA architectures pressures them We feel that this loose coupling bears several disadvantages. to create new tool suites at a rapid pace. Since the tools are typi- First, it makes the seamless integration of the tools a difficult, if not cally tailored to a specific architecture, they are rewritten almost impossible, task. This, however, is a prerequisite to quickly switch completely for every new architecture. Over time this results in a back and forth between design tools during the design process. Sec- huge collection of difficult to maintain tools. ond, file-based inter-tool communication necessitates conversions The system we present addresses these problems. It tightly in- between internal and external formats on both ends, which often tegrates the circuit design process in a single environment, from results in design information loss and makes data exchange a slow the initial circuit specification in an HDL down to bitstream gener- and vulnerable process. Third, decoupled tool development does ation. At all stages of the process, the user can exert control over not take into account that a significant part of a tool suite is inde- the circuit implementation and thus efficiently guide the tools to- pendent of any specific architecture and could thus profitably be wards the desired solution. The system targets the experienced user reused by several tools. Taking advantage of this reduces the size and memory requirements of tools and eases system maintenance. y Interval Research Corporation, Palo Alto, California z We have addressed these problems by capturing the common DEC Systems Research Center, Palo Alto, California traits of design tools in an application framework for circuit design tools [9, 8]. To create tools for a specific FPGA architecture, this architecture-independent framework is extended with architecture- specific components. The foundation for the tight integration of the framework and its extensions lies in the use of a single data structure to represent circuits throughout the system [9, 8]. That is, all tools, whether architecture-independent or -dependent, use a universal circuit rep- ends. The use of a single circuit representation resulted in the de- resentation defined in the core of the framework (Figure 1). The sired tightly integrated system with short response times and high design tools operate in a shared memory environment and modify interactivity. the data structure in situ. Data exchange between tools can thus be realized efficiently just by passing a reference to the data struc- Controlling the D esign Process ture. This avoids data structure conversions altogether and simpli- 3 fies both framework and tool implementations considerably. Keep- A key issue in the implementation of high-speed and high-density ing even large circuits entirely in main memory is possible due to circuits with FPGAs is allowing the (experienced) designer com- the compactness and simplicity of the representation. plete control over the circuit implementation. This is because, un- like in the software world, resources in an FPGA are scarce and HDL Bitstream therefore need to be tightly managed. Being the creator of the cir- Placer Router cuit, the designer has the most intimate knowledge of the circuit’s Compiler Generator structure and therefore knows best how it should be laid out. How- ever, the complexity of today’s circuits requires support by layout synthesis tools. The designer’s goal is therefore to guide the syn- thesis tools towards the desired solution. To enable this, our system Central allows the designer to influence the outcome of the tools at various Data Structure levels. At the circuit specification level, the designer can specify the placement of circuit components using position assignments in the Figure 1: Single Circuit Representation Accessed by Multiple De- Lola HDL. These placement hints are passed on to the automatic sign Tools placer which pre-places the parts prior to placing the remaining circuit parts. After placement, the layout editor can be used to en- The data structure represents circuits as a hierarchical forest of hance the placement manually. Since the hierarchy of the circuit is binary trees. Each tree specifies the Boolean equation for a sin- preserved by all tools and visualized by the layout editor, the de- gle circuit output. To accommodate for the needs of placers and signer is able to quickly identify and rearrange individual cells or routers, positional information and net lists can be attached to the entire subcircuits. As the layout editor is used frequently, we have nodes. All tools involved in the implementation process support taken care to make circuit manipulation as simple and as fast as and maintain the hierarchical circuit structure.Wehavefoundthat possible. Once a satisfactory placement is achieved, more place- this greatly improves the efficiency and quality of the layout syn- ments hints can be added to the HDL specification to reflect the thesis tools (see Section 4). new placement. These will constrain the placer during the next de- To describe the hierarchy of a circuit, the framework uses pa- sign iteration and will thus relieve the user from having to make the rameterizable templates. A template is a representation of a sub- same changes again during subsequent iterations. A compile-place circuit. Every instance of such a template is an exact copy of the cycle takes only a few seconds and the design quickly converges to template, i.e. it contains the same gates and net lists and they are at the desired placement. the same (relative) positions as in the master copy. Tools, such as a The designer can also influence the routing process. The router placer, can exploit this additional knowledge to efficiently produce allows individual nets to be routed and also supports the record- regular layouts for regular circuits, such as bit-sliced designs. ing and playback of routing scripts, which define the sequence in For textual design specification, the framework comprises a which the nets are routed. These scripts can be conveniently ap- compiler for the hardware description language Lola [21, 22]. The pended to the HDL specification text. Furthermore, the router can compiler translates a Lola circuit specification into the universal be constrained to only use certain types of routing resources, e.g. data structure ready to be processed further. The Lola HDL sup- only use the local interconnect. Should the automatic router fail to ports parameterized descriptions of subcircuits, e.g. N-bit adders, route a design successfully, the designer can use the layout editor and allows the designer to pass placement hints to back-end tools, to route certain nets manually.
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