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User's Manual, V 1.3, Feb. 2007 User’s Manual, V 1.3, Feb. 2007 XC866 8-Bit Single Chip Microcontroller Microcontrollers Edition 2007-02 Published by Infineon Technologies AG, 81726 München, Germany © Infineon Technologies AG 2007. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. User’s Manual, V 1.3, Feb. 2007 XC866 8-Bit Single Chip Microcontroller Microcontrollers 3-1 XC866 Revision History: V 1.3, 2007-02 Previous Version: V1.0, 2005-10 V1.1, 2005-12 V1.2, 2006-06 Page Subjects (major changes since last revision) 1-2 Device temperature range is updated, see Table 1-1. 1-2 Device variants are updated, see Table 1-3. 1-13 The hint for using MBC pin is added. 7-12 When the external oscillator is used, the on-chip oscillator can be powered down. 10-13 Table 10-3 is updated for the generation of 115.2 KHz baud rate. 14-6 NMI mode priority is over debug mode, see Section 14.2.1.4. We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: [email protected] XC866 Table of Contents Page 1 Introduction . 1-1 1.1 Feature Summary . 1-5 1.2 Pin Configuration . 1-7 1.3 Pin Definitions and Functions . 1-8 1.4 Textual Convention . 1-14 1.5 Reserved, Undefined and Unimplemented Terminology . 1-15 1.6 Acronyms . 1-16 2 Processor Architecture . 2-1 2.1 Functional Description . 2-2 2.2 CPU Register Description . 2-4 2.2.1 Stack Pointer (SP) . 2-4 2.2.2 Data Pointer (DPTR) . 2-4 2.2.3 Accumulator (ACC) . 2-4 2.2.4 B Register . 2-4 2.2.5 Program Status Word . 2-5 2.2.6 Extended Operation Register (EO) . 2-6 2.2.7 Power Control Register (PCON) . 2-7 2.3 Instruction Timing . 2-8 3 Memory Organization . 3-1 3.1 Program Memory . 3-3 3.2 Data Memory . 3-3 3.2.1 Internal Data Memory . 3-3 3.2.2 External Data Memory . 3-3 3.3 Memory Protection Strategy . 3-5 3.3.1 Memory Protection . 3-5 3.3.2 Flash Protection Enable . 3-7 3.4 Special Function Registers . 3-9 3.4.1 Address Extension by Mapping . 3-9 3.4.2 Address Extension by Paging . 3-12 3.4.3 Bit-Addressing . 3-15 3.4.4 System Control Registers . 3-16 3.4.4.1 Bit Protection Scheme . 3-18 3.4.5 XC866 Register Overview . 3-19 3.4.5.1 CPU Registers . 3-19 3.4.5.2 System Control Registers . 3-20 3.4.5.3 WDT Registers . 3-22 3.4.5.4 Port Registers . 3-22 3.4.5.5 ADC Registers . 3-23 3.4.5.6 Timer 2 Registers . 3-26 3.4.5.7 CCU6 Registers . 3-26 3.4.5.8 SSC Registers . 3-30 User’s Manual I-1 V 1.3, 2007-02 XC866 Table of Contents Page 3.4.5.9 OCDS Registers . 3-31 3.5 Boot ROM Operating Mode . 3-32 3.5.1 User Mode . 3-32 3.5.2 BootStrap Loader Mode . 3-32 3.5.3 OCDS Mode . 3-32 3.5.4 User JTAG Mode . 3-32 4 Flash Memory . 4-1 4.1 Flash Memory Map . 4-2 4.2 Flash Bank Sectorization . 4-3 4.3 Wordline Address . 4-5 4.4 Operating Modes . 4-7 4.5 Error Detection and Correction . 4-9 4.6 In-System Programming . 4-10 4.7 In-Application Programming . 4-11 4.7.1 Flash Programming . 4-11 4.7.2 Flash Erasing . 4-14 4.7.3 Aborting Flash Erase . 4-17 4.7.4 Flash Bank Read Status . 4-18 5 Interrupt System . 5-1 5.1 Interrupt Structure . 5-7 5.1.1 Interrupt Structure 1 . 5-7 5.1.2 Interrupt Structure 2 . 5-8 5.2 Interrupt Source and Vector . 5-10 5.3 Interrupt Register Description . 5-12 5.3.1 Interrupt Node Enable Registers . 5-12 5.3.2 External Interrupt Control Registers . 5-15 5.3.3 Interrupt Flag Registers . 5-19 5.3.4 Interrupt Priority Registers . 5-24 5.3.5 Interrupt Flag Overview . 5-27 5.4 Interrupt Handling . 5-28 5.5 Interrupt Response Time . 5-29 6 Parallel Ports . 6-1 6.1 General Port Operation . 6-2 6.1.1 General Register Description . 6-5 6.1.1.1 Data Register . 6-6 6.1.1.2 Direction Register . ..
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