Naming Convention for AURIXTM Family

Primary Brand Device Option Secondary Option

SA K – TC 2 7 5 T – 64 F 200 W

Series

TriCore

identifier

Frequency

Architecture

Memory Size Memory

Memory Type Memory

Package Type Package

Package Class Package

Infineon product product Infineon

Feature Package Feature

Core Architecture Core Temperature range Temperature

Temp. Range K -40° - +125 °C L -40°C - +150°C

Package Class Core Architecture Feature packages Flash size code Package type code 9 LFBGA-516 T Triple Core - Production Dev., No HSM 8 0.5MB W LQFP 0.5mm pitch 8 BGA-416 D Dual Core P Prod. Dev., HSM enabled 16 1 MB F TQFP 0.4mm pitch 7 LFBGA-292 S Single Core E Emulation Dev., no HSM 24 1.5 MB V VQFN 0.5mm pitch 5 LQFP-176 L Single Core F Emulation Dev., HSM enabled 32 2 MB L BGA 1.0 mm pitch 4 L/TQFP-144 with Lockstep A ADAS enhanced, HSM enabled 40 2.5 MB S LFBGA 0.8mm pitch 3 TQFP-100 B ADAS enhanced, No HSM 64 4 MB Q Fusion Quad QFP

2 TQFP-80 X Feature extension, HSM enabled 96 6 MB 0.5 mm pitch 0 Bare Die Y SRAM extension, No HSM 128 8 MB C Customer specific

2014-08-21 Copyright © Infineon Technologies AG 2014. All rights reserved. Page 1 Naming Convention for TriCore® Family

Example: SAK-TC1796-256F150E Automotive families: Code memory size: 1: Industry n*8k Bytes 2: Body e.g. 64: 64*8k=512k 3: Safety 7: Powertrain

Component specific

Temp. Range Code Mem. CPU Prefix Code Type Variation Size Type Freq. Package

40 B H 66 F L H SA TC1 y xx ED ## 80 H F N 150 K E 300

Variation: H = Quad flat pack ED = emulation device HL = L-QFP Other = blank L = Flashless HM = M-QFP F = Flash HT = T-QFP

B = 0/ 70 °C E = P-BGA F = -40/ 85 °C EL = P-LFBGA H = -40/ 110°C ET = P-TFBGA K = -40/ 125°C EB =P-LBGA U = flip-chip, bare die Example: SAK-TC1796 -256F150E

Copyright © Infineon Technologies AG 2013. All rights reserved. Page 2 Naming Convention for XMC4000 Family

Example: XMC4500–F144K1024 AC

Family Core Feature Package Pins Temp. Flash [kB] Step 1024 5 0 144 768 E K AA 4 2 100 512 XMC 4 0 F X AB 2 4 64 256 Q F AC 1 8 48 128 64

Silicon Version AA = 01 AB = 02 AC = 03

K = -40° to 125°C X = -40° to 105°C F = -40° to 85°C

E = LFBGA | F = LQFP | Q = VQFN

0 = Full Featured < ….. > 8 = Feature Subset

1 = Baseline < ….. > 5 = High-End

ARM® Cortex™-M4 with built in DSP, SPFPU, DMA and MPU

XMC := Industrial Family based on ARM® Cortex™-M Processors

Copyright © Infineon Technologies AG 2013. All rights reserved. Page 3 Naming Convention for XMC1000 Family

Example: XMC1302-T038X0200 AA

Family Core Feature Package Pins Temp. Flash [kB] Step 200 40 128 3 2 38 Q X 64 XMC 1 2 0 1 28 AA T F 32 1 0 24 16 16 8

Silicon Version AA = 01

X = -40° to 105°C F = -40° to 85°C

Q = VQFN | T = TSSOP

2 = Full Featured < ….. > 0 = Feature Subset

1 = Baseline < ….. > 3 = High-End

ARM® Cortex™-M0

XMC := Industrial Microcontroller Family based on ARM® Cortex™-M Processors

Copyright © Infineon Technologies AG 2013. All rights reserved. Page 4 Naming Convention for 16-bit Family

Example: SAF-XC161CJ-14F20F

Core: Code memory size: XC16 = C166S V2 n*8k Bytes C16 = C166 e.g. 4: 4*8k=32k (blank for ROMless)

CPU Speed: n*1 MHz (blank for Standard speed) Sub-Family Prefix Type

R F F F SA K XC16 1 CJ # # M E A E L

Key Features Package: F = P-TQFP M = P-MQFP Temp. Range: E = P-BGA F = -40/ 85 °C K = -40/ 125°C Code Memory Type: A = -40/ 140°C R = ROM F = Flash E = OTP L = ROMless

Copyright © Infineon Technologies AG 2013. All rights reserved. Page 5 Naming Convention for XC2000 Family

Automotive families: 2: Body 3: Safety Code memory size: 7: Powertrain n*8k Bytes e.g. 8: 8*8k=64k Component specific

Temp. Range Code Mem. CPU Prefix Code Type Series Size Type Freq. Package Bonding

40 F A 66 SA H XC2 y x z M ## F L R 80 K 5X 120

R = Cooper series-# F = -40/ 85 °C F = Flash L = L-QFP ED =MCDS H = -40/ 110°C V = VQFN device K = -40/ 125°C R = TSSOP

3: QFP-64 Package 6: QFP-100 Package 8: QFP-144 Package 9: QFP-176 Package

Copyright © Infineon Technologies AG 2013. All rights reserved. Page 6 Naming Convention for XE166 Family

Example: SAF-XE167F-96F80L

Temp. Range: Industrial series: Code memory size: F = -40/ 85 °C 0: 38 pin n*8k Bytes K = -40/ 125°C 1: 48 pin e.g. 8: 8*8k=64k 2: 64 pin 4: 100 pin 7: 144 pin 9: 176 pin

Temp. Silicon: Memory Mem. CPU Range Prefix Type Version Size Type Freq. Package Bonding

H F 40 M R F G 66 SA XE 16# N # F V R K H 80 L L K 100 U

Variation Members: R = Cooper C166S V2 CPU peripheral F = Flash set Enhanced: R = TSSOP 3/5 Volt IO V = VQFN more memory L = LQFP

Copyright © Infineon Technologies AG 2013. All rights reserved. Page 7 Naming Convention for XC800 Family

Code memory size: XC800 Family product 5V = 5V Supply n*4k Bytes + 3V3 = 3V Supply 2 digits: component specific e.g. 4: 4*4k=16k

F = Flash R = ROM

F X R #F A 5V SA K XC8xx CLM F #R I 3V3 A G L

F = -40°C-85°C C = CAN R = TSSOP X = -40°C-105°C L = LIN F = T/LQFP K = -40°C-125°C M = MDU G = P-DSO A = -40°C-140°C V= VQFN L = -40°C-150°C A = Automotive I = Industrial

Copyright © Infineon Technologies AG 2013. All rights reserved. Page 8 Naming Convention for C500 Family

Example: SAB-C505CA-4EM Code memory size: n*8k Bytes Core: e.g. 4: 4*8k=32k C5 = C500 (custom) (blank for ROMless)

Package: M = P-MQFP R = P-TSSOP G = P-DSO Sub-Family Type

R B S M SA F C5 05CA # E R K L G

Temp. Range: Code Memory Type: B = 0/ 70 °C R = ROM F = -40/ 85 °C S = SRAM K = -40/ 125°C E = OTP L = ROMless

Copyright © Infineon Technologies AG 2013. All rights reserved. Page 9 Mouser Electronics

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Infineon : SAF-XC888C-8FFI3V3AC SAF-XC167CI-32F40FBB-A SAF-XC866-4FRIBE SAF-XC161CJ-16F40FBB SAK- XC167CI-32F40FBB-A SAF-XC164CS-32F40FBB-A FX164CM16F40FBAXT SAF-XC161CJ-16F40F BB SAF- XC164CS-32F40F BB-A SAF-XC167CI-32F40F BB-A SAK-XC167CI-32F40F BB-A SAF-XC888C-8FFI 3V3 AC FX164CS32F40FBBAXT FX167CI32F40FBBAXT