Issues in the Design and Implementation of a Real-Time Garbage Collection Architecture " (1992)
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Iowa State University Capstones, Theses and Retrospective Theses and Dissertations Dissertations 1992 Issues in the design and implementation of a real- time garbage collection architecture William Jon Schmidt Iowa State University Follow this and additional works at: https://lib.dr.iastate.edu/rtd Part of the Computer Sciences Commons Recommended Citation Schmidt, William Jon, "Issues in the design and implementation of a real-time garbage collection architecture " (1992). Retrospective Theses and Dissertations. 10388. https://lib.dr.iastate.edu/rtd/10388 This Dissertation is brought to you for free and open access by the Iowa State University Capstones, Theses and Dissertations at Iowa State University Digital Repository. It has been accepted for inclusion in Retrospective Theses and Dissertations by an authorized administrator of Iowa State University Digital Repository. For more information, please contact [email protected]. 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Ann Arbor, MI 48106 Issues in the design and implementation of a real-time garbage collection architecture by William Jon Schmidt A Dissertation Submitted to the Graduate Faculty in Partial Fulfillment of the Requirements for the Degree of DOCTOR OF PHILOSOPHY Major: Computer Science Members of the Cornmittee; Signature was redacted for privacy. In Charge of Major Work Signature was redacted for privacy. rtmeat Signature was redacted for privacy. Signature was redacted for privacy. For lhe,cSiadua:^ College Iowa State University Ames, Iowa 1992 Copyright © William Jon Schmidt, 1992. All rights reserved. ii TABLE OF CONTENTS 1. INTRODUCTION, HISTORY, AND MOTIVATION 1 1.1 Problem statement 1 1.2 Previous work in this area 4 2. THE ISU REAL-TIME GARBAGE COLLECTION PROJECT 8 2.1 The real-time garbage-collection algorithm 9 2.2 Object types 12 2.3 The garbage-collected memory module architecture 13 2.3.1 Overall system architecture 13 2.3.2 Motivation for the object-space manager 16 2.3.3 Alternatives to the object space manager 17 3. THE OBJECT SPACE MANAGER 19 3.1 Design criteria 19 3.2 Interconnection architecture and command interface 20 3.3 Some design details 24 3.3.1 Command set implementation 28 3.4 Analysis 31 3.4.1 VLSI technologies 31 3.4.2 Transistor counts 32 3.4.3 Wire costs 36 3.4.4 Propagation delays 37 3.5 Improving performance 39 3.6 Other alternatives 42 3.'t Conclusions and future work 45 iii 4. A PROTOTYPE COMPILER IMPLEMENTATION 47 4.1 The C++ compiler 48 4.1.1 The arbiter interface 48 4.1.2 The virtual machine 52 4.1.3 Pointer location descriptions - 55 4.1.4 Special data objects 60 4.1.5 The run-time library 63 4.1.6 Optimizations 64 4.1.7 Compatibility considerations 66 4.1.8 Limitations 69 4.2 The linker and librarian 70 4.3 The dlxsimgc simulator 72 4.3.1 Explanation of statistics 73 4.3.2 Limitations 76 5. PERFORMANCE ANALYSIS 78 5.1 System definitions 78 5.2 Parameters and factors 80 5.2.1 System parameters 80 5.2.2 Workload parameters 81 5.3 Workload 82 5.4 Results of experiments 84 5.4.1 Elapsed CPU cycles 87 5.4.2 Execution latencies 90 5.4.3 CPU instructions executed 92 5.4.4 Allocation latencies 96 5.4.5 Cache performance 99 5.4.6 Difference in costs and latencies 113 5.4.7 Allocations impeded by garbage collection 118 5.4.8 Cycles required for garbage collection 118 5.4.9 Fraction of time that garbage collection is active 119 5.4.10 Bus utilization 122 5.4.11 Bus utilization due to cache invalidation 125 iv 5.4.12 Additional statistics 125 5.5 Additional experiments 127 5.5.1 Partial cache invalidation 127 5.5.2 The effects of garbage-collected memory size 132 5.6 Summary 136 6. ALTERNATIVE FUNCTION CALL MECHANISMS 138 6.1 Implementation 139 6.1.1 Compiling function calls using shared argument blocks .... 148 6.1.2 Compiling function calls using separate argument blocks . 149 6.2 Results of experiments 152 6.3 A solution to the stack manipulation overhead problem 162 6.3.1 Performance model of activation frame caching 163 6.3.2 Preliminary experimental results 170 6.3.3 A new approach to data coherence 174 7. LANGUAGE EXTENSIONS TO SUPPORT SLICE OBJECTS 177 7.1 Syntax and informal semantics 178 7.1.1 Declarations 179 7.1.2 Expressions 179 7.1.3 Possible extensions 181 7.2 Implementation notes 182 7.3 Results of experiments 185 8. CONCLUSIONS AND FUTURE WORK 189 ACKNOWLEDGMENTS 191 BIBLIOGRAPHY 193 V LIST OF TABLES Table 3.1: Transistor cost parameters 33 Table 3.2: Transistor costs by technology 35 Table 3.3: Object space per OSM chip, given chip density and object size 37 Table 3.4: Ratio of OSM chips to DRAM chips 37 Table 4.1: Register usage in the two C++compilers 54 Table 5.1: Elapsed CPU cycles, sfft 88 Table 5.2: Elapsed CPU cycles, lisp 88 Table 5.3: Elapsed CPU cycles, troff 89 Table 5.4: Elapsed CPU cycles, all experiments 89 Table 5.5: Total latencies, sfft (normal CPU cycles) 90 Table 5.6: Total latencies, lisp (normal CPU cycles) 91 Table 5.7: Total latencies, troff (normal CPU cycles) 91 Table 5.8: Total latencies, all experiments (normal CPU cycles) 92 Table 5.9: Total instructions executed, sfft 93 Table 5.10: Total instructions executed, lisp 93 Table 5.11: Total instructions executed, troff 94 Table 5.12: Number of instructions executed, all experiments 94 Table 5.13: Breakdown of arbiter calls 95 Table 5.14: Cost of stack manipulation 96 Table 5.15: Total latencies for allocations, sfft 97 Table 5.16: Total latencies for allocations, lisp 97 Table 5.17: Total latencies for allocations, troff 98 Table 5.18: Total latencies for allocations, all experiments 98 Table 5.19: Instruction cache hits, sfft 100 vi Table 5.20: Instruction cache fetches, sfft 101 Table 5.21: Instruction cache hit rate, sfft 101 Table 5.22: Instruction cache hits, lisp 102 Table 5.23: Instruction cache fetches, lisp 102 Table 5.24: Instruction cache hit rate, lisp 103 Table 5.25: Instruction cache hits, troff 103 Table 5.26: Instruction cache fetches, troff 104 Table 5.27: Instruction cache hit rate, troff 104 Table 5.28: Instruction cache hits, all experiments 105 Table 5.29: Instruction cache fetches, all experiments 105 Table 5.30: Instruction cache hit rate, all experiments 106 Table 5.31: Data cache hits, sfft 107 Table 5.32: Data cache fetches, sfft 108 Table 5.33: Data cache hit rate, sfft 108 Table 5.34: Data cache hits, lisp 109 Table 5.35: Data cache fetches, lisp 109 Table 5.36: Data cache hit rate, lisp 110 Table 5.37: Data cache hits, troff 110 Table 5.38: Data cache fetches, troff Ill Table 5.39: Data cache hit rate, troff Ill Table 5.40: Data cache hits, all experiments 112 Table 5.41: Data cache fetches, all experiments 112 Table 5.42: Data cache hit rate, all experiments 113 Table 5.43: Total cycles difference between costs and latencies, sfft ... 115 Table 5.44: Total cycles difference between costs and latencies, lisp . 115 Table 5.45: Total cycles difference between costs and latencies, troff . 115 Table 5.46: Total cycles difference between costs and latencies, all exper iments 116 Table 5.47: Wasted cycles for the standard GC configuration 116 Table 5.48: Fraction of time wasted by protocol, sfft 116 Table 5.49: Fraction of time wasted by protocol, lisp 117 Table 5.50: Fraction of time wasted by protocol, troff 117 vii Table 5.51: Fraction of time wasted by protocol, all experiments 117 Table 5.52: Number of allocations impeded by GC, all experiments ... 119 Table 5.53: Total cycles required for GC, sfft 120 Table 5.54: Total cycles required for GC, lisp 120 Table 5.55: Total cycles required for GC, troff 120 Table 5.56: Total cycles required for GC, all experiments 121 Table 5.57: Fraction of time GC is active, sfft 121 Table 5.58: Fraction of time GC is active, lisp 121 Table 5.59: Fraction of time GC is active, troff 122 Table 5.60: Fraction of time GC is active, all experiments 122 Table 5.61: Bus utilization, sfft 123 Table 5.62: Bus utilization, lisp 123 Table 5.63: Bus utilization, troff 124 Table 5.64: Bus utilization, all experiments 124 Table 5.65: Bus utilization due to cache invalidation, sfft 125 Table 5.66: Bus utilization due to cache invalidation, lisp 126 Table 5.67: Bus utilization due to cache invalidation, troff 126 Table 5.68: Bus utilization due to cache invalidation, all experiments .