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Hands-On Haswell/Broadwell Platform and SoC

Training

Let MindShare Bring “Hands-On Intel Haswell/Broadwell Platforms and SoCs” to Life For You

This course covers topics related to Intel’s latest Haswell and Broadwell x86 platform and system-on-a-chip (SoC) implementations. The term platform is used here to indicate traditional desktop, workstation, or server systems based on one or more CPUs and some form of chipset support logic such as a (PCH). SOCs are used in mobile and other small form-factor systems where an additional level of hardware integration is used to further shrink the overall footprint to one primary IC and provide additional opportunities to reduce system power consumption and heat. A number of variants of the 22nm Haswell CPU and SoCs are released and the architecturally similar 14nm Broadwell is to follow as part of the Intel tick-tock product release strategy. Emphasizing high performance and low power, Haswell/Broadwell platforms and system-on-a-chip (SoC) implementations are found in applications ranging from tablets and ultrabooks at one end of the spectrum to energy efficient workstations and servers at the other end.

Many CPU/PCH features, including integrated bridges and controllers for their external interfaces, are managed as PCI functions—each with some combination of IO, MMIO, and PCI Configuration Space registers which must be initialized by BIOS or other software. Hands-on lab exercises integrated into this course enable students to examine the decoded contents of PCI, IO, and MMIO registers, CPU model-specific registers (MSRs), as well as main memory data structures using MindShare’s Arbor software tool. The exercises allow students to determine both the capabilities and the manner in which CPUs, chipsets, and devices are actually configured. In addition to previously captured system scans distributed with Arbor software, students may use Arbor to scan their local systems, read/modify registers, and save scan results for later sharing and off-line review.

Who Should Attend?

This four-day course is intended for Hardware, Software, Board-Design, Validation and Verification Engineers interested in a broad introduction to the Haswell/Broadwell CPU internal architecture as well as the other support logic required to implement a complete system. The methods used to interface processors to support logic are a bit different for SoCs than for systems with discrete chipset components, but the basic elements are the same. Note that while this four-day course introduces all of the major Haswell/Broadwell system elements, MindShare also offers comprehensive training courses focusing on specific topics: Haswell/Broadwell CPU hardware, x86 software, DRAM architecture, and protocol details for architectures (PCIe, USB, SATA, QPI, etc.).

Course Length: 4 Days

Course Outline:

• Background: Intel Haswell/Broadwell Architecture o Generic System Elements: Processor, Main Memory, Input/Output (IO), Interconnects o Evolution of Intel x86 Performance CPU Platforms o Haswell/Broadwell Platform Types ! Mobile ! Desktop ! Data Center and Connected Systems ! Workstation Platforms ! Microserver Platforms • Review of Platform Examples o Intel Core i3/i5/i7 Desktop o Intel Core i3/i5/i7 SoC Mobile o Intel Xeon E3 single-CPU Workstation/Server o Intel Xeon E5 Multi-CPU Workstation/Server o Intel Xeon E7 Multi-CPU Server o Class exercise: Intel ARK Platform Feature Comparison 800-633-1440 1-800-633-1440 [email protected] www.mindshare.com

• System Address Maps o Memory Addresses o IO Addresses o PCI Configuration Space Addresses • CPU Internal Architecture: An Overview o Dedicated vs. Shared Internal CPU Resources o Instruction Pipeline o Execution Units o Registers o Caches o Processor Graphics And Display Support o CPU System Agent Functions o Arbor Lab: Examining CPU Architectural Features • System Memory Interface and DRAM o Integrated Memory Controller (IMC) o IMC Fast Memory Access (Intel FMA Technology) o Number of DRAM Channels o DIMM Types, Maximum Total DRAM Supported o DRAM Channel Modes ! Single-Channel Mode ! Dual-Channel Mode (Intel Flex Memory Technology) ! Dual-Channel Symmetric (Interleaved) Mode o DRAM Timing Parameters and Total Bandwidth o Memory Interface Data Scrambling o Implications of a Non-unified Memory Architecture (NUMA) • Platform Controller Hub (PCH) General Features o Integrated Bridges and Controllers o PCH Legacy Hardware Support o Platform Clock Generation and Distribution o High Performance Event Timers (HPET) o System Management ! vPro Features ! Manageability Engine (ME) ! Total Cost of Ownership (TCO) initiative ! Active Management Technology (AMT) o Arbor Lab: Platform Controller Hub Configuration • Overview of Key Platform Bus Interfaces (key features of each interface and the CPU/PCH host side controller/bridge that supports it) o Peripheral Component Interconnect (PCI) Bus ! 33MHz Legacy, Parallel IO Bus (some platforms) ! Multiple Bus Masters o PCI Express (PCIe) ! Gen1/Gen2/Gen3 Protocols ! CPU Support ! PCH Support o Direct Media Interconnect (DMI) ! Dual-simplex CPU-PCH Connection ! Bandwidth Considerations o QuickPath Interface (QPI) ! Coherent Bus (Multiple-Socket CPU Systems) ! Signaling Environment ! Traffic Types ! Snoop Protocol o Platform Environmental Control Interface (PECI) ! Motivations for PECI ! PECI Usage Model for CPU, BMC, SIO o Simple Serial Transport (SST) Bus ! Server/Workstation Platforms Only ! Thermal Sensors, Voltage Sensors, Fan Speed Control o Universal Serial Bus (USB) 2.0 ! Integrated PCH EHCI USB 2.0 Host Controllers and Rate Matching Hubs (RMH) ! Support For Low, Full, High Speed USB Downstream Devices/Hubs o Universal Serial Bus (USB) 3.0 800-633-1440 1-800-633-1440 [email protected] www.mindshare.com

! Integrated PCH xHCI USB 3.0 Host Controller ! SuperSpeed USB 3.0 Devices/Hubs ! Backward Compatible with USB 2.0 Devices/Hubs o SATA ! Dual Integrated PCH SATA Host Controllers/Six Independent Ports Total ! Supported SATA Operational Modes/Rates ! Intel Rapid Storage Technology (RST) o LAN ! Integrated GbE Controller Interfaces to External LAN Connect Device ! 10/100/1000 Mb/s (via PCIe Interface to LAN Connect Device) ! Manageability 10Mb/s Ethernet (via SMBus Interface to LAN Connect Device) o (SMBus) ! Single Integrated PCH SMBus Host Controller ! PCH acts as SMBus Master or Slave ! Usage Model (with Other Platform Management elements) o Low Pin Count (LPC) Bus ! Legacy x4 Bus managed with PCH LPC Bridge ! LPC Bus Devices ! LPC Bus PIO and DMA Protocol Basics o Serial Peripheral Interface (SPI) bus ! Four-wire Bus Supports 20/30/50 MHz devices ! Master-Slave Protocol ! SPI Flash Regions: CPU BIOS Software, Manageability Engine , Ethernet Settings, Platform Data • Platform Interrupt Handling o Background o Interrupt Types o The Controllers ! PCH 8259 PICs and IOAPIC ! CPU Local APICs o Message Signaled Interrupt (MSI/MSI-X) Basics o CPU Core Interrupt Servicing • Power Management o ACPI Overview o CPU Power Management Features ! Core & Device C-States, P-States ! Power Management MSRs ! Role of the Power Control Unit ! Enhanced Intel Speed Step ! TurboBoost o PCH Power Management Features ! Power Management Registers ! Initiating Sleep State Transitions ! Smart Connect ! Rapid Start o IMC and DRAM Power Management ! Integrated Memory Controller (IMC) ! DRAM Power Management o Graphics Power Management • Thermal Management o CPU Thermal Management Overview ! TCC (Thermal Control Circuit) ! DTS (Digital Thermal Sensors) ! Thermal Management MSRs ! Adaptive Thermal Monitor (ATM) and TM1/TM2 ! Thermal Interrupts o PCH Thermal Management ! Thermal Sensors ! Trip Points and Thermal Throttling ! Reporting Thermal Data Over SMLink o DRAM Thermal Management o Arbor Lab: Platform Power/Thermal Management (combined lab) 800-633-1440 1-800-633-1440 [email protected] www.mindshare.com

• Other Platform Topics o Platform Initialization ! Impact of Platform Reset ! First Code Access ! Generic Boot Sequence ! Fast Boot ! Cache as RAM (CaR) ! Microcode Update ! PCI Enumeration ! Loading The OS o Virtualization Overview ! Motivation ! VT-x Features ! VT-d Features

Recommended Prerequisites: some background in computer architecture is helpful

Course materials: 1) Downloadable PDF version of course presentation slides 2) MindShare’s “x86 Instruction Set Architecture” eBook by Tom Shanley 3) MindShare Arbor software learning/test/debug tool used for hands-on class exercises