Self-Interference in Full-Duplex 2×2 MIMO Transceivers: Channel Characterization and RF/Analog Cancellation

Fei Chen

Department of Electrical & Computer Engineering McGill University Montreal, Canada

April 2017

A thesis submitted to McGill University in partial fulﬁllment of the requirements for the degree of Master of Engineering. c 2017 Fei Chen

2017/04/07 i

To my parents, with all my love. ii

Abstract

Spectrum resources become more and more scarce over last few decades, leading to the sig- nificance of effectively utilizing and allocating spectrum. Recently, in-band full-duplex (FD) operation has gained more attention as a potential approach of enhancing spectrum efficiency by simultaneous transmission and reception over the same frequency. One of the most challenging problems in FD communications is the existing strong self-interference (SI) from transmitter and co-located receiver. The SI must be suppressed to a sufficiently low level by a combination of antenna, radio frequency (RF) and baseband cancellation stages so that the intended signal received from the distant transmitter can be reliably demodulated. In this work, we study the SI-channel characteristics and develop a high performance RF/Analog self-interference canceller (SIC) for a 2×2 MIMO FD transceiver. First of all,SI cancellation technique requires knowledge ofSI propagation characteristics and models. We investigate of the wideband SI-channel propagation characteristics of a 2×2 MIMO with dual-polarized antennas. The SI-channels are measured at center frequency of 2.45GHz with 500MHz bandwidth in various environments: anechoic chamber, laboratory room, and corridor. The measurement results show that the SI-channel can be represented by a multipath model composting of two segments: a quasi-static internal SI-sub-channel due to the particular Tx/Rx antenna structure and a time-varying and dynamic external SI-sub-channel due to possible reflections from the surrounding objects. Also, the external SI-channel exhibits cluster arrival features and can be described by a modified Saleh-Valenzuela (S-V) model. In addition, wea develop RF/Analog SIC to suppress the quasi-static internal SI-sub-channel. We discuss SIC design considerations at the system level. Specifically, we consider coupler selection to minimize the noise-figure increase and derive the linearity requirements of RF/Analog SIC, including the component linearity requirements, so that the nonlinear distortion introduced by RF/Analog SIC will not significantly degrade SNR after all the cancellation stages. We propose high-linear RF/Analog SIC with custom-made components. Measurements and simulations with followed digital cancellation stages show that proposed RF/Analog SIC can provide 60- 80dB cancellation and negligible SNR degradation (0.3dB) due to nonlinear distortion. Moreover, we specifically focus on the study and design of delay/phase shift module, to meet the RF/Analog SIC linearity requirements. This delay/phase shift module is composed of a RF switched true time Delay line (switched TTD) and an analog variable reflective type phase shifter (RTPS). Measurement results show significant improvement over off-the-shelf products, iii and other existing prototypes, in terms of linearity. iv

Sommaire

Les ressources du spectre sont de plus en plus rares au cours des dernieres` decennies,´ ce qui con- duit a` l’importance d’utiliser et d’allouer efficacement le spectre. Recemment,´ la transmission en duplex integral´ (FD) a gagne´ une grande d’attention comme une methode´ qui peut poten- tielle ameliorer´ l’efficacite´ spectrale par la transmission et la reception´ simultanee´ sur la memeˆ frequence.´ L’un des problemes` majeurs de la transmission en FD est l’auto-interference´ (self- interference ou SI) forte resultante´ de l’emetteur´ et le recepteur´ co-situe.´ La SI doit etreˆ reduite´ a` un niveau suffisamment faible en combinant des techniques de reduction´ au niveau des antennes, au niveau radio frequence´ (RF) et en bande de base pour graduellement attenuer´ la SI. Dans ce travail, nous etudions´ les caracteristiques´ du canal de la SI et nousd eveloppons´ un mecanisme´ d’annulation de la SI operant´ dans le domaine RF/Analogique pour un emetteur-r´ ecepteur´ a` deux antennes (2×2 MIMO). Tout d’abord, la technique d’annulation de la SI requiert la connaissance et la caracterisation´ du canal de propagation de la SI que nous etudions´ pour un systeme` MIMO 2x2 large bande avec des antennes a` polarisation double. Les canaux SI sont mesures´ pour une frequence´ cen- trale de 2,45GHz avec une bande passante de 500 MHz dans divers environnements: chambre anecho´ ¨ıque, salle de laboratoire et couloir. Les resultats´ de mesure montrent que le canal de la SI peut etreˆ represent´ e´ par des composants multitrajets a` deux segments: une composante interne quasi-statique dependante´ de la structure des antenne et une composante provenant des reflexions´ a` partir des objets environnants. De plus, nous montrons que cesr eflexions´ peuvent etreˆ decrit´ par un modele` modifie´ de Saleh-Valenzuela (S-V). En outre, nous developpons´ un schema´ d’annulation de la SI (SIC) en RF/Analogique pour supprimer la SIr esultante´ du reflextion interne quasi-statique. Nous discutons des considerations´ de la conception du SIC au niveau du systeme.` En particulier, nous etudions´ la selection´ du coupleur dans le but de minimiser de la figure de bruit et nous derivons´ la nonlinearit´ e´ introduite par le RF/Analogique SIC, pour determiner´ le caractere` nonlineaire´ des composantes, qui garantie que le RF/Analogique SIC ne degradera´ pas le SNR. Nous proposons un SIC RF/Analogique hautement lineaire´ avec des composants sur mesure. Des mesures et des simulations avec des etages´ d’annulation numeriques´ suivis montrent que le RF/Analogique SIC propose´ peut fournir une annulation de 60-80dB et une degradation´ negligeable´ de la SNR (0.3dB) due a` une distorsion non-lineaire.´ De plus, nous nous concentrons particuliairement sur l’etude´ et la conception du module de v delai/d´ ephasage,´ pour repondre´ aux exigences de la linearit´ e´ du RF/Analogique SIC. Ce module de delai/d´ ephasage´ est compose´ d’une ligne de temporisation a` temps reel´ commutee´ RF (TTD commutee)´ et d’un dephaseur´ de type analogique a` reflexion´ variable (RTPS). Les resultats´ des mesures montrent une amelioration´ significative par rapport aux solutions disponibles sur le marche´ et aux autres prototypes existants, en termes de linearit´ e.´ vi

Acknowledgments

I would like to express my deepest and sincere gratitude to my supervisor, Professor Tho Le- Ngoc, for his patience, excellent guidance, encouragement during my M.Eng. studies at McGill University. Particularly, I appreciate his devotion to this research, his broad knowledge, sharp judgment, enthusiasm. My deep appreciation goes to the Broadband Communications Research Lab (BCRL) Man- ager/Engineer, Mr.Robert Morawski, for his patient and productive research coaching and col- laboration in assisting me to complete this research work. He has helped me countless times in practical issues of my research and I have learned a great deal from him. I also would like to thank Mr.Thanh Ngon Tran for his kind assistance and helpful discussions. I would like to thank ﬁnancial support received from the Natural Sciences and Engineering Research Council of Canada (NSERC) and Huawei Technologies. I am deeply grateful to all my colleagues and friends in BCRL. They made my journey at McGill unforgettable. I would like to thank Hak Hyun Lee, Ruozhu Li, Ruikai Mai, Ahmed Masmoudi, Seonghwan Kim, Xiaowei Wang, Pragyan Hazarika. I am also thankful to my friends at McGill and in Montreal, especially, Bonan Zhang, Ge Li, Ziyin Chen, Zheng Liu, Yue Cai, Baoguang Xu, Yiqing Xiao, Randy Li, Yuhao Mao. Finally, my deepest and sincere gratitudes are devoted to my parents and my beloved girl- friend for all their immense love, presence and support. vii

Contents

1 Introduction 1 1.1 Full-Duplex Wireless Communications and Key Challenges ...... 1 1.2 Applications of Full-Duplex Communications ...... 4 1.2.1 Full-duplex Base Station or Relay ...... 4 1.2.2 Device-to-Device (D2D) Communication ...... 4 1.2.3 Two-Tier Cognitive Radio Networks ...... 5 1.2.4 Improve Security of Wireless Data Transfer ...... 5 1.2.5 Other Applications...... 5 1.3 Thesis Contributions and Organization ...... 6

2SI Channel Characteristics andSI Cancellation Techniques: A Review 8 2.1 Self-Interference Channel Characteristics and Modeling ...... 8 2.2 Self-Interference Cancellation Techniques ...... 9 2.2.1 Antenna or Propagation Domain Suppression ...... 11 2.2.2 RF Domain Self-Interference Cancellation ...... 12 2.2.3 Baseband Domain Self-interference Cancellation ...... 16 2.3 Chapter Summary ...... 16

3 SI Channel Characterization and Modeling 18 3.1 Introduction ...... 18 3.2 Measurement Setup ...... 19 3.2.1 Antenna ...... 19 3.2.2 Wideband Channel Sounding System and Data Acquisition ...... 22 3.2.3 Measurement Environments ...... 23 3.2.4 Measurement Procedure ...... 25 Contents viii

3.3 Measurement Results and SI-channel Modeling ...... 26

3.3.1 SI-channel PDPTR Trends ...... 26 3.3.2 SI-Channel Impulse Response Models and Parameters ...... 27 3.3.3 Time Dispersion Characteristics ...... 35 3.4 Concluding Remarks ...... 38

4 RF/Analog Self-Interference Canceller for 2×2 MIMO Full-Duplex Transceiver 40 4.1 Introduction ...... 40 4.2 Multi-Tap Delay Line RF/Analog SIC Structure and Design Considerations . . . 42 4.2.1 Structure ...... 42 4.2.2 Coupler Consideration ...... 42 4.2.3 Nonlinearity Consideration ...... 44 4.2.4 Tuning Algorithm ...... 49 4.2.5 Bandwidth ...... 52 4.2.6 Quantization Effects of components in RF/Analog SIC ...... 53 4.3 Implemented Prototypes ...... 57 4.3.1 Prototype 1 ...... 58 4.3.2 Prototype 2 ...... 59 4.4 Measurement Results ...... 62 4.4.1 Anechoic Chamber Measurements ...... 63 4.4.2 Indoor Environment Measurements ...... 64 4.4.3 Nonlinear Distortion Characteristic Measurements ...... 66 4.5 Concluding Remarks ...... 68

5 High-Performance Tunable Delay/Phase Shift Module 70 5.1 Introduction ...... 70 5.2 Delay/Phase Shift module Architectures and Topologies ...... 71 5.2.1 Switched True Time Delay (Switched TTD) Phase Shifter ...... 71 5.2.2 High Pass-Low Pass Type Phase Shifter ...... 73 5.2.3 Reﬂective-Type Phase Shifter (RTPS) ...... 73 5.2.4 Periodically Loaded Line phase shifter ...... 76 5.3 Target Speciﬁcations, Design Topologies Selections, and Considerations . . . . . 78 5.3.1 Switched TTD Phase Shifter...... 80 Contents ix

5.3.2 RTPS...... 81 5.4 Implemented Prototype and Characterizations ...... 84 5.4.1 Switched TTD Measurements ...... 84 5.4.2 Variable RTPS Measurements ...... 87 5.5 Concluding Remarks ...... 90

6 Conclusions 92 6.1 Summary ...... 92 6.2 Potential Future Research ...... 93

A OIP3, IIP3 and IIP3 Derivation for SIC requirements 95 A.1 OIP3 and IIP3 Background ...... 95 A.2 IIP3 Derivation for SIC requirements ...... 96

B Group Delay Measurement Accuracy 98

References 100 x

List of Figures

1.1 Illustration of the SI in a full-duplex point-to-point wireless communication system.2 1.2 Illustration operation of full-duplex base station (BS) and relay ...... 4

2.1 Illustration of SISO self-interference cancellation applied in 3 domains. (1) An- tenna domain cancellation. (2) RF domain cancellation: RF/Analog, RF/Digital. (3) Bseband digital cancellation...... 10 2.2 Antenna domain suppression configurations: (a) Dual-antenna configuration (b) Shared single antenna configuration via a circulator ...... 11 2.3 Various typical structures of RF/Analog self-interference cancellation techniques. 13

3.1 A dual-polarized antenna: (a) prototype, (b) simulation model cut view with dimensions (in mm)...... 20 3.2 Typical antenna far-field Co-and Cross polarization power ratio measurement at 2.5GHz ...... 21 3.3 Wideband 2×2 MIMO SI channel sounding system...... 22 3.4 Measurement setup and layout in various environments ...... 24 3.5 Measured PDP comparisons for three scenarios: anechoic chamber, lab, and corridor...... 27 3.6 Measured Lab PDP and S-V model fitting with exponential MPCs decay . . . . . 31 3.7 Measured corridor PDP and S-V model fitting with power law MPCs decay . . . 32

3.8 Path power decay rates: γ > 0 (exponential), nl > 0 (power-law) versus cluster

arrival delay Tl ...... 32 3.9 K-S test pass rate for different distributions at 5% signiﬁcant level ...... 34 3.10 Small-scale fading CDFs of 4 SI channels at ﬁtted with lognormal distribution at delay bin of 34ns in laboratory room...... 35 List of Figures xi

3.11 CDFs of coherence bandwidth measured in anechoic chamber, laboratory, corridor 36 3.12 CDFs of RMS delay spread measured in anechoic chamber, laboratory, corridor . 37 3.13 Fit curves of RMS delay spread versus coherence bandwidth: Plotted in log-scale 38

4.1 Generic tapped delay line canceller diagram...... 43

4.2 OIP 3 requirement plot of RF/Analog SIC for varied (PTx − AS) and TNF = 0, 2, 4, 6dB according to (4.6) ...... 45

4.3 SNR degradation merely due to CCP for different received SI power( PTx −AS) = -25, -20, -15, -10dBm and TNF = 0, 2, 4, 6dB...... 46

4.4 Illustration of different power levels in 20MHz OFDM with +30dBm PTx : tar-

geted CCP (-105.7dBm) 10dB below the receiver noise ﬂoor (-95.7dBm). PIMD3 is -105.7dBm-13.3dB = -119dBm ...... 47 4.5 Overall IIP 3 contour for varied IIP 3 of attenuator and delay/phase module, red curve represents the overall IIP 3 78dBm requirement of SIC to achieve the nonlinear distortion target. The combination around corner in the contour is the optimal...... 48 4.6 Optimization surface of 2-tap RF/Analog SIC with ﬁxed optimal attenuation and swept delay, revealing that local optimas are repeated at a period of reciprocal of center frequency...... 51 4.7 The effects of different bandwidths, and different number of taps, on the self- interference cancellation performance when the carrier frequency is 2.27GHz. . . 54 4.8 Simulated variable attenuator step size versus cancellation performance for 10MHz, 20MHz, 40MHz, bandwidth under the assumption of no phase error, 2-tap RF/Analog SIC...... 55 4.9 Simulated variable phase/delay step size versus cancellation performance for 10MHz, 20MHz, 40MHz bandwidth under the assumption of no attenuation error, 2-taps RF/Analog SIC...... 56 4.10 Cancellation performance contours for various attenuator and phase/delay step sizes. Phase/delay module with 0.4◦ and attenuator with 0.02dB are required for keep cancellation reduction less than 0.5dB...... 57 4.11 RF/Analog SIC prototype1 box...... 58 4.12 Operation schematic of the entire RF/Analog SIC prototype1 for FD 2×2 transceiver 59 4.13 RF/Analog SIC prototype2 stack structure and interconnections ...... 61 List of Figures xii

4.14 Main RF Board Block Diagram and Fabrication Prototype ...... 62 4.15 RF/Analog SIC prototype test system setup...... 63 4.16 SI Spectra for 2×2 MIMO RF/Analog SIC performance of 4 separated SI channels measured in anechoic chamber...... 64 4.17 SI Spectra for 2×2 MIMO RF/Analog SIC performances of combined SI channels measured in anechoic chamber...... 65 4.18 SI Spectra for 2×2 MIMO RF/Analog SIC performances of 4 separated SI channels measured in realistic indoor environment...... 65 4.19 SI Spectra for 2×2 MIMO RF/Analog SIC performances of combined SI channels measured in realistic indoor environment...... 66 4.20 Measured typical OIP 3 for two prototypes ...... 67 4.21 Simulated residualSI power after all cancellation stages...... 69

5.1 Schematic diagram of switched true-time delay line ...... 72 5.2 Schematic diagram of Π and T networks ...... 74 5.3 Switched high pass–low pass phase shifters ...... 74 5.4 Schematic diagram of RTPS operation...... 75 5.5 Schematic periodically loaded line phase shifter...... 77 5.6 Schematic periodically loaded line phase shifter...... 78 5.7 Schematic diagram of switched true-time delay line...... 80 5.8 Reﬂective load with series inductor...... 81 5.9 Entire delay/phase shift module prototype...... 84 5.10 Measured input (S11) and output (S22) return loss of Switched TTD for 0-1260ps delay setting...... 85 5.11 Measured insertion loss of Switched TTD for 0-1260ps delay setting...... 85 5.12 Measured true time delay at 1.7-2.7GHz normalized to state 0 (0ps) ...... 86 5.13 Measured delay RMS error and amplitude RMS error over 1.7-2.7GHz...... 86 5.14 Measured IIP3 of switched TTD verus delay setting...... 88 5.15 Measured insertion loss over 0-20 control voltage...... 88 5.16 Measured input (S11) and output (S22) return loss over 0-20 control voltage. . . 89 5.17 Measured unwrapped phase response over 0-20V control voltage...... 89 5.18 Measured IIP 3 verus Control voltage for RTPS only,as well as entire module at maximum and minimum switched TTD setting ...... 90 List of Figures xiii

A.1 Straight-line relationship between IMD3 and the fundamental...... 95

B.1 Accuracy of group delay measurement at 1.7GHz ...... 98 xiv

List of Tables

3.1 Antenna Speciﬁcations Summary ...... 19 3.2 VNA Setting Parameters ...... 25 3.3 The modiﬁed S-V model parameters for the SI-sub-channels in 2 environments (ii) and (iii) ...... 33

4.1 IIP 3 requirements of each component in the RF/Analog SIC ...... 49

5.1 High Pass - Low Pass Type Phase Shifter Design Equations ...... 73 5.2 Design Target Speciﬁcations and Comparisons with Off-the-shelf Delay/phase Modules ...... 79 5.3 Comparison Target Speciﬁcations with Measured Prototype ...... 91

B.1 VNA Group delay measurement parameters ...... 99 xv

List of Acronyms

ADC Analog-to-digital converter AP Access point AS Antenna suppression BS Base station CCP Co-Channel power CCPR Co-Channel power Ratio CDF Cumulative distribution function D2D Device-to-device DAC Digital-to-analog converter dB Decibel dBm Decibel-milliwatts FD Full-Duplex FDD Frequency-division duplex FFT Fast fourier transform FGCPW Finite grounded coplanar waveguides FIR Finite impulse response FSPL Free space path loss IDFT Inverse discrete fourier transform IF Bandwidth Intermediate frequency bandwidth IFFT Inverse fast fourier transform List of Terms xvi

IIP Input intercept point IMD3 Third-Order inter-modulation distortion IMR Inter-modulation ratio LNA Low-noise-amplfier LTE Long-term evolution MAC Media access control MEMS Microelectromechanical Systems MIMO Multiple-input multiple-output MMIC Monolithic microwave integrated circuit NF Noise figure OFDM Orthogonal frequency-division multiplexing OIP Output intercept point PA Power amplifier PCB Printed circuit board PDP Power delay profile PIM Passive inter-modulation distortion PSO Particle swarm optimization QAM Quadrature amplitude modulation RF Radio frequency RMS Root mean square RTPS Reflective type phase shifter Rx Reception SI Self-interference SIC Self-interference cancellation SINR Signal-to-interference noise ratio SISO Single-input single-output SNR Signal-to-noise ratio SP3T Single pole three throw List of Terms xvii

Switched TTD Switched true time delay TDD Time-division duplex Tx Transmission UEs User equipments UWB Ultra-wide band VGC Variable-Gain-Control VNA Vector network analyzer VSG Vector signal generator VSWR Voltage standing wave ratio WLAN Wireless local area network 1

Chapter 1

Introduction

Wireless communications have experienced tremendous growth over last few decades, and spectrum becomes more and more scarce. Thus, effectively utilizing and allocating of spectrum is of beneficial for nowadays wireless communications applications. Several techniques have been proposed for enhancing spectral efficiency, e.g., multilevel QAM modulation [1], massive MIMO [2], cognitive radio [3]. In the past few years, in-band full-duplex (FD) communications has gained more attention for its potential doubled spectral efficiency by enabling simultaneous transmission and reception over the same frequency slot. In this chapter, to start with, we intro- duceFD communication and its challenging problems. And then, its potential applications and advantages ofFD are discussed. Finally, we present contributions and organization of this thesis.

1.1 Full-Duplex Wireless Communications and Key Challenges

Traditionally, wireless communication systems are based on the half-duplex (HD) operation in which the transmitted and received signals must be separated either in different time-slots, i.e., time-division duplex (TDD), or in different frequency-band, i.e., frequency-division duplex (FDD), or in different orthogonal spectrum spreading codes, to avoid strong self-interference (SI) from its own transmission. The past few years have witnessed fast growing deployment of wireless communications applications, spectrum become one of the scarcest resources.FD communications consider simultaneous transmission and reception over the same frequency to

2017/04/07 1 Introduction 2 enhance the spectral efﬁciency.

Fig. 1.1 Illustration of the SI in a full-duplex point-to-point wireless communication system.

One of the most challenging problems in FD communications is the existing strong self- interference (SI) between the co-located transmitter and receiver, as illustrated in Fig. 1.1. SI travels much shorter distance than the remote intended signal, so SI power can be much higher than the intended signal power. For instance, for two FD nodes distant by 1000 meters, in Fig. 1.1, the intended signal from the remote node is attenuated by roughly 100 dB at 2.4GHz due to the path loss. If the isolation between co-located transmitter and receiver is 20dB, the SI is 80dB greater than the intended received signal. Self-interference cancellation (SIC) must be applied to suppress the SI below a sufficiently low level. Otherwise, residual in-band SI will degrade the effective SNR of intended signal (SINR, signal-to-interference-noise ratio), leading to performance degradation. Usually, 90 to 120dB cancellation is required. For instance, for 20MHz LTE with 20dBm transmitted power, the thermal noise power is -101dBm=174dBm/Hz+10log10(20MHz), and with an assumed receiver noise figure of 10dB, the overall receiver noise floor is -91dBm. Hence the SI power needs to be less than -91dBm at the receiver in order not to increase the receiver noise and interference 1 Introduction 3 and thus maximize sensitivity in the RX chain [4]. Thus, at least 110dB cancellation is required. However, it is difficult, if not impossible, to achieve this target of 110dB by SIC in a single stage. Let us justify this with the example above. For convenience, we assume that there is 20 dB isolation between the transmit and the receive paths of the same transceiver. Considering two transceivers distant by 1000 meters, the intended signal coming from the distance transceiver is attenuated by approximately 100dB, so the intended signal of -80dBm=+20dBm-100dB. If SIC is done only at baseband via a digital approach, strong SI will pass through entire receiver chain, including low-noise-amplifier (LNA), ADC, and down-converter. First of all, the aforementioned high power SI possibly saturates the LNA, leading to gain compression and nonlinear distortion. Typical IMD3 of a LNA is 40dBc so that nonlinear distortion yields to -40dBm = (20dBm - 20dB) - 40dBc, which is 40dB higher than the intended signal (-80dBm), blocking the detection of the intended/received signal. In addition, the quantization noise of ADC will be a major bottleneck for the cancellation. In fact, the ADC input power is scaled by variable-gain-control (VGC), and full range of ADC is used to avoid clipping of signal. The signal-to-quantization- noise ratio (SNR) of the ADC is

SNR = 6.02 × b + 4.76 − P AP R (1.1) where b is the number of bits at the ADC, P AP R is the peak-to-average power ratio. So for a 12 bit ADC and LTE signal with 12dB P AP R, the SNR of ADC is roughly 55dB. In this case, the SI power passing through receiver is 80dB higher than intended signal, the resulting quantization noise is 15dB greater than intended signal so that intended signal will not be converted correctly. The aforementioned problems can be solved by mitigating power of SI prior to LNA and the ADC, i.e., RF SIC prior to LNA/ADC. Recently, several SI-cancellation techniques have been proposed for FD systems, which adopts a combination of antennas techniques,RF techniques and baseband techniques. Details will be discussed in Chapter 2. 1 Introduction 4

1.2 Applications of Full-Duplex Communications

1.2.1 Full-duplex Base Station or Relay

FD can be applied to communications between UEs and BS or relay, as illustrated in Fig. 1.2.BS operates inFD mode, transmitting signal to half-duplex UE on the downlink and receiving signal from half-duplex UE on the uplink. Compared with half-duplex BS where transmitted signal and received signal are separated either by different frequency bands or time slots,FD BS enables simultaneous transmissions and receptions from UEs. In the presence of aFD UE,FD BS can transmit and receive signal simultaneously from this UE. Besides, the same idea is applied for FD relay station, which receives and forwards simultaneously data between two UE terminals, increasing the spectral efﬁciency or throughput of network.

(a) Full-duplex base station (BS) with half-duplex (b) Full-duplex relay with half-duplex users and full-duplex users

Fig. 1.2 Illustration operation of full-duplex base station (BS) and relay

1.2.2 Device-to-Device (D2D) Communication

When the two user equipments (UEs) are in proximity compared to base station (BS), they can communicate with each other directly, increasing spectral and power efﬁciency since UEs do not need to interface withBS thenBS transmits signal to other UEs. Usually, D2D communication is in short range so the path loss of intended signal is much smaller than base station (BS) case, 1 Introduction 5 resulting in lower SI cancellation requirement to maintain certain SINR level. For FD applicable in D2D, the SI canceller can be fabricated as a very compact monolithic microwave integrated circuit (MMIC) chip and integrated into the UE.FD D2D communications will be able to either enhance spectral efﬁciency or increase the system throughput [5, 6].

1.2.3 Two-Tier Cognitive Radio Networks

One of the most difﬁcult problems in two-tier cognitive radio networks is that the secondary node needs to know that status of channel to see if the channel is occupied by primary node or not [7]. In conventional half-duplex systems, the secondary node must stop the transmissions periodically to detect status of channel, leading to inefﬁciencies. However, if the secondary node operates in full-duplex mode, it will be able to transmit while listening to the status of channel so that it can interrupt transmissions on the instant as long as primary terminal starts to occupy the channel.

1.2.4 Improve Security of Wireless Data Transfer

Another application ofFD communications is to enhance wireless secrecy rate. Traditionally, for half-duplex receiver, an auxiliary transmitter is required to send jamming signal to degrade the signal quality received by the eavesdroppers, securing transmission between the legitimate transmitter and receiver [8–10]. But FD transceiver can be used as jammer for eavesdropper while receiving intended signal from legitimate transmitter.

1.2.5 Other Applications

Besides mentioned above, practicalFD technology can solve several challenging current problems in wireless network [11]. First of all, the hidden terminal problem occurs when a node is visible from an access point (AP), but not from other nodes interfacing with this AP, leading to collision at the AP. We assume that all the nodes in the network operate in full-duplex mode. One node starts to transmit signal to AP while receiving signal from AP. Another node can hear the transmission from the AP and postpone its transmission to avoid a collision. Secondly, FD technology can mitigate the loss of throughput caused by congestion and MAC (Media Access 1 Introduction 6

Control) scheduling, since congested nodes will be able to forward packets and receive packets simultaneously. Thirdly, it can theoretically decrease the end-to-end delay within a multihop network. The idea is that full-duplex node enables simultaneous reception and forwarding of packet. Thus, instead of the default store-and-forward architecture,FD nodes could forward a packet immediately when receiving it.

1.3 Thesis Contributions and Organization

The main objective of this thesis is to characterize 2×2 MIMO self-interference (SI) channels, to develop RF/Analog self-interference canceller (SIC) for 2×2 MIMOFD transceiver. The main contributions of this thesis are highlighted along with the thesis organization in the following. In Chapter 2, we start with a brief survey of the most relevant state-of-the-art researches re- gardingSI channel characterizations, as well as cancellation techniques, particularly RF/Analog self-interference cancellation. Also, we review the shortcomings of existing work, which gives motivation of this research work. All the self-interference cancellation techniques are based on accurately reconstructing the SI channel from the transmitter to the receiver of the same transceiver. Accurate SI-channel estimation obviously requires a clear understanding of SI-channel propagation characteristics and modelling. In Chapter 3, we present an investigation of the wideband SI channel characteristics of a 2×2 MIMO FD transceiver using dual-polarized antennas. The measured SI-channel power delay profiles at 2.45GHz with 500MHz span in various environments: anechoic chamber, laboratory room, and corridor, reveal that the SI-channel can be represented by a multipath model consisting of two components: a quasi-static internal SI-sub-channel due to the specific Tx/Rx antenna structure and a time-varying external SI-sub-channel due to possible reflections from the surrounding environment. The quasi-static internal SI-sub-channel parameters can be derived from the Tx/Rx antenna structure specifications. The time-varying external SI-channel exhibits cluster arrival features and can be represented by a modified Saleh-Valenzuela (S-V) model with lognormal-distributed taps, and the cluster power exponentially decays with cluster arrival delay. However, the path power-versus-arrival-delay decay is exponential in a laboratory-room envi- 1 Introduction 7 ronment while it follows the power law in a corridor environment. The SI-channel coherence bandwidth and RMS delay spread in all three measurement environments follow normal and lognormal distributions, respectively. Based on the characteristics of SI-channel, we propose SI cancellation (SIC) at 3 stages: (i) the RF/Analog SIC stage at the receiver input to suppress the strong but quasi-static SI component from the internal SI-sub-channel, (ii) the RF/digital SIC stage also at the receiver input to adaptively suppress the time-varying SI component from the external SI-sub-channel, and (iii) the baseband (BB) digital adaptive SIC stage at ADC output to further suppress the residual SI. This thesis solely focuses on RF/Analog self-interference cancellation, i.e., stage1. In Chapter 4, we discuss and analyze RF/Analog SIC design in system level. Specifically, we firstly discuss coupler consideration to minimize the noise figure increment and transmitted power reduction due to RF/Analog SIC. Moreover, we derive the linearity requirements of RF/Analog SIC, including the sub-components linearity requirements, so that the nonlinear distortion introduced by RF/Analog SIC will not significantly degrade the performance. Also, we study the effects of quantization error of components in RF/Analog SIC on the cancellation performance. And then, two prototypes are built. Prototype1 is for proof of concept with off-the-shelf components. For the prototype2, we present a new solution to the nonlinear distortion problems by using custom- made, highly-linear components and integrated all the components on a compact PCB board. To evaluate the performance of the implemented prototype, it is measured in an anechoic chamber and a realistic indoor environment in terms of cancellation and nonlinear characteristics. The simulation with followed digital cancellation stages reveals negligible SNR degradation due to the nonlinear distortion introduced by RF/Analog SIC. As stated in Chapter 4, at least 57dBm IIP 3 is needed for delay/phase shift module so that the nonlinear distortion introduced by RF/Analog SIC will not result in greater than 0.4dB SNR degradation. But most of widely used off-the-shelf delay lines or phase shifters do not meet this requirement. In Chapter 5, we present design of highly-linear delay/phase shift module. The delay/phase shift module is composed of a RF switched true time delay line with a nominal 30ps step size, followed by an analog variable reflective type phase shifter with 120◦ range. Finally, the last chapter concludes this thesis. 8

Chapter 2

SI Channel Characteristics andSI Cancellation Techniques: A Review

This chapter gives a brief overview on state-of-the-art researches on SI channel characterization, as well as self-interference cancellation techniques, especially RF/Analog domain cancellation. The existing studies on self-interference channel characterization and self-interference cancellation techniques are surveyed in Sections 2.1 and 2.2, respectively. More speciﬁcally, Section 2.1 focuses on self-interference (SI) channel measurements. Section 2.2 focuses on the RF/Analog self-interference cancellation, while brieﬂy introducing antenna domain, RF/digtial, and baseband digital domain cancellation techniques.

2.1 Self-Interference Channel Characteristics and Modeling

An unavoidable question for self-interference cancellation techniques in FD is what is the propagation characteristics of SI-channel. As mentioned previously, SIC schemes can be applied at RF prior to the LNA/ADC using analog and/or digital techniques, and/or at the baseband (in demod- ulator) using digital techniques by accurately reconstructing the SI based on the known transmitted signal, and an accurate estimation of the SI channel from the transmitter to the receiver of the same transceiver. Accurate SI-channel estimation obviously requires a clear understanding of SI-channel propagation characteristics and modelling. The SI-channel has many different

2017/04/07 2SI Channel Characteristics andSI Cancellation Techniques: A Review 9 characteristics of propagation of forward channel (intended signal channel). A few preliminary studies regarding propagation characterization of SI-channel have been reported. In [12], outdoor-to-indoorFD radio relay SI-channels are measured at 2.6GHz for both of compact relay and separate relay scenarios. Particularly, for a separate relay scenario, relation of antenna suppression and separation distance is investigated. Dual dipole antenna SI propagation for indoor environment is characterized at 2.6GHz with 200MHz bandwidth in [13]. In [14], indoor mobile SISO SI-channel propagation characteristics of a shared single omni-dipole antenna with circulator are studied, indicating that the corresponding SI-channel power delay profile (PDP) has three components: leakage path and reflection due to antenna port mismatch, space multipath due to surrounding environment. In [15], coherence bandwidth of SISO SI channel and antenna suppression in various scenarios are analyzed for ultra-wideband (3-10GHz). In [16], wideband SI channel for outdoor-to-indoor relay is characterized and modeled as a single decaying exponential function with specular components and small-scale fading of each tap is modeled by Rician distribution. Authors of [17] study the performance of self-interference cancellation, in which some parts are relevant to the characteristics of SI-channel. They find that environmental reflections limit cancellation performance that passiveSI suppression can achieve. In addition, higher passiveSI suppression generally results in serious frequency selectivity of the residualSI channel. In [18], the authors assume that theSI channel is Ricean distributed and characterize K-factor for theSI channel prior to RF cancellation, after RF cancellation, and after digital baseband cancellation. However, little attention has been paid to MIMOFD SI-channel. Furthermore, dual-polarized antenna for FD operation has recently attracted more attentions for its compact size and high isolation [19], while most of existing SI-channel studies have focused on single-polarized antenna.

2.2 Self-Interference Cancellation Techniques

As mentioned previously, the self-interference cancellation techniques can be applied in three domains: antenna domain, RF domain, baseband domain, as shown in Fig. 2.1. 2SI Channel Characteristics andSI Cancellation Techniques: A Review 10

Fig. 2.1 Illustration of SISO self-interference cancellation applied in 3 domains. (1) Antenna domain cancellation. (2) RF domain cancellation: RF/Analog, RF/Digital. (3) Bseband digital cancellation. 2SI Channel Characteristics andSI Cancellation Techniques: A Review 11

(a) (b)

Fig. 2.2 Antenna domain suppression configurations: (a) Dual-antenna configuration (b) Shared single antenna configuration via a circulator

2.2.1 Antenna or Propagation Domain Suppression

The antenna or propagation domain suppression is applied prior to RF self-interference cancellation to reduce the SI. Antenna or propagation domain suppression can be implemented by several configurations. One of the simplest methods is dual-antenna system in which one antenna is for transmission and another one is for reception, and two antennas are separated phys- ically [13, 15, 17, 18, 20–22], as indicated in Fig. 2.2a. This approach can provide 30-40dB suppression, depending on the separation distance. The suppression can be improved 10-25dB by placing a slab of RF absorber material between the two antennas or by using directional antenna with beam separation [17]. Another approach of implementing antenna domain suppression is dual-polarization antenna with 2 ports. One port excites a horizontal polarization mode, and the other excites a vertical polarization mode, providing approximately 30-50dB suppression [16,19,23–25]. In [19], the dual-polarization is combined with planar wavetraps, improving isolation by roughly 15dB. It is worth noting that dual-polarization can be applied to separate- antenna systems [26, 27]. Some antenna domain suppressions are based on mutiple Tx antennas with special placement to create null space to increase suppression. For instance, two Tx anten- 2SI Channel Characteristics andSI Cancellation Techniques: A Review 12 nas are fed by signals with 180◦ phase difference and Rx antenna is placed to have equal distance ◦ ◦ λ to the Tx antennas. The 180 phase difference can be achieved by 180 phase shifter [28], 2 antenna distance difference [11], and broadband rat race coupler [29, 30]. In [31], ring array λ λ antenna is proposed. The ring array elements are spaced 2 apart and roughly 4 to the central conducting cylinder. All the aforementioned configurations can be represented by Fig. 2.2a as well. In addition, another method of interfacing with antenna is that one antenna (or antenna port) is used to simultaneously transmit and receive in which the transmission and reception paths are isolated through a circulator, as illustrated in Fig. 2.2b. One of the biggest advantages of this configuration is saving the number of antennas. While due to the mismatch of antenna port, part of SI signal gets reflected from antenna back to receiver chain (depending on the return loss of antenna port, usually 10-15dB), contributing the most to the overall SI. So the suppression of this configuration is merely 15-20dB [4, 14, 25, 32, 33].

2.2.2 RF Domain Self-Interference Cancellation

RF/Digital Self-Interference Cancellation

RF SIC can be implemented with digital approach. We tap the transmit signal in digital baseband and properly reconstruct SI by adjusting the attenuation and phase accordingly. The reconstructed SI signal is converted/up-converted to RF analog domain, and combined with SI signal prior to LNA via a coupler [34–41], as indicated Fig. 2.1 RF/Digital SIC. In this way, we can take advantage of digital signal processing techniques to accurately reconstruct the linear channel response since it uses a digital FIR ﬁlter with many taps.

RF/Analog Self-Interference Cancellation

The RF SIC can be done via pure analog approach. The transmitted signal is directly coupled right after PA to the canceller and combined with SI signal prior to LNA via a coupler, as indicated Fig. 2.1 RF/Analog SIC. The design of the RF/Analog cancelling circuit is highly related to the characteristics of the SI channel. As discussed in Section 2.1, the SI channel can be divided into internal reﬂections with a small number of paths, shorter delays and stronger amplitudes 2SI Channel Characteristics andSI Cancellation Techniques: A Review 13

(a) (b)

(e) (f)

Fig. 2.3 Various typical structures of RF/Analog self-interference cancellation techniques. (a) RF/Analog SIC based on QHx220 noise canceller chip [42]. (b) RF/Analog SIC based on multi-tap with evenly power distributed [33] (c)RF/Analog SIC based on multi-tap with non-evenly power distributed [43]. (d) RF/Analog SIC based on clustered tap structure [44]. (e) RF/Analog SIC based on vector modulator structure [45]. (f) RF/Analog SIC based on BPFs [46]. 2SI Channel Characteristics andSI Cancellation Techniques: A Review 14 compared to the external (far-field) reflections. The internal reflections are static since they depend on the internal structure of antenna configurations, while the external reflections vary with surrounding objects. Since it is difficult to adapt the analog circuits with variations of the external reflections, the RF/Analog cancellation stage reduces the static internal reflections. Recently, a variety of RF/Analog structures have been proposed. As studied in [42], an off-the-shelf noise canceller chip (QHx220) with balun is used for the RF/Analog SIC circuit, as indicated in Fig. 2.3a. It takes the input signal and separates it into an in-phase and quadrature component. The quadrature component has a fixed delay with respect to the in-phase component. It emulates a variable delay by controlling the attenuation of the in-phase and quadrature signals, adding them to create the output to remove a known analog SI signal from the received signal. One of the most widely used approaches is multi-tap structure, which is similar to analog FIR filter. The transmitted signal is tapped right after PA and evenly distributed into multiple taps, consisting of tunable attenuator and/or phase shifter and/or fixed delay line. And then, all the taps are combined by a power combiner, subtracting from SI signal at receiver port prior to LNA, as shown in Fig. 2.3b. In [32, 33], authors propose a 12-tap RF/Analog SIC with variable attenuator and fixed delay line for shared single antenna circulator configuration, working with the wide bandwith, 80MHz, and data rates used by the latest 802.11ac PHY in the 2.4GHz spectrum. In [47], a 2×2 MIMO FD LTE system is built with 4 separated omni-directional dipole antennas, in which 4-tap RF/Analog SIC is with variable attenuator, variable phase shifter, and fixed delay line, for each SI channel. A non-uniform tap weighting structure is proposed in [43, 48, 49]. The concept of this structure is similar to the aforementioned multi-tap structure with evenly distributed power. But the transmitted signal is split or combined into multi-tap via coupler instead of power divider/combiner, as illustrated in Fig. 2.3c, resulting in an extension of its attenuation dynamic range. Each tap consists of a variable attenuator (Avago Technologies’s ALM-38140) and a phase shifter (Hittite Microwave’s HMC928LP5E), as well as a fixed delay line. Researchers in [37,44] have proposed a clustered tap structure for RF/Analog SIC, eliminat- ing the requirement of accurate delays or phase shifts, in which each clustered tap is composed of 4 individual taps and 4 variable attenuators and 3 power divider. Each power divider divides the transmitted signal into two different copies from each other with phase difference of 90◦. There- 2SI Channel Characteristics andSI Cancellation Techniques: A Review 15 fore, 4 copies of the tapped transmitted signal are fed into variable attenuators with a continuous phase shift of 90◦, thus covering the entire 360◦ complex attenuation plane and are later combined with the use of a power combiner. Fig. 2.3d displays the block diagram for this structure. Besides, some researchers have proposed vector modulator structure (Fig. 2.3e) with a RF variable-gain-amplifier (VGA), in which a vector modulator is used as the programmable phase shifter and attenuator to obtain the inverted of SI signal and RF variable gain amplifier helps extend the cancellation dynamic range [21, 45]. RF/Analog domain cancellation also can be implemented on monolithic microwave integrated circuit (MMIC) to reduce the size of circuits significantly. Generation of significant (in the order of nano second) true time delay on silicon or other substrates is fundamentally challenging due to the length of the transmission lines required and the lossy nature of the substrate. Thus, the authors of [46, 50, 51] propose wideband SIC in the RF domain based on frequency-domain equalization of the wireless SI channel, implemented with tunable, reconfigurable, second-order, high-Q RF band-pass filter (BPFs) which are realized as N-path Gm-C filters with embedded variable attenuation and phase shifting, as shown in Fig. 2.3f. Nevertheless, most of the previous RF/Analog SIC designs are for low or medium power scenarios. More power, such as +30dBm or +38dBm, needs to be transmitted for serving as medium range BS for micro cell [52], which brings in more challenges on the SIC design. To start with, more suppression performance is needed to suppress the SI down to the receiver noise floor. For instance, for +30dBm LTE 20MHz radio, roughly 120dB cancellation is required in order to mitigate SI down to receiver noise floor of -90dBm [47]. This cancellation requirement is almost 10-20dB higher than the performance reported in [34, 47, 53]. In addition, RF/Analog SIC will introduce nonlinear distortion due to higher transmitted power, which effectively increases the receiver noise floor. Researchers in [54, 55] try to solve this problem by proposing RF/Analog SIC nonlinear suppression technology, in which the nonlinear distortion is modeled by memory polynomial. In the subsequent cancellation stages, the model estimations are subtracted instan- taneously from the received signal containing nonlinear distortions. However, more extra hard- ware resource will be used, e.g., down-converter and ADC. Thus, in order to support high power full-duplex application without increasing implementation complexity, the RF/Analog SIC needs 2SI Channel Characteristics andSI Cancellation Techniques: A Review 16 to be highly-linear. But little attention has been attracted to nonlinear distortion introduced by RF/Analog SIC. The linearity requirements for RF/Analog SIC, as well as components of it, i.e., variable attenuator and/or delay/phase module, are not well investigated and analyzed. Another thing is that none of these works explicitly analyze the effects of quantization error of components, i.e., variable attenuator and delay/phase shift module in RF/Analog SIC on the cancellation performance. And also, few these publications discuss noise figure increment and transmitted power degradation due to coupler in RF/Analog SIC.

2.2.3 Baseband Domain Self-interference Cancellation

Processing the SI in the digital domain facilitates the use of adaptive digital filtering for a large number of reflected paths due to the external environment. The digital SI-cancellation is based on the general transversal symbol-synchronous finite impulse response (FIR) structure, where the constant tap-delay is equal to the signal sampling period and implemented as a D-flipflop clocked by the sampling clock. Here, only the tap-coefficients need to be specified from an estimate of the SI channel and thus we avoid the interaction between the delays and the attenuations as it is the case for the analog TDL. As a result, the digital processing can deal with a larger number of taps than the analog TDL to adapt to a varying external environment. Digital SI-cancellation is particularly suitable for MIMO systems as the cross interference between antennas increases considerably the number of taps needed to reduce the SI.

2.3 Chapter Summary

In this chapter, we provide an overview of the existing works on SI channel characterizations and modeling, as well as the self-interference cancellation techniques. In particular, we focus on design of the RF/Analog cancellation while digital SI-cancellation technique is beyond the scope of the thesis. This survey provides motivations for the research proposed in this thesis. For SI-channel characterization, first of all, little attention has been paid to MIMO FD SI- channel. Furthermore, most of existing SI-channel studies have focused on single-polarized antenna. Dual-polarized antenna has recently attracted more attention for its compact size and high 2SI Channel Characteristics andSI Cancellation Techniques: A Review 17 isolation. In Chapter 3, we present an investigation of the wideband SI-channel characteristics of a 2x2 MIMO FD system using dual-polarized antennas at center frequency of 2.45GHz with 500MHz bandwidth in various environments: anechoic chamber, laboratory room, and corridor. For RF/Analog SIC, firstly, most of the aforementioned RF/Analog SIC designs are for low or medium power scenarios. RF/Analog SIC will introduce nonlinear distortion when transmitted power is increased, causing SNR degradation. In order to support high power FD applications, the RF/Analog SIC needs to be highly-linear. But little attention has been paid to nonlinear distortion introduced by RF/Analog SIC. The linearity requirements for RF/Analog SIC and its components, i.e., variable attenuator and/or delay/phase module, are not well investigated and analyzed. Secondly, none of this work explicitly analyzes the effect of quantization error of components, i.e., variable attenuator and delay/phase shift module in RF/Analog SIC on the cancellation performance. And also, a few publications discuss noise figure increment and transmitted power degradation due to coupler in RF/Analog SIC. In Chapter 4, we analyzed all the design considerations,i.e., the effects of coupler loss on the noise figure degradation, system and sub-components linearity requirements, the effect of quantization error of components, and tunning algorithm. And then, we propose a solution to the nonlinear distortion problems by using a custom-made highly-linear variable attenuator and delay/phase shift module. Regarding the delay/phase shift module, commercial products and existing prototypes do not meet the linearity requirements analyzed in Chapter 4. So in Chapter 5, we propose a custom- made highly-linear delay/phase shift module. 18

Chapter 3

SI Channel Characterization and Modeling.

3.1 Introduction

Accurate SI-channel estimation obviously requires clear understanding of SI-channel propagation characteristics and modeling. Dual-polarized antenna for full-duplex operation has recently attracted more attention for its compact size and high isolation [19], while most of existing SI-channel studies have focused on single-polarized antenna. To fill in this gap, this chapter presents an investigation of the wideband SI-channel characteristics of a 2x2 MIMO FD system using dual-polarized antennas at center frequency of 2.45GHz with 500MHz bandwidth in various environments: (i) anechoic chamber, (ii) laboratory room, and (iii) corridor. The measured SI-channel power delay profiles suggest that the SI-channel can be represented by a multipath model consisting of two components: a quasi-static internal SI-sub-channel due to the specific Tx/Rx antenna structure and a time-varying external SI-sub-channel due to possible reflections from the surrounding environment. Measurements in anechoic chamber show only the quasi-static internal SI-sub-channel due to the absence of external reflections. In other words, the quasi-static internal SI-sub-channel can be clearly identified by measurements in anechoic chamber, and its parameters can be derived from the Tx/Rx antenna structure specifications. The

2017/04/07 3 SI Channel Characterization and Modeling 19 time-varying external SI-channel exhibits cluster arrival features and can be represented by a modiﬁed Saleh-Valenzuela (S-V) model, and the cluster power exponentially decays with the cluster arrival delay. However, the path power-versus-arrival-delay decay is exponential in a laboratory-room environment while it follows the power law in a corridor environment. Section 3.2 gives a brief overview of wideband channel sounding system, measurement environment, and measurement procedure. In Section 3.3, we present the measurement result and SI-channel from corresponding PDP, to small-scale fading characteristics. Section 3.4 provides concluding remarks.

3.2 Measurement Setup

We consider the SI-channel from the Tx-antenna inputs (i.e., after Tx power amplifiers (PA)) to the Rx-antenna outputs (i.e., to the Rx low-noise amplifiers (LNA)) of a 2x2 MIMO system. SI existing at the Rx LNA input comes from the high-power Tx signal via various paths, which can be classified into two main sub-channels. The first sub-channel includes the direct coupling paths inside the Tx/Rx antenna structure, and hence can be called the internal SI-sub-channel. The second sub-channel includes the reflection paths due to possible reflectors in the environment surrounding the transceiver, and hence can be called the external SI-sub-channel.

Table 3.1 Antenna Speciﬁcations Summary

Frequency 1.7-2.7GHz Gain >7.9dBi VSWR <1.4 Vertical and Horizontal beam width 3dB:75◦, 10dB:160◦ Port isolation >45dB

3.2.1 Antenna

Since possible reﬂectors in the surrounding environment are usually in a much longer distance from the Rx input than the Tx output, the internal SI-sub-channel is expected to be dominant, 3 SI Channel Characterization and Modeling 20

(a)

(b)

Fig. 3.1 A dual-polarized antenna: (a) prototype, (b) simulation model cut view with dimensions (in mm). and large Tx/Rx isolation is a very important feature in Tx/Rx antenna structure design for FD 3 SI Channel Characterization and Modeling 21

Fig. 3.2 Typical antenna far-field Co-and Cross polarization power ratio measurement at 2.5GHz systems. For this, we consider a dual-polarized antenna for compact size and high isolation [19]. In particular, we designed and implemented a new dual-polarized antenna structure using comb- corrugated Vivaldi ridges integrated in a circular horn to achieve broadband characteristics and directivity, as indicated in Fig. 3.1. This dual-pol antenna operates over the broadband 1.7- 2.7GHz with low-variation beam-patterns, covering most of the LTE spectrum. Typical performance specifications listed in Table 3.1. Fig. 3.2 indicates the far-field cross polarization power ratio, normalized to 8dBi antenna gain. 3 SI Channel Characterization and Modeling 22

Fig. 3.3 Wideband 2×2 MIMO SI channel sounding system.

3.2.2 Wideband Channel Sounding System and Data Acquisition

The two antennas are mounted on a wood-frame with 50cm-separation (for a 2x2 MIMO FD transceiver) in the SI-channel measurement system shown in Fig. 3.3. The VNA 8722ES is used in the 4-port measurement modes under the control of two switches to enable the 2x2 MIMO SI- channel measurement. PA and LNA are used to increase the dynamic range of sounding system for better accuracy. The measurements are carried out at center frequency of 2.45GHz with 500MHz bandwidth with VNA 8722ES setting, as listed in Table 3.2. As mentioned above, RF switches, PA and LNA are used to enable MIMO measurement and improve accuracy. However, they are not considered as a part of SI channel. Therefore, the 3 SI Channel Characterization and Modeling 23 effects of switches, PA and LNA should be removed in order to obtain real SI channel, which can be given by dividing the combined responses of switches, PA and LNA, as follows:

H (f) H(f) = total (3.1) Hextra(f) where H(f) is the real SI channel frequency response, Htotal(f) is the frequency response including switches, PA and LNA measured by VNA, Hextra(f) is the combined frequency response of switches, PA and LNA.

3.2.3 Measurement Environments

The measurements were carried out in 3 environments, (i) anechoic chamber: 7m(L)×3.5m(W)×3.5m(H), (ii) laboratory room (MC838): 14m(L)×10m(W)×6(H), (iii) corridor: 60m(L)×8m(W)×3.5m(H). In environment (i), the 2x2 MIMO antenna subsystem (Fig. 3.4a 3.4b) are mounted on a tripod at 1.9m above the chamber floor. The anechoic chamber represents an ideal environment without external reflection as radiated incident signals are heavily attenuated by its absorbing walls. Therefore, we can identify the internal SI-sub-channel and investigate its characteristics. In environment (ii), the 2x2 MIMO antenna subsystem are mounted on a tripod (located on the mezzanine, as shown in Fig. 3.4d) at 4.5m above the room floor. The test location is 10m, 12m away from wall 1 and wall 2 respectively. Around 3.3-3.6m, there are several white boards and load-bearing columns, as illustrated in Fig. 3.4c. Distance between antenna and floor objects is approximately 5-7m. This 14m(L)×10m(W) laboratory room is almost square with a lot of possible surrounding reflectors, which allows us to observe both the internal and external SI-sub- channels and their characteristics. In environment (iii), the 2x2 MIMO antenna subsystem are mounted on a measurement equip- ment rack 2m above the corridor floor, located at one side of corridor, as shown in Fig. 3.4f 3.4e. The test location is 29m away to wall 1, 59m to wall 2, 3.5-4m to load-bearing column. The length of the corridor (60m) is almost 17 times its width (3.5m). Hence, possible reflectors are likely along the length of the corridor, which allows us to see both the internal and external SI-sub-channels with characteristics different from those in environment (ii). 3 SI Channel Characterization and Modeling 24

(a) Anechoic chamber measurement set-up (b) Anechoic chamber layout

(e) Corridor measurement set-up (f) Corridor layout

Fig. 3.4 Measurement setup and layout in various environments 3 SI Channel Characterization and Modeling 25

Table 3.2 VNA Setting Parameters

Sweep frequency 2.2-2.7 GHz Number of Sweep Point 1601 output power 5dBm IF bandwidth 100Hz Average factor 10 Sweep time 800ms

3.2.4 Measurement Procedure

We focus on the small-scale fading characterization. For each environment, we perform 30 measurements, each at one of 30 locations in a small 6×5 grid with 7cm-distance, which corresponds to half of wavelength of 2.2GHz. Assuming the SI-channel is approximately unchanged during the measurement time ∆t = 800ms, for the previously discussed VNA setting, each measurement (excluding effects of switches, PA and LNA in the channel sounding system) represents the time-varying SI-channel frequency response sample HTR(f; ti) at the measurement time ti, i= 1,2, . . . ,30, where f=2.2GHz+k∆f with k=0,1,2,. . . ,1600 and ∆f=5/16MHz. T=1,2 and R=1,2 designate the Tx and Rx ports, respectively, of the 2×2 MIMO SI-channel. The time-varying SI- channel impulse response sample hTR(f; ti) is computed by performing Inverse Discrete Fourier

Transform (IDFT) of the measured HTR(f; ti) with Kaiser-Bessel window, β=8, resulting in a 1.95 1 time domain resolution 500MHz =3.9ns [57] . The time domain SI-channel response in linear scale is calculated as

30 2 1 X 2 S (τ) = E |h(τ, t )| = |h(τ, t )| (3.2) TR ti i 30 i i=1

th where ti is the i measurement in 6x5 grid. Eti is the expectation operator.

1The time domain resolution is increased by window compensation. Usually, without window compensation, the 1 time domain resolution is given by 500MHz . 3 SI Channel Characterization and Modeling 26

3.3 Measurement Results and SI-channel Modeling

3.3.1 SI-channel PDPTR Trends

The SI-channel PDPTR in dB, i.e., 10log10[STR(τ)], T=1,2 and R=1,2, for the three environments under consideration are plotted in Fig. 3.5. The SI-channel PDPTR clearly indicates almost only the internal SI-sub-channel in environment (i): anechoic chamber. Note that for each dual-polarized antenna we use one polarization (e.g., Vertical) for Tx port and the other polarization (e.g., Horizontal) for Rx port. Correspondingly, PDP11 and PDP22 in the anechoic chamber exhibits a dominant peak of about -45dB at a very short delay τ = 4.7ns, which is the V-H isolation of the same antenna. Similarly, PDP12 and PDP21 in the anechoic chamber exhibits a lower peak of -70dB at short delay, representing the cross-polarization coupling from the V (or H)-port of one antenna to the H (or V)-port of the other antenna. For larger delay

(>45ns), the four PDPTR curves quickly drop to negligibly low levels, suggesting the absence of the external SI-sub-channel in the anechoic chamber. This can be explained by the dimension of anechoic chamber (7.3m×3.7m). 7.3m distance corresponds to approximately 48ns two way electromagnetic wave prorogation time. Reﬂections after 48ns is at extreme low level, which matches PDP shown in Fig. 3.5. For measurements in an outdoor environment with the 2×2 MIMO antenna subsystem mounted on a sufﬁciently high location in open space (as in the case of micro/macro-cell base stations), we also obtain the same measurement results as in the anechoic chamber.

In both environments (ii) and (iii), the SI-channel PDPTR indicate the presence of both the internal and external SI-sub-channels. However, while the segment corresponding to the internal SI-sub-channel (i.e., short delay) is the same, the segment corresponding to the external SI-sub- channel (i.e., long delay) has a noticeably different decaying behavior in two environments (ii) and (iii). The external SI-sub-channel PDPTR in dB versus delay in environment (ii), laboratory room, looks like a straight line, indicating an exponential decay. On the other hand, in environment (iii): corridor, the external SI-sub-channel PDPTR curves exhibits noticeable clusters and while the cluster power decays exponentially with delay, the path power-versus-delay in each cluster does not follow the exponential decay. Further investigations of the SI-channel PDPTR 3 SI Channel Characterization and Modeling 27 in detail, to reveal their characteristics, will be presented.

Fig. 3.5 Measured PDP comparisons for three scenarios: anechoic chamber, lab, and corridor.

3.3.2 SI-Channel Impulse Response Models and Parameters

This phenomenon of clusters arrival has been observed in other measurement campaigns of indoor environment and can be modeled by the Saleh-Valenzuela (S-V) model [58–60]. To identify different clusters, visual inspection is used to distinguish clusters, since in our measurement, clusters are well-separated in the PDP. Actually, this method is widely used in other measurement campaigns [58–61]. The laboratory-room environment (ii) has more clusters than the corridor environment (iii). The measured results suggest that the SI-channel impulse response can be appropriately modeled as

M L K X X Xl hTR(τ) = g0mδ(τ − τ0m) + glkδ(τ − Tl − τkl) (3.3) m=1 l=1 k=1 3 SI Channel Characterization and Modeling 28

PM where the 1st summation m=1 g0mδ(τ − τ0m) represents the internal SI-sub-channel, while the 2nd summation represents the external SI-sub-channel as a modiﬁed version of the Saleh-

Valenzuela (S-V) model. The coefﬁcients g0m is gain of internal reﬂection. M is the possible th number of internal paths, τ0m is the arrival time of the m internal path. L is the number of th clusters in the external SI-sub-channel, Kl is the number of MPCs in l cluster, glk are the th th th complex gain of the k path of the l cluster. Tl and τkl represent arrive time of l cluster and th arrival time of k MPC relative to Tl, respectively.

However, M, g0m, and τ0m depend on the internal antenna structure: they are quasi-static, and can be calculated/estimated based on the antenna structure speciﬁcations. On the other hand,

L, K, glk, Tl, τlk depend on the external possible reﬂectors in the surrounding environment, and are time-varying. In a single shared antenna with circulator, M is equal to 2 [14]. For our 2×2 MIMO FD transceiver using the dual-polarized antennas, M = 1. Direct internal SI-sub-channel, (i.e., TR=11,22), is caused by the direct coupling between V-H polarization of the same antenna. direct So g01 [dB] could be estimated by antenna V-H isolation in frequency domain measured in anechoic chamber (represented by ISOV −H ) and cable loss (represented by ILcable).

direct g01 [dB] = ISOV −H − 2ILcable. (3.4)

direct direct τ01 can be approximated by feed cable propagation time (τcable) as τ01 ≈ 2τcable. In our 2 case, 0.5m feeding cable was used for each antenna port. Estimated τ01 is approximately 4.6ns for both of TR=11 and TR=22, compared with measurement of 4.7ns and 4.8ns. ISO1−1 and direct ISO2−2 are -47.4dB and -50dB, respectively over 500MHz. g01 is estimated using (3.4), approximately -48.2dB and -50.8dB respectively, which matched with measured -48.5dB and -50.9dB, respectively as indicated in Fig. 3.5. cross cross g01 and τ01 of cross internal SI-sub-channel, (i.e., TR=11,22), can be estimated by the free space path loss (FSPL) between two antennas and far-ﬁeld cross polarization ratio (CPR)

2For CCSMA18-MM series with 70% velocity of propagation, 0.5m corresponds to 2.3ns propagation time and roughly 0.4dB insertion loss 3 SI Channel Characterization and Modeling 29 of the cross antenna, which is given by

cross g01 [dB] = CPR − 2ILcable − F SP L. (3.5)

cross d τ01 ≈ 2τcable + υ , d is the distance between two antennas, υ is the velocity of electromagnetic cross 0.5 waves in free space. τ01 is calcuated 2 × 2.3ns+ 3×108 =6.2ns, while approximately 7.2ns was measured. CPR is approximately -35dB at 90◦ and -90◦, as indicated in Fig. 3.2. FSPL is cross roughly -33dB. Thus, we could estimate g01 = -68.8dB, which is close to the measured result of -70 to -65dB. The aforementioned comparisons between measurement and estimation conﬁrm idea that the internal SI-sub-channels are quasi-static, and dependent on the antenna structure speciﬁcations.

Cluster Arrival Rate

The inter-cluster interval, ∆T = ∆Tl − ∆Tl−1 > 0, of the external SI-sub-channel can be assumed to follow an exponential distribution with an arrival rate Λ, which could be estimated by 1 E{∆T } , where E{∆T } is the average inter-cluster interval.

Path Arrival Rate

Similar to cluster arrival with exponential distribution, the path arrival interval follows exponential distribution as well. But due to the limited time domain resolution of inverse DFT, we can not resolve path within 3.9ns. Each resolvable delay bin have signiﬁcant energy. Subsequently, paths are assumed to arrive every 3.9ns in the classical tapped delay line model [62].

Power of Cluster and Path Decay Model

In the original SV model, cluster power is assumed to exponentially decay with the cluster arrival delay. Thus, the power of kth path in lth cluster is given by

T 2 2 − l |glk| = |g11| e Γ P (τlk) (3.6) 3 SI Channel Characterization and Modeling 30

th where P (τlk) is the path decay function, Tl is the arrival time of l cluster. The cluster power decay constant Γ is determined as the exponential decay of the peak power of the received clusters. In the standard SV model, path power decays exponentially with path arrival delay in a cluster, as follows: τ − lk P (τlk) = P (τl0)e γ (3.7)

th where P (τl0) is the power of ﬁrst path in l cluster. And the exponential decay rate γ is proportional to the arrival time of clusters [58], i.e., γ = aγTl + γ0. Further investigations indicate that the external SI-sub-channel PDPTR curves in the laboratory-room environment (ii) closely follow the ﬁtting exponential-decay S-V model as shown in Fig. 3.6. So the proposed PDP model for indoor laboratory-room environment can be expressed as follows:

2 PDPTR(τ) = 10log10 |g0m| δ(τ − τ0m)

L Kl (3.8) X X 2 10 TL 10 τlk + {10log |g | − + 10log P (τ ) − }δ(τ − T − τ ) 10 11 ln(10) Γ 10 l0 ln(10) γ l kl l=1 k=1

On the other hand, the external SI-sub-channel PDPTR curves in the corridor environment (iii) do not ﬁt the exponential-decay S-V model. Instead, similar to results reported in [58, 59], our further studies reveal that its power-versus-delay decay follows well the power law as shown in Fig. 3.7. Thus, the path decay function is given by

−nl P (τlk) = P (τl0)τlk (3.9)

th where P (τl0) is the power of ﬁrst path in l cluster. We found that the power-law decay rate nl is proportional to the arrival time of clusters, i.e., nl = bnl Tl + nl0. The plots of nl versus cluster arrival delay Tl and their linear models show a good agreement in Fig. 3.8. Therefore, the proposed PDP model for corridor environment can be given by the equation as follows: 3 SI Channel Characterization and Modeling 31

Fig. 3.6 Measured Lab PDP and S-V model ﬁtting with exponential MPCs decay

2 PDPTR(τ) = 10log10 |g0m| δ(τ − τ0m)

L Kl X X 2 10 TL + {10log |g | − + 10log P (τ ) − 10log (τ −nl )δ(τ − T − τ )} 10 11 ln(10) Γ 10 l0 10 lk l kl l=1 k=1 (3.10)

All parameters in S-V model for laboratory-room and corridor are listed in Table 3.3. We could associate certain clusters with the antenna surroundings. In environment (ii), it can be seen from Fig. 3.6 that there always are 1-2 clusters at around 20ns, corresponding to 3m, which is the distance to the wall and to the chamber metal cover. The distance to the floor reflector is around 5-7m, corresponding to clusters around 40ns-50ns. Around 70ns, there are clusters, which are caused by the reflections from the wall 1 and/or wall 2 of 10-12m in front of antenna, as indicated in Fig. 3.4d. In environment (iii), there are 3 clusters for the all SI-sub- channels. The first cluster is caused by the load-bearing columns 3.5-3.7m away from antennas, 3 SI Channel Characterization and Modeling 32

Fig. 3.7 Measured corridor PDP and S-V model ﬁtting with power law MPCs decay

Fig. 3.8 Path power decay rates: γ > 0 (exponential), nl > 0 (power-law) versus cluster arrival delay Tl 3 SI Channel Characterization and Modeling 33

corresponding to 23ns-25ns. The second cluster is located at roughly 197-200ns, which is exactly the round-way delay of 29m-30m distance, corresponding to wall 1. The third cluster around 400ns is due to reﬂections from wall 2, 59-61.5m away from antennas, as illustrated in Fig. 3.4f.

Table 3.3 The modiﬁed S-V model parameters for the SI-sub-channels in 2 environments (ii) and (iii) External Cluster power Meausrement Environment No. of clusters Λ−1ns−1 SI-sub-channels decay rate Γ TR=11 4 0.019 26.4 Environment (ii): Laboratory room TR=22 5 0.027 36.2 Exponential path power delay rate: TR=21 5 0.026 46.2 a =-0.002, γ =1.986 γ 0 TR=12 4 0.016 41.4 TR=11 3 0.0051 51.9 Environment (iii): Corridor TR=22 3 0.0051 56.6 Power-law path power delay rate: TR=21 3 0.0052 65.3 b =0.242, n =6.368 nl 0l TR=12 3 0.0051 57.7

The different external SI-sub-channel PDPTR characteristics in the laboratory-room and corridor environments can be explained by the fact that the 14m(L)×10m(W) laboratory room is almost square with a lot of possible surrounding reﬂectors, while in the corridor, possible reﬂec- tors are likely along the length of the corridor. As a result, the corridor environment (iii) has a smaller number of clusters with larger inter-cluster delay than the laboratory-room environment (ii). Furthermore, a cluster in the corridor environment (iii) likely has less number of paths than a cluster in the laboratory-room environment (ii). Accordingly, the power-versus-delay decay is exponential in the laboratory-room environment (ii) and follows the power law in the corridor environment (iii).

Small-Scale Fading Characteristics

The delay axis is divided into bins with 3.9ns bin width, which is corresponding to time domain resolution. The small-scale fading characteristic is evaluated with bins at specific delay over all 30 measurements at 3 environments. Amplitude of bin at specific delay is fitted to theoretical Rayleigh, Nakagami, Rician, and Lognormal distributions. P-value returned by Kolmogorov- Smirnov (K-S) test [63] is used to evaluate the goodness of fitting result. Fig. 3.9 displays the comparison of passing rate of different distributions at 5% significant level. 3 SI Channel Characterization and Modeling 34

It can be seen from Fig. 3.9 that Rayleigh distribution has a much low passing rate. One explanation is that the ﬁne resolution of the wideband channel would imply a too small number of paths arriving in each delay bin, consequently, the central limit theorem is no longer applicable.

Fig. 3.9 K-S test pass rate for different distributions at 5% signiﬁcant level

It turns out that lognormal distribution has the highest passing rate for all the channels, as illustrated in Fig .3.9. It has been observed and reported in [59,64–66] that lognormal distribution ﬁts the measured data very well for wideband channel or ultra-wide band channel (UWB), which is similar to our wideband measurement of 500MHz centered at 2.45GHz, Fig. 3.10 represents typical lognormal distribution ﬁtting results of path gain at delay 34ns bin. Measured data from other delay bins or other two environments show similar results. 3 SI Channel Characterization and Modeling 35

Fig. 3.10 Small-scale fading CDFs of 4 SI channels at ﬁtted with lognormal distribution at delay bin of 34ns in laboratory room.

3.3.3 Time Dispersion Characteristics

Coherence Bandwidth

Coherence bandwidth is a statistical measure of frequency selectivity of the channel. Autocorre- lation function Ac(∆f) of channel response could be obtained from STR(τ) as follows [67]:

Z +∞ −j2π∆f Ac(∆f) = STR(τ)e dτ (3.11) −∞

Coherence Bandwidth (Bc) is defined as the minimum ∆f so that |Ac(∆f)| < 0.9. Coherence bandwidth of SI channel can be modeled by a normal distribution, but with different parameter values for various scenarios. The CDFs of the coherence bandwidth of all the measurements are shown in Fig. 3.11. Coherence bandwidth of SI channel in anechoic chamber is much larger than that in environments (ii) and (iii), since the external reflections are negligibly small in anechoic chamber. As 3 SI Channel Characterization and Modeling 36 shown in Fig. 3.11, coherence bandwidth of the direct SI-channels (TR=11, 22) in the anechoic chamber are 40-55MHz wider than that of the cross SI-channels (TR=12, 21) because the direct SI-channel coupling is -50 to -45dB (V-H isolation), which is approximately 30-40dB higher than the strongest external reflection path, as illustrated in Fig. 3.5, so that the direct SI-channel PDP is dominated by the high power delta function, corresponding to a relatively flat frequency response. On the other hand, the internal path is only 5-10dB stronger than possible external reflection path in the cross SI-channels, and hence, the cross SI-channel exhibits noticeable multipath fading effects with narrower coherence bandwidth. Fig. 3.11 also indicates that the SI-channel in the corridor environment has a wider coherence bandwidth than in the laboratory-room environment by 1-2MHz, corresponding to the fact that the SI-channel PDP at the delay around 70-120ns the laboratory-room environment has roughly 10dB higher than that in the corridor environment (shown in Fig. 3.5).

Fig. 3.11 CDFs of coherence bandwidth measured in anechoic chamber, laboratory, corridor 3 SI Channel Characterization and Modeling 37

RMS Delay Spread

The RMS delay spread is the statistical parameter of the time dispersion of the channel. It can be computed as follows [67]:

s p Pk α τ 2 Pk α τ τ = τ 2 − τ 2 = k k − ( k k )2 (3.12) RMS Pk Pk αk αk

th th where τk is the excess delay of k bin, αk is the amplitude of MPCs at k bin.

Fig. 3.12 CDFs of RMS delay spread measured in anechoic chamber, laboratory, corridor

The threshold of calculating RMS delay spread is given side-lobe level (SLL) of the applied window function. In this case, SLL of the Kaiser-Bessel window with β=8 is approximately 60dB. Thus, The threshold is calculated as 60dB below the peak signal level. Fig. 3.12 represents CDFs of RMS delay spread of all measurements. RMS delay spread could be approximated by lognormal distribution. RMS delay spread measured in chamber was much smaller than that in corridor and laboratory room, especially for direct SI channel (TR=11, 3 SI Channel Characterization and Modeling 38

Fig. 3.13 Fit curves of RMS delay spread versus coherence bandwidth: Plotted in log-scale

22). SI-channel RMS delay spread in the corridor environment is less than that in the laboratory room environment.

Typically, the coherence bandwidth (B0.9) is inversely proportional to the RMS delay spread α (τRMS) of the channel, B0.9 = , where α is constant. The relation between RMS delay τRMS spread and coherence bandwidth is shown in Fig. 3.13. α is obtained by minimizing mean square error (MSE) between measured data and ﬁtted curve.

3.4 Concluding Remarks

In this chapter, the wideband 2×2 MIMO SI-channel for FD operation with dual-polarized antennas is characterized by measurements at 2.45GHz with 500MHz span in different environments: (i) anechoic chamber, (ii) laboratory room, and (iii) corridor. It is observed that the SI-channel can be represented by a multipath impulse response with two sections: a quasi-static internal SI-sub-channel due to the specific Tx/Rx antenna structure and a time-varying external SI-sub- 3 SI Channel Characterization and Modeling 39 channel due to possible reflections from the surrounding environment. Measurement in anechoic chamber shows that the quasi-static internal SI-sub-channel parameters can be derived from the Tx/Rx antenna structure specifications. The time-varying external SI-channel exhibits cluster arrival features and can be represented by a modified Saleh-Valenzuela (S-V) model, and the cluster power exponentially decays with cluster arrival delay. However, the path power-versus-arrival- delay decay is exponential in a laboratory-room environment while it follows the power law in a corridor environment. The SI-channel coherence bandwidth and RMS delay spread in all three measurement environments follow normal and lognormal distributions, respectively. 40

Chapter 4

RF/Analog Self-Interference Canceller for 2×2 MIMO Full-Duplex Transceiver1

4.1 Introduction

In Chapter 3, we investigated and measured the characteristics of SI-channels, which indicates that the SI-channel can be considered to have 2 segments: (a) the quasi-static internal SI-sub- channel due to the internal antenna structure and (b) the time-varying external SI-sub-channel due to external reﬂections from the surrounding environment. Due to this characteristic of SI- channels, SI cancellation (SIC) can be effectively done at 3 stages: (i) the RF/Analog SIC stage at the receiver input to suppress the strong but quasi-static SI component from the internal SI- sub-channel, (ii) the RF/digital SIC stage also at the receiver input to adaptively suppress the time-varying SI component from the external SI-sub-channel, and (iii) the baseband (BB) digital adaptive SIC stage at ADC output to further suppress the residual SI. The 2 RF SIC stages (i) and (ii) at the receiver input (prior to the LNA/ADC) are required to suppress the SI to a sufﬁciently low level in order to prevent LNA/ADC from being overloaded or saturated. The remaining self- interference signal from the output of RF/Analog SIC is fed to RF/Digital SIC stage, as well as BB/Digital SIC stage, for further suppression processing. This chapter focuses on RF/Analog

1Parts of this chapter will be presented at 2017 IEEE International Conference on Communications (ICC), Paris, France [68].

2017/04/07 4 RF/Analog Self-Interference Canceller for 2×2 MIMO Full-Duplex Transceiver 41 self-interference cancellation, i.e., stage 1. Discussions regarding stage 2 and 3 are beyond the scope of this thesis. As mentioned previously, most of existing works are based on low or medium power scenario. More power, such as +30dBm, needs to be transmitted for serving as medium range BS for micro cell [52], which causes more challenges on the SIC design. To start with, more suppression performance is needed to suppress the SI down to the receiver noise floor. In addition, RF/Analog SIC will introduce nonlinear distortion due to higher transmitted power, which effectively increases the receiver noise floor. But little attention has been attracted to nonlinear distortion introduced by RF/Analog SIC. The linearity requirements for RF/Analog SIC and its components of it, i.e., attenuator and delay/phase module, are not well investigated and analyzed. Besides, none of current works explicitly analyze the effect of quantization error of components, i.e., variable attenuator and delay/phase shift module in RF/Analog SIC, on the cancellation performance. To fill up these gaps, in this chapter, we first discuss coupler consideration to minimize the noise figure increment and transmitted power reduction due to RF/Analog SIC. Moreover, we derive the linearity requirements of RF/Analog SIC, including the component linearity requirements, so that the nonlinear distortion will not significantly degrade the performance. Effects of quantization error of components are also investigated. Two prototypes are built. Prototype 1 is for proof of concept with off-the-shelf components. For the prototype2, we present a new solution to the nonlinear distortion problems by using custom-made, highly-linear components and integrate all components ona compact PCB. For performance evaluation, two prototypes are measured in anechoic chamber and realistic indoor environment in terms of cancellation and nonlinear characteristics. Measured results indicate that when combined with custom dual-polarized antenna, prototype2 could provide typically 34dBm OIP 3, and a cancellation of roughly 80dB (in anechoic chamber) and 61dB (in indoor environment) for +30dBm, OFDM 20MHz signal centered at 2.27GHz. The simulation with followed digital cancellation reveals negligible SNR degradation (0.3dB) due to the nonlinear distortion of prototype2, as compared with 6.1dB of prototype1. Section 4.2 presents RF/Analog SIC structure and design considerations, including cou- 4 RF/Analog Self-Interference Canceller for 2×2 MIMO Full-Duplex Transceiver 42 pler selection, nonlinearity analysis, tunning algorithms, effects of quantization error of sub- components on cancellation performance. Two prototypes are implemented in Section 4.3. Mea- sured results are shown in Section 4.4. Section 4.5 provides some concluding remarks.

4.2 Multi-Tap Delay Line RF/Analog SIC Structure and Design Considerations

4.2.1 Structure

The RF/Analog SIC stage 1 is based on multiple tapped delay line with evenly distributed power, as indicated in Fig. 4.1. Tx signal is probed by a coupler (coupler 1) to RF/Analog SIC. All the tapped SI power is evenly divided into each tap by power divider. In each tap, there are an adjustable attenuator to tune the amplitude of copied signal, and a delay/phase shift module to adjust the phase coefﬁcients. At the output of RF/Analog SIC, all the adjusted delayed versions of SI signal are combined by a combiner, and are subtracted from SI signal at antenna receive port with another coupler (coupler 2).

4.2.2 Coupler Consideration

As illustrated in Fig .4.1, insertion loss of coupler 1 introduces the transmitted power reduction. Insertion loss of coupler 2 introduces receiver noise ﬁgure increment. Insertion loss of coupler is mainly caused by the fact that some power enter to the coupled port and is given by [69]

− C ILcoupler = −10log10(1 − 10 10 ) (4.1) where C is the coupling factor in dB. In order to minimize transmitted power degradation and receiver noise ﬁgure with RF/Analog SIC, coupler with high coupling factor should be selected. However, maximum coupling factor is also constrained by the antenna suppression (AS) since if coupling factor is too large, the minimum tap attenuation potentially can be larger than AS, which will be ineffective to cancel SI. Another consideration is that it is beneﬁcial to place a coupler with larger coupling factor 4 RF/Analog Self-Interference Canceller for 2×2 MIMO Full-Duplex Transceiver 43

Fig. 4.1 Generic tapped delay line canceller diagram. on the transmitter side (coupler 1) since it will release the linearity requirements of variable attenuator and delay/phase shift module. Considering the AS, as well as insertion loss of power divider, combiner, variable attenuator and delay/phase shift module in our system, 10dB and 6dB coupler are chosen as coupler 1 and 2, respectively, which correspond to 0.5dB and 1.3dB insertion loss, calculated by (4.1). Thus, the actual transmitted power would be reduced by 0.5dB and receiver noise figure with RF/Analog SIC would increase by 1.3dB. Actually, coupler 2 could be also replaced by a 10dB coupler to reduce noise figure degradation by 0.8dB at the cost of narrowing down attenuation dynamic range of each tap. The noise figure of receiver with RF/Analog SIC is given by:

TNF = 1.3dB + NF (4.2) where NF is the receiver noise ﬁgure without RF/Analog SIC, e.g., for a typical NF of 4dB [70]. Therefore, TNF is approximately 5.3dB. 4 RF/Analog Self-Interference Canceller for 2×2 MIMO Full-Duplex Transceiver 44

4.2.3 Nonlinearity Consideration

As mentioned previously, nonlinear distortion (characterized by co-channel nonlinear distortion power, i.e., CCP ) introduced by RF/Analog SIC increases the receiver noise floor, limiting the total cancellation performance of all stages and degrading effective SNR. CCP must be lower than the receiver noise floor at certain level to avoid significant SNR degradation. The total achievable cancellation (T AC) limitation is related to the co-channel nonlinear distortion, signal bandwidth, and the receiver noise figure. The total achievable cancellation (including antenna suppression, RF/Analog SIC, Digital SIC) at the receiver output under the assumption of perfect digital SIC stages is:

T AC[dB] =PTx [dBm] − (−174dBm/Hz+ (4.3) 10log10Bw + TNF + CCP )[dBm]

where PTx is the transmitted power, TNF is the total receiver noise ﬁgure with RF/Analog SIC,

Bw is the signal bandwidth, CCP is co-channel nonlinear distortion power [71]. In order not to degrade2 the effective SNR (SINR) by more than 0.4dB, the CCP should be

10dB below the receiver noise ﬂoor, i.e., −174dBm/Hz + 10log10Bw − 10dB + TNF . We can transfer the CCP requirement to the PIMD3 (Third-order inter-Modulation Distortion Power) requirement, which is the widely used metric for characterizing system or device nonlinear distortion. The typical relation between the CCP and two-tone PIMD3 , as a function of number of tones, is [71] :

P 3K3 P out1st = out1st (4.4) CCP (K) 3 2 K P 64K − 102K + 56K + 6mod( 2 ) IMD3 where Pout1st is the power of fundamental output tone. K is the number of tones or sub-carriers. Pout1st and Pout1st are CCPR (co-channel nonlinear distortion power ratio) and IMD ratio CCP (K) PIMD3 (IMR2) [71]. Usually, the number of tones or sub-carriers is large, e.g., 2048 in LTE 20MHz. 64 Subsequently, above equation can be simpliﬁed to CCP = 3 PIMD3 when the number of tones

2 Pintended Pintended SNR degradation is calculated by:10log10 Noise -10log10 Noise+CCP . 4 RF/Analog Self-Interference Canceller for 2×2 MIMO Full-Duplex Transceiver 45

K goes to inﬁnity but total input power is kept unchanged.

64 CCP [dBm] =10log10( PIMD3 ) 3 (4.5)

=PIMD3 [dBm] + 13.3dB

With this relation, we can transfer the CCP requirement to the PIMD3 requirement.

Fig. 4.2 OIP 3 requirement plot of RF/Analog SIC for varied (PTx − AS) and TNF = 0, 2, 4, 6dB according to (4.6)

The OIP 3 of RF/Analog SIC with 10dB CCP margin is given by

3 1 OIP 3[dBm] = (PTtone [dBm] − AS[dB]) − (−174dBm/Hz 2 2 (4.6) +10log10Bw − 10[dB] − 13.3[dB] + TNF [dB])

where PTtone = PTx − 3[dB] is the power per tone in the two-tone test and AS is antenna suppression/isolation previously discussed. The derivation is in Appendix A. The results plotted in Fig. 4.2 show that the OIP 3 requirement of RF/Analog SIC increases with the received SI power (PTx − AS) and decreases with TNF . Usually, in the shared antenna 4 RF/Analog Self-Interference Canceller for 2×2 MIMO Full-Duplex Transceiver 46

with circulator configuration [47,54], the AS is merely 15-25dB. Therefore, the (PTx −AS) is approximately 0-10dBm under the assumption of PTx = +20 to +30dBm, leading to the RF/Analog SIC OIP 3 requirement greater than 60dBm. Practically, it is very challenging, if not impossible, to implement circuit with such high linearity, specially in considering the fact that an amplifier is required to compensate the large insertion loss of each tap. Subsequently, shared antenna with circulator configuration may be not applicable for high power transmission FD radios. Fig. 4.3 represents SNR degradation for a given OIP 3 of the RF/Analog SIC over various the received SI power (PTx − AS) and TNF values. We observe that the SNR degradation is highly dependent on the (PTx − AS). When( PTx − AS) is as small as -25dBm to -20dBm, the RF/Analog SIC with low OIP 3 causes less than 0.2dB SNR degradation, which is a relatively minor penalty for most applications. However, for larger( PTx − AS), e.g., -10dBm or -15dBm, highly-linear RF/Analog SIC is necessary to maintain low SNR degradation.

Fig. 4.3 SNR degradation merely due to CCP for different received SI power

(PTx − AS) = -25, -20, -15, -10dBm and TNF = 0, 2, 4, 6dB.

In our previous design, QPADL3 with 47dBm IIP 3, and ALM-38140 with 55dBm IIP 3 are used. An assumed 45dB AS yields a received SI power (PTx − AS) of -15dBm. The IIP 3 and OIP 3 of an overall RF/Analog SIC are 70dBm and 25dBm, respectively. It can be seen from Fig. 4.3 that the SNR degradation due to RF/Analog SIC nonlinear distortion is as high as 6-10dB, 4 RF/Analog Self-Interference Canceller for 2×2 MIMO Full-Duplex Transceiver 47 which isa major reduction for most applications.

In our design system, PTx is +30dBm and minimum AS is approximately 45dB, yielding

(PTx − AS) = -15dBm. In addition, TNF is roughly 5.3dB, resulting in a RF/Analog SIC OIP 3 requirement of 33dBm, as shown in Fig. 4.2. We also can convert OIP 3 to IIP 3 using (A.6). Consequently, 33dBm OIP3 is corresponding to 78dBm IIP 3 under the assumption of 45dB AS.

In this case, PIMD3 generated by the RF/Analog SIC must be lower than -119dBm to maintain

CCP lower than -105.7dBm = −174dBm/Hz + 10log1020MHz − 10dB + 5.3dB, so that the SNR degradation is approximately 0.4dB, as illustrated in Fig. 4.4.

Fig. 4.4 Illustration of different power levels in 20MHz OFDM with +30dBm PTx : targeted CCP (-105.7dBm) 10dB below the receiver noise ﬂoor (-95.7dBm). PIMD3 is -105.7dBm-13.3dB = -119dBm

After deriving linearity requirement of the entire RF/Analog SIC, we investigate the IIP 3 requirements of each component to achieve overall IIP 3 of 78dBm. We assume that in the RF/Analog SIC, there is only one dominant tap, which generates the strongest nonlinear distortion. We focus on tunable attenuator and delay/phase shift module in each tap of the RF/Analog SIC, since passive devices used in each tap, e.g., coupler and power divider/combiner, are relatively linear. PIM (passive inter-modulation distortion) measurements from Anaren Microwave show that the PIMs of coupler and divider/combiner are -140dBc and -160dBc at the condition 4 RF/Analog Self-Interference Canceller for 2×2 MIMO Full-Duplex Transceiver 48 of +43dBm two-tone, which could be converted to IIP 3 of 113dBm and 123dBm, respectively. Another thing is the passive nonlinear distortion of antenna path, including PIM of antenna, as well as PIM of connector. Typical PIM of SMA connector is 103dBc under the condition of 30dBm per tone [72], namely an IIP 3 of 95dBm. Typical PIM of antenna [73] is 150dBc with +43dBm two-tone, corresponding to an IIP 3 of 118dBm. Similarly to coupler and power divider/combiner mentioned above, nonlinear distortions of SMA connectors and antennas are negligible in our case of +30dBm transmitted power.

Fig. 4.5 Overall IIP 3 contour for varied IIP 3 of attenuator and delay/phase module, red curve represents the overall IIP 3 78dBm requirement of SIC to achieve the nonlinear distortion target. The combination around corner in the contour is the optimal.

Various combinations of IIP 3 of attenuator and delay/phase are simulated and calculated with cascaded IIP 3 formula under the assumption of speciﬁc insertion loss of all the components (see Table 4.1). Overall IIP 3 contours are shown in Fig. 4.5. We can observe that when the IIP 3 of tunable attenuator is low, i.e., 43dBm, no matter how good the linearity of delay/phase module is, the overall IIP 3 saturates at 60dBm. Similarly, if the IIP 3 of delay/phase module is as low as 33dBm, keeping improving the linearity performance of attenuator would not increase 4 RF/Analog Self-Interference Canceller for 2×2 MIMO Full-Duplex Transceiver 49 overall IIP 3 since nonlinear distortion introduced by delay/phase module would be dominant. The optimum set of IIP 3 requirements for tunable attenuator and delay/phase module would be the one giving us the lowest set of IIP 3 values (to make it easier for design). Therefore, the combinations around corner in the contour are optimal. One of the most practical combinations of IIP 3 is 62dBm and 57dBm, respectively, for variable attenuator and delay/phase shift module. With this combination, the overall IIP 3 are approximately 78dBm. The IIP 3 requirements of attenuator and delay/phase module are dis- played in Table 4.1.

Table 4.1 IIP 3 requirements of each component in the RF/Analog SIC IIP 3 Requirement Insertion Loss Overall 78dBm 45dB Coupler 1 + N/A 11dB Power Divider + N/A 6.5dB Tunable Attenuator 62dBm 9.5dB Delay/phase Shift 57dBm 5dB Power Combiner + N/A 6.5dB Coupler 2 + N/A 6.5dB + Completely passive device: nonlinear distortion is negligible (IIP 3>113dBm).

4.2.4 Tuning Algorithm

The multi-tap RF/Analog SIC needs to be tuned by the optimization algorithm to emulate the SI- channel, and minimize the residualSI power over the interested frequency band. The frequency domain self-interference cancellation problem could be formulated as

B Z fc+ 2 2 min |Hchannel(f) − HSIC (f)| df (4.7) α θ d B fc− 2 where Hchannel(f) is the frequency response ofSI channel, HSIC (f) is the frequency response of canceller, fc is the center frequency, B is the cancellation bandwidth, α is the attenuation vector, θ is the phase shift vector, d is the delay vector. Frequency response of multi-tap RF/Analog SIC 4 RF/Analog Self-Interference Canceller for 2×2 MIMO Full-Duplex Transceiver 50 could be readily expressed as

N X jθi −j2πfdi HSIC (f) = αie e (4.8) i=1

th where N is the number of taps, αi is the amplitude coefficient of i tap, θi phase coefficient of th th i tap, di is delay coefficient of i tap. By substituting (4.8) into (4.7), the optimization problem can be expressed as follows:

2 f + B N Z c 2 X jθi −j2πfdi min Hchannel(f) − αie e df (4.9) α θ d B fc− 2 i=1

Integration in (4.9) could be replaced by sum since in practical theSI channel sample point is ﬁnite, represented as:

B/∆f 2 N X X jθi −j2πfldi min ∆f Hchannel(fl) − αie e (4.10) α θ d l=1 i=1 where B is the bandwidth, ∆f is the channel frequency domain sample difference. N is the number of taps. However, it has been reported in [74, 75] that the aforementioned multi-tap filter optimization problem is irregular with many local optima, meaning that it is a non-convex optimization problem. Thus, usual algorithms, e.g., gradient descent algorithm, tend to be trapped into these local optima. Particle swarm optimization (PSO) is a stochastic optimization technique developed in [76], and is appropriate for optimization surface with many local optima. PSO starts with a group of random particles and then they search for optima by updating generations in the problem space. In each iteration, each particle is updated by following two optimal solutions. The first one is the best solution that this particle has achieved so far, i.e., local optimum, represented by rlbest. The second one is the best solution that obtained so far by any particles. This best value is a global optimum and called rgbest. We find that in terms of delay, local optima are repeated at a period of reciprocal of center frequency. To illustrate this, we capture the SI channel frequency response in an anechoic chamber 4 RF/Analog Self-Interference Canceller for 2×2 MIMO Full-Duplex Transceiver 51 and use 2-tap RF/Analog SIC to emulate channel response. The optimization surface is simulated by fixing both tap amplitudes to optimal solutions, and sweeping 2-tap delays, as indicated in Fig. 4.6. It can be seen that delay 1 difference between peak 1 and peak 2 is 0.440ns. And delay 2 difference between peak 2 and peak 3 is also 0.440ns, which is exactly equal to the reciprocal of 1 center frequency ( 2.27GHz ≈ 440ps). Essentially, it is equivalent to findings in [77] that HSIC (f) 1 generates a signal with a period of and effective repetition frequency of di. di

Fig. 4.6 Optimization surface of 2-tap RF/Analog SIC with ﬁxed optimal attenuation and swept delay, revealing that local optimas are repeated at a period of reciprocal of center frequency.

Due to this characteristic, a modiﬁed version of PSO algorithm combined with simulated annealing algorithm (PSO-SA) [78, 79] is employed for tuning the parameters of the RF/Analog SIC. After single PSO iternation ﬁnished, it will jump away 1 to other potential optimal solution fc position, starting a new PSO search. In this algorithm, we could keep the single PSO search range small, and enhance overall search range by jumping between potential optima according to simulated annealing algorithm. The procedure descriptions of single PSO, and PSO-SA are shown in Algorithm 1 and Algorithm 2. 4 RF/Analog Self-Interference Canceller for 2×2 MIMO Full-Duplex Transceiver 52

The optimal solution vector (V) for this optimization problem can be found by aforementioned PSO-SA as

h i = jθe1 −j2πfldf1 jθe2 −j2πfldf2 jθfN −j2πfldfN V αf1e e αf2e e ··· αfN e e (4.11)

Algorithm 1 PSO-SA Set maxIter, I repeat Single PSO search Update the global optimal in Single PSO search. Record the current residual SI-power as rgbest (the position vector is stored in Xgbest) repeat Jump to next potenial global optimal:di=di+djump 0 Start single PSO search, record the current residual SI-power and position vector as rgbest 0 and Xgbest 0 Compute increment ∆=rgbest-rgbest If e(−∆/T ) > random number at internal (0,1) 0 Update Xgbest from Xgbest di jumps to the another potential location at the opposite direction (2djump away from current one): di=di-2djump else di keep stay at this position Endif T=α× T Set i = i + 1; until i > I Set m = m + 1; until m >maxIter or Target is achieved

4.2.5 Bandwidth

It can be seen from (4.10) that optimal RF/Analog self-interference cancellation performance is associated with the signal bandwidth. Using theSI channel measured in anechoic chamber, the optimal parameters of the multi-tap RF/Analog SIC with different signal bandwidths are calculated and simulated by the aforementioned PSO-SA. The effects of different bandwidths and 4 RF/Analog Self-Interference Canceller for 2×2 MIMO Full-Duplex Transceiver 53

Algorithm 2 Single PSO search INPUT: Number of particles(N), initial position vector (Xi) while rgbest >target or iter N Update global best rgbest and record position vector resulting in rgbest as Xgbest Update velocities and positions vector X the number of taps on the self-interference cancellation performance when the carrier frequency is 2.27GHz are shown in Fig. 4.7. It is observed from Fig. 4.7 that for a given number of taps, as the signal bandwidth increases, the self-interference cancellation performance degrade since the overall frequency response difference of SI-channel and RF/Analog SIC over the occupied frequency band increases. For instance, when the signal bandwidth is 10MHz, 2-tap RF/Analog SIC can provide approximately 46dB cancellation, while if the bandwidth is increased to 60MHz, the cancellation degrades to 22dB. On the other hand, for a given bandwidth, increasing the number of taps from 2 to 4 results in 8-10dB cancellation improvement. These phenomenons are due to the fact that wider bandwidth shows more severe frequency selectivity. Thus, more taps are required to cover the frequency selectivity.

4.2.6 Quantization Effects of components in RF/Analog SIC

As mentioned previously, the RF/Analog SIC is to reconstruct the SI-channel response. However, in practical, theSI could not be completely cancelled due to the limitation accuracy (quantization effects) of the variable attenuator and phase/delay module in the RF/Analog SIC. The effects of the quantization error of tunable attenuator and delay/phase shift module on self-interference cancellation performance of the RF/Analog SIC are analyzed in this part. And also, it can be used as benchmark of selection of variable attenuator and phase/delay module. 4 RF/Analog Self-Interference Canceller for 2×2 MIMO Full-Duplex Transceiver 54

Fig. 4.7 The effects of different bandwidths, and different number of taps, on the self-interference cancellation performance when the carrier frequency is 2.27GHz.

Variable Attenuator Quantization Error

We assume that step size of attenuator is ∆A, in dB typically, and the attenuator quantization

∆A ∆A noise i for each tap is i.i.d and uniformly distributed at internal (− 2 ,+ 2 ). The residualSI A power with attenuator quantization error (Pe ) is given by

 B/∆f N 2 A  X X 20log10(αfi)+i jθ −j2πf d  20 ei l ei Pe = E ∆f Hchannel(fl) − 10 e e (4.12)  l=1 i=1  where E is the expectation operator. N is the number of taps, αei is the optimal attenuation in th th th dB of i tap, αei the optimal phase in degree of i tap, dei the optimal delay of i tap, i is the attenuator quantization noise of ith tap. The RF/Analog SIC cancellation performance (GA) with attenuator quantization error could be expressed as P A GA = 10log e (4.13) 10 PB/∆f 2 ∆f l=1 |Hchannel(fl)| 4 RF/Analog Self-Interference Canceller for 2×2 MIMO Full-Duplex Transceiver 55

Fig. 4.8 Simulated variable attenuator step size versus cancellation performance for 10MHz, 20MHz, 40MHz, bandwidth under the assumption of no phase error, 2-tap RF/Analog SIC.

Fig. 4.8 displays the simulation results over various attenuator step sizes and signal bandwidths under the assumption of no phase error and 2-taps RF/Analog SIC. When the attenuator step size is small (< 0.1dB), for a given bandwidth, e.g., 20MHz signal, it almost has no impacts on the cancellation, only 0.5dB degradation. However, the RF/Analog SIC cancellation performance for 20MHz signal reduces to 32dB from 39dB when step size increases to 0.5dB, which is typically value for digital controlled attenuator. On the other hand, the effect of attenuator error on the cancellation performance for wideband scenario is less than that of narrowband scenario. For example, considering 0.2dB attenuator step size, the cancellation degrades by 5dB for 10MHz while for 60MHz scenario, it merely reduces less than 1dB.

Variable Delay/phase Module Quantization Error

We assume step size of delay/phase shift module is ∆φ, in degree typically, and the quantization

∆φ ∆φ error ϕi for each tap is i.i.d and uniformly distributed at internal (− 2 ,+ 2 ). The the residualSI 4 RF/Analog Self-Interference Canceller for 2×2 MIMO Full-Duplex Transceiver 56

P power with phase/delay quantization error (Pe ) can be obtained as follows:

 B/∆f N 2  X X  P j(θei+ϕi) −j2πfldei Pe = E ∆f Hchannel(fl) − αeie e (4.14)  l=1 i=1  where E is the expectation operator. N is the number of taps, αei is the optimal attenuation in th th th dB of i tap. αei the optimal phase in degree of i tap, dei the optimal delay of i tap, ϕi is the attenuator quantization noise of ith tap.

Fig. 4.9 Simulated variable phase/delay step size versus cancellation performance for 10MHz, 20MHz, 40MHz bandwidth under the assumption of no attenuation error, 2-taps RF/Analog SIC.

The RF/Analog SIC cancellation performance (GP ) with phase quantization error can be expressed as P P GP = 10log e (4.15) 10 PB/∆f 2 ∆f l=1 |Hchannel(fl)| Fig. 4.9 illustrates relation between RF/Analog SIC cancellation performance and phase/delay shifter imperfection. It can be seen that for 20MHz bandwidth, the cancellation performance reduces by approximately to 29dB when 5.6◦ step size is used, and this is typically value for 6-bit 4 RF/Analog Self-Interference Canceller for 2×2 MIMO Full-Duplex Transceiver 57 digital controlled phase shifter. On the other hand, similarly to the attenuator step size, the effects of phase error on the cancellation performance for wideband scenario is less than that of narrowband scenario. For instance, considering 5.6◦ attenuator step size, the cancellation degrades by 14dB for 10MHz while for 60MHz scenario, it merely reduce less than 3dB. The cancellation performance contours of 20MHz signal for various variable attenuator step sizes and phase/delay step sizes are shown in the Fig. 4.10. It could be observed that in order to keep insigniﬁcant performance degradation (less than 0.5dB), phase/delay module with 0.4◦ and attenuator with 0.02dB are required.

Fig. 4.10 Cancellation performance contours for various attenuator and phase/delay step sizes. Phase/delay module with 0.4◦ and attenuator with 0.02dB are required for keep cancellation reduction less than 0.5dB.

4.3 Implemented Prototypes

In this section, we implement two RF/Analog SIC prototypes for 2×2 MIMO FD transceiver. Prototype 1 is implemented with off-the-shelf variable attenuator, programmable delay/phase shift module, and other discrete components, e.g., coupler and power divider/combiner. As mentioned previously in Section 4.2.3, at least 62dBm and 57dBm IIP 3 are required for variable 4 RF/Analog Self-Interference Canceller for 2×2 MIMO Full-Duplex Transceiver 58 attenuator and delay/phase shift module, respectively. But current off-the-shelf analog controlled variable attenuator and delay/phase shift module do not meet the IIP 3 requirements. Thus, we design and implement highly-linear attenuator and delay/phase shift module, and applied to prototype2. Besides, the surface mount components are adopted and integrated on multilayer PCB to keep it compact. Further detailed discussions of two prototypes will be presented in the following.

4.3.1 Prototype 1

Fig. 4.11 RF/Analog SIC prototype1 box

For the purpose of proof-of-concept, prototype1 is implemented with commercial Avago ALM-38140 analog controlled attenuator, QPADL3 of GigaBaudics programmable delay line, PD1140 power combiner/divider of Instockwireless, and C13-6/10 6/10dB coupler of MCLI. All the components are connected with coaxial cable, ﬁtted into a box with dimensions of 331mm×425mm×114mm, as shown in Fig. 4.11. Fig. 4.12 shows the operation schematic of the entire RF/Analog SIC for FD 2×2 FD transceiver. The switches are used to change RF paths to tune different SI-channels. The controller devices are NI 6501 low-cost USB digital I/O device (for controlling switches and 4 RF/Analog Self-Interference Canceller for 2×2 MIMO Full-Duplex Transceiver 59

Fig. 4.12 Operation schematic of the entire RF/Analog SIC prototype1 for FD 2×2 transceiver

QPADL3 delay line), and NI 9265 with 4 channels 16-bit resolution analog current output (for controlling variable ALM-38140 attenuator).

4.3.2 Prototype 2

In prototype2, we apply custom-made highly-linear variable attenuator and delay/phase shift module.

Attenuator Prototype

The custom current-controlled variable attenuator is based on quadrature hybrid coupler with 2 PIN diodes. The load impedances are controlled by the biased current of PIN diodes from 50Ω to 3Ω, RF signal is either grounded when matched impedance or reﬂected to the output port. Prototype measurement reveals features of large return loss (> 20dB over 1.7 to 2.7GHz), excellent linearity (+65dBm IIP 3 at 6dB attenuation), low insertion loss (1.8dB), and 16dB attenuation dynamic range. When combined with a 16-bit DAC for current control of variable 4 RF/Analog Self-Interference Canceller for 2×2 MIMO Full-Duplex Transceiver 60 attenuator, e.g., Analog Device’s AD5668, the attenuation step size is smaller than 0.001dB.

Delay/Phase Shift Module Prototype

The delay/phase-shift module consists of a RF switched true time delay (switched TTD) with a step size of 30ps, followed by an analog-voltage controlled variable reﬂective-type phase-shifter (RTPS) with 120◦ range. The measurement shows that, from 1.7 to 2.7GHz, insertion loss of the entire module is 5dB, minimum IIP 3 of this module is up to 60dBm, which is almost 30dB greater than that of the phase shifter HMC928LP5E of Hittite Microwaves used in [43], [47], and 15dB higher than that of the QPADL3 programmable delay line3. The phase step size yields to roughly 0.01◦ using a 16-bit DAC for voltage control of the phase shifter.

RF/Analog SIC Prototype

The RF/Analog SIC prototype2 for 2×2 MIMOFD radio is implemented, consisting 6 boards fabricated on 4-layer PCB substrate4 (2 main RF boards, 2 switched true time delay line boards, 1 controller board, 1 RF switch board). They are vertically stacked each other in a 170mm × 170mm × 170mm cube, which is similar to the dimensions of typical access point (AP), as depicted in Fig. 4.13. Each main RF board is composed of 4 independent taps or channels, consisting custom-made variable attenuator and delay/phase module. 2 taps are for direct SI channel, another 2 taps are for cross SI channel, as illustrated in Fig. 4.14. Similarly, each switched TTD board consists 4 independent switched delay lines. The switch board consists of 8 switches to select RF paths, namely, Tx-Rx pairs. The controller board is to send digital or analog control signal to other boards, i.e., RF main board, to tune the variable attenuator and delay/phase shift module, and switch board to conﬁgure the RF paths. Interconnections between all the 6 boards are shown in Fig. 4.13c. This prototype is applicable for any frequency band from 1.7-2.7GHz, covering most of LTE bands. This concept can also be applied to other center frequencies and signal bandwidth.

3Measured at 2.27GHz in our lab. 44 metal layers 0.5 Oz Copper, with 2 PCB dielectric double layer cores, total of 62mils thick. The ﬁst PCB core is Rogers 4350B with 20mils, in which top layer is used to rout RF trace. The bottom layer is for RF ground. The second PCB core is FR4 for control signal. 4 RF/Analog Self-Interference Canceller for 2×2 MIMO Full-Duplex Transceiver 61

(a) (b)

(c)

Fig. 4.13 Overall 2×2 RF/Analog SIC prototype2 stack structure and interconnections: (a) PCB assembled board in a 170mm×170mm×170mm cube box (b) As- sembled PCB stack each other (c) Schematic of 2×2 RF/Analog SIC prototype PCB interconnections. 4 RF/Analog Self-Interference Canceller for 2×2 MIMO Full-Duplex Transceiver 62

(a) (b)

Fig. 4.14 Main RF board Block Diagram and Fabrication Prototype: (b) Image of Fabrication Prototype Main RF Board. (b) Main RF Board Block Diagram.

4.4 Measurement Results

To evaluate the cancellation performance of the proposed RF/Analog SIC prototype, measurements are carried out by using 20MHz OFDM centered at 2.27GHz with +30dBm. This OFDM signal has 12dB PAPR (Peak-to-Average Power Ratio), which is similar to LTE signal. The entire 2×2 MIMOFD with RF/Analog SIC is measured both in the anechoic chamber and realistic indoor environment, mezzanine of laboratory room. Fig. 4.15 depicts the entire measurement system. 20MHz OFDM signal centered at 2.27GHz is generated by Keysight N5182B vector signal generator (VSG). The signal goes through a power ampliﬁer (PA) to generate +30dBm. A linearizer for PA is to reduce the distortion and output noise. Keysight N9030A signal analyzer is to capture received OFDM signal. 4 RF/Analog Self-Interference Canceller for 2×2 MIMO Full-Duplex Transceiver 63

Fig. 4.15 RF/Analog SIC prototype test system setup.

4.4.1 Anechoic Chamber Measurements

First, we investigate prototype performance under an ideal condition, i.e., anechoic chamber. The measured results in anechoic chamber can also be applied to outdoor BS scenario with sufﬁciently high antennas. Fig. 4.16 represents all 4 individual RF/Analog SIC spectrum responses for 2×2 MIMO FD transceiver. The custom dual-polarized antenna could provide approximately 50dB isolation 4 RF/Analog Self-Interference Canceller for 2×2 MIMO Full-Duplex Transceiver 64

Fig. 4.16 SI Spectra for 2×2 MIMO RF/Analog SIC performance of 4 separated SI channels measured in anechoic chamber. for direct channel and 70dB for cross channel in the anechoic chamber. The addition of the RF/Analog SIC improves the isolation up to roughly 83dB, yielding 17-31dB RF/Analog SIC cancellation, depending on channel. During 2×2 MIMOFD operations, the total power of SI signal at the receiver is the addition of SI signal going through 2 corresponding SI channels. For example, received SI at receiver 1(Rx=1) is the addition of SI from transmitter 1 (Tx=1) and transmitter 2 (Tx=2), i.e.,TR=11 and TR=21 SI channel. Fig. 4.17 plots the combined spectrum response. It can be seen from Fig.4.17 that RF/Analog SIC could provide roughly 80dB cancellation when combined with antenna suppression.

4.4.2 Indoor Environment Measurements

The second measurement is carried out at realistic indoor environment, the mezzanine of a laboratory room (MC838), which is typical location for indoor wireless node. Fig. 4.18 illustrates +30dBm transmitted OFDM signa and the resulting spectrum response of MC838 mezzanine for each individual RF/Analog SIC. We notice that the antenna suppression degrades 4-7dB for direct SI channel and 13-15dB for cross SI channel due to rich multipath components compared 4 RF/Analog Self-Interference Canceller for 2×2 MIMO Full-Duplex Transceiver 65

Fig. 4.17 SI Spectra for 2×2 MIMO RF/Analog SIC performances of combined SI channels measured in anechoic chamber. with anechoic chamber case. In addition, the cancellation provided by RF/Analog SIC is reduced to 10-16dB.

Fig. 4.18 SI Spectra for 2×2 MIMO RF/Analog SIC performances of 4 separated SI channels measured in realistic indoor environment.

It is worth noting that RF/Analog SIC in the indoor environment mitigates SI signal by 12- 4 RF/Analog Self-Interference Canceller for 2×2 MIMO Full-Duplex Transceiver 66

14dB, yielding a total approximately 61dB isolation for 2×2 MIMO system, as depicted in Fig. 4.19.

Fig. 4.19 SI Spectra for 2×2 MIMO RF/Analog SIC performances of combined SI channels measured in realistic indoor environment.

4.4.3 Nonlinear Distortion Characteristic Measurements

In this part, nonlinear distortion characteristics of two prototypes, in terms of OIP 3, are measured with standard two-tone test with 27dBm/tone, 2MHz tone spacing (2.269GHz, 2.271GHz). For prototype1, the OIP 3 of roughly 25dBm is measured, as shown in Fig. 4.20a. Fig. 4.20b displays a typical measured result of OIP 3 for prototype2. It is improved from 25dBm to 34.3dBm by using custom-made variable attenuator and delay/phase shift module with excellent linearity. The prototype2 IIP 3 of 79.3dBm is obtained using (A.6) under the assumption of 45dB AS. To evaluate effects of RF/Analog SIC nonlinear distortion of two prototypes on theFD system, a simulation platform is built. Digital cancellation stages in [80–84] is applied. In this platform, we consider a case in which everything is ideal expect nonlinear distortion introduced 4 RF/Analog Self-Interference Canceller for 2×2 MIMO Full-Duplex Transceiver 67

(a) Measured typical 25dBm of OIP 3 for RF/Analog SIC prototype1 under 27dBm tone power.

(b) Measured typical 34.3dBm of OIP 3 for RF/Analog SIC prototype2 under 27dBm tone power.

Fig. 4.20 Measured typical OIP 3 for two prototypes 4 RF/Analog Self-Interference Canceller for 2×2 MIMO Full-Duplex Transceiver 68 by the RF/Analog SIC, i.e., no PA and LNA nonlinear distortion, and no other effects limiting digital cancellation. The residualSI power after all the cancellation stages is illustrated in Fig. 4.21. The receiver noise floor with TNF = 5.3dB is also shown in Fig. 4.21 for comparison. It can be seen that the SIC techniques applied in RF/Analog stage (second prototype) and digital stages (Stages 2 and 3) are able to suppress the SI down to -95.3dBm (totally +30dBm-(- 95.3dBm) = 125.3dB cancellation), indicating negligible 0.3dB SNR degradation caused by nonlinear distortion of this prototype, when compared with receiver noise floor (-95.6dBm). Thus, the prototype2 implemented using excellent linearity components has insignificant impact on the FD performance. While for the first prototype, the total cancellation performance is limited to +30dBm-(-89.4dBm) = 119.4dB due to the nonlinear distortions introduced by the RF/Analog SIC, so that the SNR degrades approximately 6.2dB, which matches with results in Fig. 4.3.

4.5 Concluding Remarks

This chapter considers RF/Analog SIC to suppress the internal reflection. First, we discuss coupler consideration to minimize the noise figure increment and transmitted power reduction due to the RF/Analog SIC. Subsequently, we derive linearity requirements for RF/Analog SIC and its components. For OFDM 20MHz signal with +30dBm transmitted power, if we assume that the CCP is 10dB below the receiver noise floor, the effective SNR degradation due to the CCP will be only 0.3dB. We can convert this CCP requirement to OIP 3 requirement of 33dBm. The effects of quantization error of components are analyzed. Two prototypes are implemented. The RF/Analog SIC prototypes for 2×2 FD MIMO is measured and characterized using 20MHz OFDM centered at 2.27GHz with +30dBm signal. For anechoic chamber environment, RF/Analog SIC prototypes can provide approximately 80dB cancellation for 2×2FD MIMO system when combined with custom dual-polarized antenna with 50dB isolation. In the realistic indoor environment, due to the rich multi-path effects, the RF/Analog SIC prototypes improve cancellation 10-16dB cancellation over 48dB antenna suppression, yielding approximately 61dB cancellation. And 34.3dBm OIP 3 of RF/Analog SIC prototype2 is measured. In the simulation of all cancellation stages with prototype2, residual self-interference power are 4 RF/Analog Self-Interference Canceller for 2×2 MIMO Full-Duplex Transceiver 69 almost the same with the receiver noise floor, resulting in merely 0.3dB SNR degradation.

(a) Simulated residualSI power after all cancellation stages with RF/Analog SIC prototype 1: -89.4dBm/20MHz, 6.2dB SNR degradation.

(b) Simulated residualSI power after all cancellation stages with RF/Analog SIC prototype2: -95.3dBm/20MHz, 0.3dB SNR degradation.

Fig. 4.21 Simulated residualSI power after all cancellation stages. 70

Chapter 5

High-Performance Tunable Delay/Phase Shift Module

5.1 Introduction

In Chapter 4, the IIP 3 requirement of delay/phase shift module was derived under the assumption of +30dBm 20MHz bandwidth OFDM signal, and 45dB antenna suppression (AS). At least IIP 3 of 57dBm is needed for delay/phase shift module so that the nonlinear distortion introduced by the RF/Analog SIC would not limit the overall cancellation performance and keep SNR degradation less than 0.3dB. But most of the widely used off-the-shelf delay lines or phase shifters do not meet this requirement, e.g., Hittite Microwave’s HMC928LP5E phase shifter with 30dBm IIP 3 [85], QPADL3 of GigaBaudics programmable delay line with 45dBm IIP 3 [86]1. Several delay/phase shift modules have been proposed and developed. All-pass time-delay cells with 550ps range and monotonous delay steps of 15ps is proposed for 1-2.5GHz [87]. But its IIP 3 is only -13dBm. In [88–91], delay modules are implemented by MEMS switches combined with different length of transmission line. But these designs are not suitable for RF/Analog SIC. First of all, delay step of these designs is relatively large, resulting in large tuning error [92, 93]. Besides, the range of delay, merely 400-600ps, is too narrow for SIC ﬂexible tuning. Another thing is implementation challenges: packages of many modern MEMS switches (e.g., ADG1904

1Measured at 2.27GHz in our lab.

2017/04/07 5 High-Performance Tunable Delay/Phase Shift Module 71

MEMS) are small with only 0.5 mm pitch between the RF signal ports. So MEMS switches are integrated to multilayer PCB by means of golden-wires thermosonic ball-soldering bonding which complicates the fabrication process [91]. The measurement of 360◦ reflective type phase shifter (RTPS) in [89] shows IIP 3 > 46dBm over all phase states, phase resolutions approximately 5◦.A 360◦ phase shifter is proposed in [94]. The linearity measurements show that IIP 3 is greater than 44dBm over all phase states. In [95], 100◦ RTPS using silicon-on-sapphire digitally tunable capacitors is presented for 1.8- 2.4GHz, achieving insertion loss 0.7±0.3dB, IIP 3 > 58dBm across all usable states, and 2◦ ◦ phase resolution. However, in order to provide 2 phase resolution and more usable states, ΓL reflection coefficients of two reflective loads must be different, complicating the tuning control. To fill up these gaps, we present another practical solution to highly-linear delay/phase shift module at 1.7-2.7GHz, covering most of LTE spectrum. The delay/phase shift module is composed of a RF switched true time delay line with a nominal 30ps step size, followed by an analog variable phase shifter with 120◦ range. The insertion loss of the module is 5dB and the minimum IIP 3 of this module is 60dBm. Total delay/phase shift range is approximately 1.3ns or 1000◦ for 1.7-2.7GHz. In section 5.2, we review various phase shifter architectures and topologies. An attempt is made to present the main advantages and disadvantages of each topology. In section 5.3, we discuss target specifications and design considerations of this delay/phase shift module. Prototype measurement results will be shown in Section 5.4. We conclude this chapter in Section 5.5.

5.2 Delay/Phase Shift module Architectures and Topologies

5.2.1 Switched True Time Delay (Switched TTD) Phase Shifter

In the Switched TTD phase shifter, by switching a signal between two pre-determined lengths of transmission line, it is therefore possible to realize a speciﬁc phase shift at a given frequency [96]. The time delay of a transmission line of length τ = 2πl0 , where v is the phase velocity of the 0 vp p 5 High-Performance Tunable Delay/Phase Shift Module 72 guided wave. As a result, the time delay of the two states and phase difference are given by:

2π(l + ∆l) 2πl 2π∆l ∆τ = 0 − 0 = (5.1) vp vp vp

2π∆l ∆φ = × f0 (5.2) vp where ∆l is the length difference between the two transmission lines. f0 is the operation frequency in Hz. By cascading a number of single-bit phase shifters mentioned above, we can

Fig. 5.1 Schematic diagram of switched true-time delay line create a multibit digital phase shifter. The phase shift that each bit should introduce is decided based on the desired phase shift range and resolution. For instance, if 360◦ range is controlled by 4 bits, resulting in 22.5◦ step. In this arrangement, each network switches between 0◦ and its corresponding phase shift as controlled by bits Bit0 - Bit3. The total phase shift will be given by: ∆φ = 22.5◦ × Bit0 + 45◦ × Bit1 + 90◦ × Bit2 + 180◦ × Bit3 (5.3)

The major advantage of the Switched TTD phase shifter is that it is true time delay, rendering it ideal for wideband applications. In addition, it is relatively easy to implement. Nevertheless, the length of reference transmission line and delayed transmission line are unequal, resulting in 5 High-Performance Tunable Delay/Phase Shift Module 73 amplitude imbalance between the two states. Besides, in order to realize large time delay, long transmission line length is required, leading to impractical size, especially for low frequency band, as well as large insertion loss for larger time delays.

5.2.2 High Pass-Low Pass Type Phase Shifter

The high-pass or low-pass ﬁlter can be conﬁgured as T network or Π network, consisting of series capacitors/inductors and shunt capacitors/inductors, as indicated in Fig. 5.2. The insertion phase undergoes a phase advance in high-pass network and a phase delay in low-pass network at a particular frequency ω. The design equations are provided in Table 5.1 [97].

Table 5.1 High Pass - Low Pass Type Phase Shifter Design Equations

L C φ tan( |φ| ) Low pass Π network L= Z0 sin(|φ|) C= 2 −90◦ < φ < 0◦ ω Z0ω Z tan( |φ| ) Low pass T network L= 0 2 C= sin(|φ|) −90◦ < φ < 0◦ ω Z0ω Z0 1 ◦ ◦ High pass Π network L= |φ| C= 0 < φ < 90 Z0ω sin(|φ|) ω tan( 2 ) Z0 1 ◦ ◦ High pass T network L= ω sin(|φ|) C= |φ| 0 < φ < 90 Z0ω tan( 2 )

Phase shift can be obtained by switching between the high-pass and low-pass ﬁlter, as illustrated in Fig. 5.3. Similarly to Switched TTD phase shifter, single bit high pass-low pass phase shifter can also be cascaded as a multibit phase shifter. One of the biggest advanteages of high-pass/low-pass phase shifter is the compact size [98]. It can be realized in integrated circuit with spiral inductors and Metal-Insulator-Metal (MiM) capacitors. However, the large number of switches is required, resulting in higher loss and nonlinear distortion.

5.2.3 Reﬂective-Type Phase Shifter (RTPS)

Reflective-type phase shifter (RTPS) is most commonly realized in analog form with a single control voltage. The RTPS is composited of 3-dB hybrid quadrature coupler combined with two identical reflective loads [99]. The operation is shown in the Fig .5.4. The input signal is split evenly into port 3 and port 4. At port 3, the signal gets reflected to port 1 with 180◦ + φ constant 5 High-Performance Tunable Delay/Phase Shift Module 74

Fig. 5.2 Schematic diagram of Π and T networks

Fig. 5.3 Switched high pass–low pass phase shifters 5 High-Performance Tunable Delay/Phase Shift Module 75

Fig. 5.4 Schematic diagram of RTPS operation. phase shift, and to port 2 with 90◦ + φ constant phase shift. Similarly at port 4, the signal is reflected back to port 1 with 180◦ + φ, while at port 2 is 90◦ + φ. The reflected signal would combine with incoming signal at port 1 and port 2, but at port 1 the signal will be combined destructively since the phase difference between incoming signal and reflected signal is 180◦. However, at port 2, they would be combined constructively with φ phase shift. The reflection coefficient (ΓL) of reflective load is then obtained as follows:

ZL − Z0 jφ ΓL = = |Γ| e (5.4) ZL + Z0 where ZL impedance of reﬂective load, Z0 is the characteristics impedance.

Thus, it is straightforward to obtain S21 as follow:

jφ+ π S21 = α |Γ| e 2 (5.5) where α is the loss of 3dB hybrid coupler. The corresponding phase shift range could be calculated as follows:

ZL,max ZL,min ∆φ = 2 arctan( ) − arctan( ) (5.6) Z0 Z0 where ZL,max and ZL,min are the impedance of reﬂective load when Ct(V ) = Cmax, Ct(V ) =

Cmin, respectively. 5 High-Performance Tunable Delay/Phase Shift Module 76

The RTPS is simple design that uses a minimal number of components, a copler, and two varators. Furthermore, the coupler is completely passive, meaning excellent linearity. As long as linearity of two varactor is good enough, linearity of RTPS can be guaranteed.

5.2.4 Periodically Loaded Line phase shifter

The periodically loaded line phase shifter is composed of a transmission line that are periodically loaded with varactors, as indicated in Fig. 5.5. By varying the capacitance of the varactors, the phase velocity of the resulting synthetic transmission line can also be changed [100], as shown in (5.10). The transmission lines are assumed to have Z0 unloaded characteristic impedance, vp unloaded phase velocity and l length.

Z0 Ll = (5.7) vp 1 Cl = (5.8) Z0vp s Ll ZL = (5.9) CV (V ) (Cl + l )

0 1 vp = q (5.10) CV (V ) Ll(Cl + l )

0 where the line inductance Ll and line capacitance Cl are normalized per unit length (l). vp and

ZL are varactor dependent phase velocity and characteristic impedance. The loading factor (x) of the transmission line is deﬁned as: Cmax x = V (5.11) Cll

Capacitance ratio (rC ) is the ratio of the minimum-to-maximum varactor capacitance, which is given by min CV rC = max (5.12) CV 5 High-Performance Tunable Delay/Phase Shift Module 77

max Assuming that the characteristic impedance of the synthetic line is 50Ω when CV = CV , the phase shift of each section is [100]:

l √ √ ∆φ = 2πf ( 1 + x − 1 + xrC ) (5.13) vp

Fig. 5.5 Schematic periodically loaded line phase shifter.

The transmission line in Fig. 5.5 can be replaced by distributed low-pass structures consisting of lumped inductors to reduce the size of circuits [101, 102], shown in Fig. 5.6. The design equations for the inductance (L) and the center capacitor (C) of single Π-low-pass segment with equivalent characteristic length φ between 0◦ and 90◦ are given by

tan( φ ) C = − 2 (5.14) 2πf0Z0

Z sin(φ) L = − 0 (5.15) 2πf0 where f0 is the operation frequency. For loaded line phase shifter, the larger the phase shift is, the large the insertion loss is. It has been reported in [101] that in order to keep large phase shift range (e.g., > 120◦) and low insertion loss (e.g., <2dB), approximately 5 individual sections will be required, so totally 10 varactors are needed, which not only increases the circuits size, but also degrades the linearity since the nonlinear distortion introduced by each varactor will be accumulated at the output. 5 High-Performance Tunable Delay/Phase Shift Module 78

Fig. 5.6 Schematic periodically loaded line phase shifter.

5.3 Target Speciﬁcations, Design Topologies Selections, and Considerations

The delay/phase module speciﬁcations for RF/Analog SIC application are governed by the system requirements. One of the most important parameters is the linearity, i.e., IIP 3. Other speciﬁcations are insertion loss, delay/phase tuning range, phase step size, operation bandwidth, and return loss.

• IIP 3: As stated in Chapter 4, IIP 3 of delay/phase shift module must be greater than 57dBm in order to maintain less than 0.4dB SNR degradation.

• Insertion loss: The insertion loss should be as low as possible. First of all, low insertion loss increases ability of SIC to address SI channels reﬂections with low amplitudes. Secondly, coupler with higher coupling factor can be placed prior to the variable attenuator, releasing IIP 3 requirements of variable attenuator and delay/phase module a little bit. Currently, for most of commercial phase phase shifter, nethior analog controlled or digital controlled, their insertion loss is 4-6dB. We aim to have 4-5dB insertion loss.

• Phase step size: Fine phase step size are critical since large phase step size introduces the quantization error, limiting cancellation performance. As analyzed in chapter 4, at least 0.4◦ minimum phase step is required if the cancellation provided by RF/Analog needs to be maintained around 38dB. 5 High-Performance Tunable Delay/Phase Shift Module 79

• Delay/phase tuning range: RF/Analog with large delay/phase shift tuning range is more flexible to various environments, either the reflections very close to antenna, or reflectors at further distances occurred at relatively longer times. The target is around 1.5ns true time delay, or approximately 1000◦ at 1.7-2.7GHz.

• Bandwidth: The bandwidth of the phase shifters should be wide, and consistent with RF/Analog SIC bandwidth, 1.7-2.7GHz (1GHz), covering most of LTE spectrum.

• Return loss: The return loss should be as large as possible, minimizing the reﬂected power due to the mismatch. Typically, return loss should be larger than 10dB.

Target speciﬁcations and speciﬁcations of two commercial delay/phase shift modules are listed in Table 5.2 for comparison.

Table 5.2 Design Target Speciﬁcations and Comparisons with Off-the-shelf De- lay/phase Modules

Target speciﬁcations QPADL3* HMC928LP5E* IIP 3 >57dBm 45dBm 26-30dBm Insertion loss 4-5dB 6.5dB 4dB Phase step size < 0.4◦ nominal 5ps (4◦) analog + Tuning range 1.5ns 5ns 450◦ Bandwidth 1.7-2.7GHz up to 3GHz 2-4GHz Return loss >10dB 14dB 9dB

* Measured at 2.27GHz in our lab. + Less than 0.13◦ when combined with 12-bit resolution DAC.

In order to meet target specifications above, we combine the switched true time delay (switched TTD) phase shifter with analog controlled reflective-type phase shifter (RTPS). Switched TTD has relatively large delay/phase step size and range. Analog variable RTPS compensates the large step of Switched TTD, enabling fine tuning. With this architecture, we can obtain large tunning range, at the same time, keep small phase step size. Even if the switched true time delay line has several disadvantages, we will discuss in the following to reduce its drawbacks. 5 High-Performance Tunable Delay/Phase Shift Module 80

5.3.1 Switched TTD Phase Shifter

In order to reduce the area of the adjustable switched TTD and the number of switches, 8 SP3T switches are used. The switched TTD has 12 delay lines connected by 4 SP3T switch pairs, as shown in Fig .5.7. In each switch pair, there is reference delay line path (dir), the reset of two th delay lines have its own delay characteristics (di2 + dir, di3 + dir), where i is the i switches pairs. Therefore, the total delay of switched TTD could be represented as

T = t1 + t2 + t3 + t4 (5.16)

where ti ∈ {dir, di1 + dir, di2 + dir}. In this design, d12 = 720ps, d13 = 240ps, d22 = 360ps,

Fig. 5.7 Schematic diagram of switched true-time delay line.

d23 = 180ps, d32 = 120ps, d33 = 90ps, d42 = 60ps, d43 = 30ps. So the nominal LSB (Least Signiﬁcant Bit) is 30ps. This switched TTD totally has 43 states, from 0ps (reference path) to 1260ps. As mentioned previously, amplitude imbalance is one of the most serious problems in switched TTD. One approach to mitigate this problem is to select PCB material with small dissipation factor tan δ, e.g., Rogers 4350B with tan δ=0.0031. This no only reduces the amplitude ﬂuctuations but also mitigate total insertion loss. In addition, most of insertion loss is caused by loss of switches. Thus, we keep the minimum number of switches by using SP3T instead of SPDT. GaAs SP3T switch NJG1682MD7 of New Japan Radio [103] is chosen, which features very low insertion loss (0.25dB at 1.9GHz), high isolation (30dB at 1.9GHz), excellent linearity (>70dBm 5 High-Performance Tunable Delay/Phase Shift Module 81

IIP 3). In the topology, the reference line and the delay lines controlled by the same RF SP3T switch pair must maintain a sufﬁcient distance to avoid the loss and delay error caused by the signal coupling [104]. One solution to signal coupling between two trace is to use ﬁnite grounded coplanar waveguides (FGCPW), since usually, by inserting vias along the whole line on both left and right upper ground planes, it could provide good isolation between two transmission lines [88]. The separation between the vias should not exceed one tenth of the propagating wavelength at the highest operating frequency. Thus, the SP3T devices are interconnected by using FGCPW. In order to keep the circuits compact, meander transmission line is considered. The layout is designed in ANSYS HFSS with dimensions of 55mm × 45mm × 1.5mm.

5.3.2 RTPS

As mentioned previously, the purpose of analog controlled RTPS is to compensate for large delay step size of switched TTD (nominally 30ps, ±15ps). But according to measurement results (see in the Section 5.4), the maximum individual step size is 52ps (±26ps). So practically, phase shift range demands for approximately 50◦ = 52 × 10−12(s) × 2.7 × 109(Hz) × 360◦ at maximum frequency 2.7GHz. Nevertheless, given of unwanted phase shift introduced by variable attenuator, 2 times margin is added. The phase shift range requirement for phase shifter is roughly 50◦ × 2 = 100◦.

Fig. 5.8 Reﬂective load with series inductor.

The phase shift range is dependent on the configuration of reflective load. The most common approach to implement reflective load is a single varactor. This approach can be highly effective 5 High-Performance Tunable Delay/Phase Shift Module 82 when the phase shift necessary is not large, or hyper abrupt tuning diodes are available. In [105], phase shift range is a function of varactor tuning ratio rC , which is given by

√ 1 ∆φ = 2 arctan( rC ) − arctan(√ ) (5.17) rC

Thus, for such a reflective load with varactor tuning ratio 3.5 (rC ), the phase range is approximately 67◦. The phase shift could be increased by adding a series inductor that would resonate with the varactor at the operating frequency. In this case, the reflective load could be modeled as a variable capacitance with a parasitic resistance, series inductor with parasitic resistance. To make calculation easier, the parasitic resistance of varactor and inductor is combined as a single parasitic resistance (Rs), as illustrated in Fig. 5.8. The impedance of reflective load is obtained as 1 ZL = + Rs + jωLs (5.18) jωCt(V )

The Ls is obtained as 1 1 1 Ls = 2 ( min + max ) (5.19) 2ω Ct Ct In this case, the phase shift range can be calculating using (5.6)(5.18), as follows:

1 1 max + Rs + jωLs min + Rs + jωLs jωCt jωCt ∆φ = 2 arctan( ) − arctan( ) (5.20) Z0 Z0

If we assume that the parasitic resistance RS is 0, submitting (5.19) to (5.20), the phase shift range can be simpliﬁed as follows:

1 1 1 ∆φ = 4 arctan( ( min − max )) (5.21) 2ωZ0 Ct Ct

One of the most common options for varactor in RTPS is diode varactor. However, diode varactor is considered to be highly nonlinear [106] and low Q factor [107]. Therefore, the typical performance of diode varactor is inadequate for the high demand of low insertion loss and excellent IIP 3 for the RF/Analog SIC. Thus, in this design, parascan STPTIC-27 tunable integrated capacitor [108], a version of Barium Strontium Titanate (BST), is adopted as varactor. This tun- 5 High-Performance Tunable Delay/Phase Shift Module 83

able capacitor is controlled by analog bias voltage from 0 to 20V, switched from Cmin(0.77pF ) to

Cmax(2.7pF ), with tuning ratio approximately 3.5. One of the biggest advantages of this device is the high IIP 3, which is 60-75dBm depending on the applied control voltage. We can calculate phase shift range of roughly 136◦ using above tunable capacitor speciﬁcations and (5.20). The 3-dB hybrid coupler is a wideband off-the-shelf commercially product, Anaren’s X3C22E1- 03S. We calculate insertion loss using (5.5) as follows:

2 2 S21[dB] =10log10(α |ΓL| ) = 20log10(α) ( 2 1 2 ) (Rs − Z0) + (ωLs − ) (5.22) + 10log ωCt(V ) 10 (R + Z )2 + (ωL − 1 )2 s 0 s ωCt(V )

The phase shift is controlled by changing value of tunable capacitor. However, the insertion loss is varied over control voltage as well, according to (5.22). The ﬂuctuation of insertion loss should be minimized in order to reduce the tunning error in term of amplitude. The constant insertion loss condition in this case is 2 (Rs − Z0) 2 = 1 (5.23) (Rs + Z0)

This is valid if only Rs Z0. Where Rs is obtained as follows:

1 2πfLs Rs = + (5.24) 2πfCt(V )Qc QL where Qc and QL are quality factor of tunable capacitor and inductor, respectively. In order to keep the insertion loss as constant over control, high Q inductor and tunable capacitor should be adopted. Usually, quality factor of tunable capacitor (Qc) and inductor (QL) is frequency dependent. But for the convenience of calculation, we assume that quality factors of tunable capacitor and inductor (Qc,QL) are 45, 80, respectively, and constant over 1.7-2.7GHz. So Rs is computed by using (5.24), 0.5-2.5 ohms. Ls could be calculated at 2.2GHz by using (5.19). The phase shifter circuit is simulated and designed in Advanced Design System (ADS). 5 High-Performance Tunable Delay/Phase Shift Module 84

5.4 Implemented Prototype and Characterizations

Fig. 5.9 Entire delay/phase shift module prototype.

Switched TTD and analog variable RTPS prototypes are separately fabricated on 4-layer Rogers 4350B substrate with 1.5mm thickness, and connected together with SMA connector, as illustrated in Fig. 5.9. The top layer is RF layer. Layer 2 is the RF and DC ground, 0.28 mm from the top layer. Layer 3 and layer 4 are the digital control layer used for routing the control signal. Actually, both of switched TTD and RTPS could be integrated on the same board to further reduce the size. Due to the complexity of combined control states, the switched TTD and variable RTPS are characterized separately. Performance of switched TTD and variable RTPS are measured by Keysight E5247 vector network analyzer (VNA). The IIP 3 is measured by standard two tone test (27dBm/tone) with Keysight N9010A spectrum analyzer.

5.4.1 Switched TTD Measurements

The input and output return loss are better than 14 dB for all control states over 1GHz, as shown in Fig. 5.10. The insertion loss (IL) for all delay setting (0-1260ps) is 3.1±0.6dB at center 5 High-Performance Tunable Delay/Phase Shift Module 85 frequency of 2.2GHz, as illustrated in Fig. 5.11.

Fig. 5.10 Measured input (S11) and output (S22) return loss of Switched TTD for 0-1260ps delay setting

Fig. 5.11 Measured insertion loss of Switched TTD for 0-1260ps delay setting. 5 High-Performance Tunable Delay/Phase Shift Module 86

Fig. 5.12 Measured true time delay at 1.7-2.7GHz normalized to state 0 (0ps)

Fig. 5.13 Measured delay RMS error and amplitude RMS error over 1.7-2.7GHz. 5 High-Performance Tunable Delay/Phase Shift Module 87

Fig. 5.12 plots the normalized group delay for all 0-1260ps delay settings from 1.7-2.7GHz. The accuracy of group delay measurement depends on the measurement parameters, especially on group delay aperture. VNA measurement parameters settings and corresponding accuracy are in Appendix B. We can observe that the tuning range is approximately 1.25ns for 1.7-2.7GHz, which corresponds to 1000◦ at 2.2GHz. This switched TTD prototype is with good control mono- tonicity. Average step size is 29.3ps. The maximum and minimum step size over 1GHz band and all control states are 52ps and 6ps, respectively. RMS delay error is the main ﬁgure of merit determining the performance of digital controlled delay line, which can be calculated as follows:

v u I uX ¯ 2 ∆ψRMS = t (Di − Di) (5.25) i where I is the number of states, D is the measured delay of state i, D¯ is the ideal or intended delay of state i. Similarly, RMS amplitude error is given by

v u I uX ¯ 2 ∆εRMS = t (Ai − Ai) (5.26) i where I is the number of states, A is the measured S21 amplitude of state i, A¯ is the average S21 amplitude of all states I. Fig. 5.13 shows the measurement results for RMS delay error and S21 amplitude error of switch TTD prototype. It can be seen that over 1.7-2.7GHz band, the RMS delay error is less than 9ps. And the S21 amplitude error is below 0.3dB. As mentioned above, IIP 3 is measured with standard two tones (27dBm/tone) with 2MHz tone spacing. Fig. 5.14 illustrates measured IIP 3 over all delay settings, which is almost a constant, approximately 61dBm.

5.4.2 Variable RTPS Measurements

The insertion loss (IL) of variable RTPS prototype over control voltage for 1.7-2.7GHz is shown in the Fig. 5.15. The average IL is 0.65dB with only ±0.1dB ﬂuctuation at the middle band 2.2GHz. The input and output return loss are greater than 16dB for all control and 1GHz fre- 5 High-Performance Tunable Delay/Phase Shift Module 88

Fig. 5.14 Measured IIP3 of switched TTD verus delay setting. quency band (see in the Fig. 5.16).

Fig. 5.15 Measured insertion loss over 0-20 control voltage.

The resulting of measured phase changes are given in Fig. 5.17. The phase shift covers 5 High-Performance Tunable Delay/Phase Shift Module 89

Fig. 5.16 Measured input (S11) and output (S22) return loss over 0-20 control voltage.

Fig. 5.17 Measured unwrapped phase response over 0-20V control voltage. approximately 120◦ range over 1GHz band, which is enough to compensate the aforementioned maximum step size of switched TTD. When combined with 16-bits DAC, e.g., Analog Device’s AD5668, the step size yields to roughly 0.01◦. 5 High-Performance Tunable Delay/Phase Shift Module 90

Fig. 5.18 Measured IIP 3 verus Control voltage for RTPS only,as well as entire module at maximum and minimum switched TTD setting

The IIP 3 of RTPS verus control voltage is plotted in the Fig. 5.18. For control voltage >1V, the IIP 3 is greater than 63.6dBm, and average IIP 3 over all control voltage is 70.5dBm. And the IIP 3 of entire module is measured as 59.5dBm to 63.5dBm, depending on switched TTD states and control voltage. Other performance of entire delay/phase shift module could be obtained by combining separate measurement results of switched TTD and variable RTPS. The measured speciﬁcations and requirements list in the Table 5.3. The performance prototype meets the requirements of delay/phase module for RF/Analog SIC.

5.5 Concluding Remarks

High performance tunable delay/phase shift module is developed, fabricated, and measured in this Chapter. Delay/phase shift module consists of swtiched TTD, followed by variable RTPS. Both of them are separately fabricated on Rogers 4350B, with relatively compact size. The measurement results for swtiched TTD show that insertion loss (IL) for all 43 states is 3.1±0.6dB, 1.25ns range at 2.2GHz, average 29.3ps step size, <7ps RMS delay error, and constant IIP 3 of 5 High-Performance Tunable Delay/Phase Shift Module 91

Table 5.3 Comparison Target Speciﬁcations with Measured Prototype

Target speciﬁcations Measured prototype IIP 3 >57dBm >60dBm Insertion loss 4-5dB 3.8±0.7dB Phase step size < 0.2◦ 0.01◦+ Tuning range 1.5ns 1.25ns Bandwidth 1.7-2.7GHz 1.7-2.7GHz Return loss >10dB >13dB

+ combined with 16-bit resolution DAC.

61dBm. The measurement results for analog controlled RTPS illustrate that insertion loss (IL) for all control voltage is 0.65±0.1dB and average IIP 3 is 70.5dBm IIP 3. The phase shift range is 110◦ − 130◦, compensating step size of switch TTD. Switched TTD and variabel RTPS are combined to measured, 60dBm IIP 3 is achieved, which is 3dB larger than the requirement, 57dBm. When combining 16-bits DAC, the entire delay/phase shift yields to 0.01◦ step size. 92

Chapter 6

Conclusions

6.1 Summary

In this thesis, we study the problem of strong self-interference (SI) for full-duplex (FD) communications. Firstly, we presents an investigation of the widebandSI channel characteristics of a 2×2 MIMOFD transceiver using dual-polarized antennas in Chapter 3. The measured SI-channel power delay profiles at 2.45GHz with 500MHz span in various environments: anechoic chamber, laboratory room, and corridor, reveal that the SI-channel can be represented by a multipath model consisting of two components: a quasi-static internal SI-sub-channel due to the specific Tx/Rx antenna structure and a time-varying external SI-sub-channel due to possible reflections from the surrounding environment. The quasi-static internal SI-sub-channel parameters can be derived from the Tx/Rx antenna structure specifications. The time-varying external SI-channel exhibits cluster arrival features and can be represented by a modified Saleh-Valenzuela (S-V) model with lognormal-distributed taps, and the cluster power exponentially decays with cluster arrival delay. However, the path power-versus-arrival-delay decay is exponential in a laboratory-room environment while it follows the power law in a corridor environment. The SI-channel coherence bandwidth and RMS delay spread in all three measurement environments follow normal and lognormal distributions, respectively. Due to fact that the SI-channel consist two components: a quasi-static internal SI-sub-channel a time-varying external SI-sub-channel, we propose RF/Analog SIC to suppress internal SI-sub-

2017/04/07 6 Conclusions 93 channel. In Chapter 4, we firstly discuss coupler consideration to minimize the noise figure increment and transmitted power reduction due to RF/Analog SIC. Moreover, we derive the linearity requirements of RF/Analog SIC and its components linearity requirements, so that the nonlinear distortion will not significantly degrade the performance. In addition, quantization error of attenuator and delay/phase shift module is analyzed. And then, two prototypes are built. Prototype 1 is implemented with off-the-shelf components. For the prototype2, we present a new solution to the nonlinear distortion problems by using custom-made, highly-linear components and integrated all components on a compact PCB. To evaluate the performance of the implemented prototypes, it is measured in anechoic chamber and realistic indoor environment in terms of cancellation and nonlinear characteristics. The simulation with followed digital cancellation stages reveals negligible SNR degradation due to the nonlinear distortion introduced by the RF/Analog SIC. As stated in Chapter 4, IIP 3 of 57dBm is needed for delay/phase shift module so that the nonlinear distortion introduced by the RF/Analog SIC would not limit the overall cancellation performance. But most of the widely used off-the-shelf delay lines or phase shifters do not meet this requirement. In Chapter 5, we present design of highly-linear delay/phase shift module. The delay/phase shift module is composed of a RF switched physical delay line with a nominal 30ps step size, followed by an analog variable phase shifter with 120◦ range. The IIP 3 is greater than 60dBm.

6.2 Potential Future Research

Although several issues regardingSI cancellation have been addressed in this thesis, many inter- esting related problems remain to be answered and deserve further attention. The proposed future work is given as follows:

• Size of circuit: The current RF/Analog SIC circuit is large, our prototype2 is with the dimensions of 17cm×17cm×17cm. This dimension is acceptable for access point (AP) or outdoorBS which is our initial focus. However, this prototype too big for phones and other UE devices. To enable UEs device FD communication, the RF/Analog SIC needs to be integrated in a Monolithic microwave integrated circuit (MMIC). 6 Conclusions 94

• Massive MIMO: The design should be scaled to massive MIMO extension to have more de- grees of freedom, diversity and to support more parallel streams to enhance the throughput. The current design targets 2×2 MIMO scenarios. For massive MIMO, we could replicate to each SI-channel, but a key challenge is that the complexity of circuits increase squarely. Reducing complexity is the one of most important future research works. 95

Appendix A

OIP3, IIP3 and IIP3 Derivation for SIC requirements

A.1 OIP3 and IIP3 Background

Fig. A.1 Straight-line relationship between IMD3 and the fundamental.

2017/04/07 A OIP3, IIP3 and IIP3 Derivation for SIC requirements 96

Relationship between IMD3 and the fundamental tone is shown in Fig. A.1, the power of input and output fundamental tones are plotted on a Log (dBm) scale. The fundamental tones have a slope of 1, and the slope of third-order products is 3. By extending these two lines, third-order intercept points (IP 3) can be found. If they are referred to the input, they are called third-order input intercept points (IIP 3) and if they are referred to the output, they are called output intercept points (OIP 3). IIP 3 and OIP 3 can be derived from Fig. A.1 as follows:

IMD3[dBc] IIP 3[dBm] = P [dBm] − (A.1) IN 2

IMD3[dBc] OIP 3[dBm] = P [dBm] − (A.2) OUT 2 From A.1 and A.2, the relation of IIP 3 and OIP 3 can be found as follows:

IIP 3[dBm] = OIP 3[dBm] − G[dB] (A.3)

Where G is the gain of device under test.

A.2 IIP3 Derivation for SIC requirements

CCP [dBm] = − 174dBm/Hz + TNF + 10log10Bw − 10[dB] (A.4)

PIMD3 = CCP [dBm] − 13.3[dB] (A.5) 1 IIP 3[dBm] =P − (P [dBm] − (P [dBm] − AS[dB])) (A.6) Ttone 2 IMD3 Ttone

OIP 3[dBm] = IIP 3[dBm] − AS[dB] (A.7) A OIP3, IIP3 and IIP3 Derivation for SIC requirements 97

3 1 OIP 3[dBm] = (PTtone [dBm] − AS[dB]) − (−174dBm/Hz 2 2 (A.8) +10log10Bw − 10[dB] − 13.3[dB] + TNF [dB])

Substituting (A.4)-(A.6) to (A.7), we could obtain (A.8). 98

Appendix B

Group Delay Measurement Accuracy

Fig. B.1 Accuracy of group delay measurement at 1.7GHz

Group delay is computed as the difference in phase measured at frequencies offset by the group delay aperture, as shown in (B.1). The frequency interval (∆f) between the two phase measurement points is called the aperture. The systematic portion of phase error will common mode out for narrow frequency apertures because the residual systematic errors vary slowly with frequency. Both the electrical length of the measured device and the aperture are used to predict the onset of errors due to residual systematic error [109]. The group delay curve in Fig. B.1

2017/04/07 B Group Delay Measurement Accuracy 99

Table B.1 VNA Group delay measurement parameters Freqeuncy span 1.5-3GHz Power +10dBm Sweep points 6401 Average factor 20 Group delay aperture 135MHz IF bandwidth 150Hz provides an estimate for the accuracy of the group delay measurement. VNA Group delay measurement set-up parameters are listed in Table B.1. It can be seen from Fig. B.1 that the accuracy is approximately 4ps at 1.7GHz under above parameters.

∆φ GroupDelay(ns) = ± (B.1) 360◦ × Aperture(GHz) 100

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