Scalable Parallel Performance Measurement and Analysis Tools – State-Of-The-Art and Future Challenges B

Total Page:16

File Type:pdf, Size:1020Kb

Scalable Parallel Performance Measurement and Analysis Tools – State-Of-The-Art and Future Challenges B DOI: 10.14529/jsfi140207 Scalable parallel performance measurement and analysis tools – state-of-the-art and future challenges B. Mohr1 Current large-scale HPC systems consist of complex configurations with a huge number of potentially heterogeneous components. As the systems get larger, their behavior becomes more and more dynamic and unpredictable because of hard- and software re-configurations due to fault recovery and power usage optimizations. Deep software hierarchies of large, complex system software and middleware components are required to operate such systems. Therefore, porting, adapting and tuning applications to today’s complex systems is a complicated and time-consuming task. Sophisticated integrated performance measurement, analysis, and optimization capabilities are required to efficiently utilize such systems. This article will summarize the state-of-the-art of scalable and portable parallel performance tools and the challenges these tools are facing on future extreme-scale and big data systems. Keywords: parallel programming, performance tools, extreme scale computing. Introduction Current large-scale HPC systems consist of complex configurations with a huge number of components. Each node has multiple multi-core sockets and often one or more additional accelerator units in the form of many-core nodes (e.g., Intel Xeon Phi), GPGPUs or FPGAs, resulting in a heterogeneous system architecture. Caches, memory and storage are attached to the components on various levels and are shared between components in varying degrees. Typically, there is a (huge) imbalance between the computational power of the components and the amount of memory available to these components. Thus, deep software hierarchies of large, complex system software and middleware components are required to efficiently use such systems. Therefore, porting, adapting and tuning applications to today’s complex systems is a com- plicated and time-consuming task. Sophisticated integrated performance measurement, analysis, and optimization capabilities are required to efficiently utilize such systems. However, designing and implementing efficient and useful performance tools is extremely difficult because of the same reasons. While the system and middleware software layers are designed to be transparent, they are typically not transparent with respect to performance. This performance intransparency will result in escalation of unforeseen problems to higher layers, including the application. This is not really a new problem, but certain properties of current large-scale and future extreme-scale systems significantly increase its severity and significance: At extreme-scale scale, there always will be failing components in the system, which has • a large impact on performance. A real-world application will probably never run on the exact same configuration twice. Load balancing issues limit the success even on moderately parallel systems, and the • challenge of data locality will become another severe issue which has to be addressed by appropriate mechanisms and tools. Dynamic power management, e.g., at hardware level inside a CPU or accelerator, will result • in performance variability between cores, nodes, and across different runs. The alternative to run at lower but system-wide consistent speed without dynamic power adjustments may not be an option in the future. 1J¨ulich Supercomputing Centre, Forschungszentrum J¨ulich GmbH, J¨ulich, Germany 108 Supercomputing Frontiers and Innovations B. Mohr The challenge of predicting application performance at extreme scale will make it difficult • to detect a performance problem if it is escalated undetected to the application level. The ever growing higher integration of components into a single chip and the use of more • and more hardware accelerators makes it more difficult to monitor application performance and move performance data out of the system unless special hardware support will be integrated into future systems. Altogether this will require an integrated, collaborative, and holistic approach to handle performance issues and correctly detect and analyze performance problems. In the following, we will summarize the state-of-the-art of scalable and portable parallel performance tools. Next, we discuss the various methods and approaches regarding tool portability, scalability, and integra- tion. The article closes with an outlook on the challenges tools will face on future extreme-scale and big data systems. 1. Overview of state-of-the-art parallel performance tools Research on parallel performance tools has a long history. First tools appeared at the same time as the first parallel computer systems back in the 1980s and early 90s [1]. Meanwhile, many performance instrumentation, measurement, analysis and visualization tools exist, and summarizing and listing all major methods, approaches and tools is impossible in a short journal paper. Therefore, in the following section we concentrate on the major tool sets that are (i) portable, i.e., they can be used on more than one of today’s dominating architectures: Cray, IBM BlueGene, Fujitsu K computer, and Linux/UNIX clusters, (ii) scalable, i.e., it was demonstrated that they can be successfully used for an application executing on a couple of thousand nodes, (iii) versatile, i.e., they allow the performance analysis of all levels of today’s HPC systems: message passing between nodes, multi-threading and multi-tasking inside nodes, and offloading to accelerators, and (iv) supported, i.e., there are well-established groups or organizations behind them which maintain and further develop them. The structure of the following subsections is modelled after and re-uses excerpts from the VI-HPS Tools Guide [2], which also includes descriptions of further tools. 1.1. TAU TAU [3, 4] is a comprehensive profiling and tracing toolkit that supports performance eval- uation of programs written in C++, C, UPC, Fortran, Python, and Java. It is a robust, flexible, portable, and integrated framework and toolset for performance instrumentation, measurement, analysis, and visualization of large-scale parallel computer systems and applications. TAU sup- ports both direct measurement as well as sampling modes of instrumentation and interfaces with external packages such as PAPI [25] or tools like Score-P, Scalasca, and Vampir (all described in the following sections). TAU is available under a BSD-style license. Typical Workflow TAU allows the user to instrument the program in a variety of ways including rewriting the binary using tau rewrite or runtime pre-loading of shared objects using tau exec. Source- level instrumentation typically involves substituting a compiler in the build process with a TAU compiler wrapper. This wrapper uses a given TAU configuration to link in the TAU library. At 2014, Vol. 1, No. 2 109 Scalable Parallel Performance Measurement and Analysis Tools — State-of-the-Art and... runtime, a user may specify different TAU environment variables to control the measurement options chosen for the performance experiment. This allows the user to generate call-path pro- files, specify hardware performance counters, turn on event-based sampling, generate traces, or specify memory instrumentation options. Figure 1. TAU main profile window. Each line shows a flattened histogram of a selected perfor- mance metric for a specific thread or task. The different colors represent the different program regions (e.g., functions, loops, parallel sections, etc.). The display allows to get a quick overview via comparing the differences/commonalities of the different threads/tasks. Clicking on a line label brings up more detailed information about the selected thread or task. Clicking on a col- ored region brings up more detailed information about the selected program region. The menu bar allows to choose the performance metric shown or to launch further, more detailed displays like a call-graph or communication matrix display. Results from larger performance experiments can be more easily analyzed with the 3D displays of TAU, see fig. 2. Performance-analysis results may be stored in TAUdb, a database for cross-experiment analysis and advanced performance data mining operations using TAU’s PerfExplorer tool [5]. It may be visualized using ParaProf, TAU’s profile browser that can show the extent of performance variation and compare executions, see fig. 1. Supported platforms IBM Blue Gene/P/Q, NVIDIA and AMD GPUs and Intel MIC systems, Cray XE/XK/XC30, SGI Altix, Fujitsu K Computer (FX10), NEC SX-9, Solaris & Linux clusters (x86/x86 64, MIPS, ARM), Windows, Apple Mac OS X. Supported Runtime Layers MPI, OpenMP (using GOMP, OMPT, and Opari instrumentation), Pthread, MPC Threads, Java Threads, Windows Threads, CUDA, OpenCL, OpenACC. 110 Supercomputing Frontiers and Innovations B. Mohr Figure 2. TAU 3D profile view. It displays the distribution of two selected performance metrics (encoded via height and color) over the axes program regions and threads/tasks. 1.2. HPCToolkit HPCToolkit [6, 7] is an integrated suite of tools for measurement and analysis of program performance on computers ranging from multi-core desktop systems to the largest supercomput- ers. HPCToolkit provides accurate measurements of a program’s work, resource consumption, and inefficiency, correlates these metrics with the program’s source code, works with multilingual, fully optimized binaries, and has very low measurement overhead. HPCToolkit’s measurements provide support for analyzing a program’s execution cost, inefficiency, and scaling characteristics
Recommended publications
  • D5.1 Report on Performance and Tuning of Runtime Libraries for ARM
    D5.1 Report on performance and tuning of runtime libraries for ARM Architecture Version 1.0 Document Information Contract Number 288777 Project Website www.montblanc-project.eu Contractual Deadline M12 Dissemintation Level PU Nature Report Coordinator Alex Ramirez (BSC) Contributors Isaac Gelado (BSC), Xavier Martorell (BSC), Judit Gimenez (BSC), Harald Servat (BSC), Bernd Mohr (JUELICH), Daniel Lorenz (JUELICH), Marc Schluetter (JUELICH) Reviewers Chris Adeniyi-Jones (ARM) Keywords compiler, runtime system, parallelism, instrumentation, perfor- mance analysis Notices: The research leading to these results has received funding from the European Community's Seventh Framework Programme (FP7/2007-2013) under grant agreement no 288777 c 2011 Mont-Blanc Consortium Partners. All rights reserved. D5.1 - Report on performance and tuning of runtime libraries for ARM Architecture Version 1.0 Change Log Version Description of Change v0.1 Initial draft released to the WP5 contributors v0.2 Draft version sent to internal reviewer v1.0 Final version sent to the EU 2 D5.1 - Report on performance and tuning of runtime libraries for ARM Architecture Version 1.0 Contents Executive Summary 4 1 Introduction 5 2 Runtime Libraries 6 2.1 Mercurium compiler . .6 2.1.1 Porting to ARM-v7 . .6 2.1.2 Fortran support . .6 2.2 Nanos++ . .7 2.3 Extrae instrumentation library . .8 2.4 Scalasca support for the ARM platform . .8 3 Performance Analysis and Tuning 11 4 Conclusions 14 3 D5.1 - Report on performance and tuning of runtime libraries for ARM Architecture Version 1.0 Executive Summary In this Mont-Blanc deliverable we present the current status of porting to the ARM architecture of the OmpSs (Mercurium compiler and Nanos++ runtime system), the Extrae instrumentation library and the Scalasca instrumentation facilities.
    [Show full text]
  • Scalasca User Guide
    Scalasca 2.5 User Guide Scalable Automatic Performance Analysis March 2019 The Scalasca Development Team [email protected] The entire code of Scalasca v2 is licensed under the BSD-style license agreement given below, except for the third-party code distributed in the 'vendor/' subdirectory. Please see the corresponding COPYING files in the subdirectories of 'vendor/' included in the distribution tarball for details. Scalasca v2 License Agreement Copyright © 1998–2019 Forschungszentrum Jülich GmbH, Germany Copyright © 2009–2015 German Research School for Simulation Sciences GmbH, Jülich/Aachen, Germany Copyright © 2014–2015 RWTH Aachen University, Germany Copyright © 2003–2008 University of Tennessee, Knoxville, USA Copyright © 2006 Technische Universität Dresden, Germany All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: • Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. • Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. • Neither the names of – the Forschungszentrum Jülich GmbH, – the German Research School for Simulation Sciences GmbH, – the RWTH Aachen University, – the University of Tennessee, – the Technische Universität Dresden, nor the names of their contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DIS- CLAIMED.
    [Show full text]
  • TAU, PAPI, Scalasca and Vampir
    Parallel Performance Evaluation Tools: TAU, PAPI, Scalasca and Vampir Two day tutorial at LLNL Building 453 R1001 (Armadillo), May 26-27, Livermore, CA Sameer Shende [email protected] http://www.paratools.com/llnl09 Outline Slide # • Outline and workshop goals 2 • Part I: TAU: A quick reference 8 • Part II: Introduction to performance engineering 77 • Part III: PAPI 105 • Part IV: TAU 119 • Part V: Vampir/VNG 266 • Part VI: Scalasca/KOJAK 307 • Lab Session: PAPI, TAU, Vampir and Scalasca examples 385 2 1 Outline • Day 1: – Introduction to performance evaluation tools: TAU, PAPI, Scalasca, and Vampir – Hands-on: – TAU instrumentation at routine, loop level, PAPI hardware performance counter data collection, derived metrics, analyzing performance using TAU’s paraprof profile browser, using Performance database (PerfDMF), memory evaluation, leak detection • Day 2: – Scalasca, TAU PerfExplorer, VampirServer – Hands-on: – Scalasca bottleneck detection tools, PerfExplorer, trace visualization, workshop examples including the NAS Parallel Benchmarks 3.1 3 Workshop Goals • This tutorial is an introduction to portable performance evaluation tools. • You should leave here with a better understanding of… – Concepts and steps involved in performance evaluation – Understanding key concepts in improving and understanding code performance – How to collect and analyze data from hardware performance counters using PAPI – How to instrument your programs with TAU – Automatic instrumentation at the routine level and outer loop level – Manual instrumentation
    [Show full text]
  • Score-P – a Joint Performance Measurement Run-Time Infrastructure for Periscope, Scalasca, TAU, and Vampir
    VIRTUAL INSTITUTE – HIGH PRODUCTIVITY SUPERCOMPUTING Score-P – A Joint Performance Measurement Run-Time Infrastructure for Periscope, Scalasca, TAU, and Vampir VI-HPS Team VIRTUAL INSTITUTE – HIGH PRODUCTIVITY SUPERCOMPUTING Congratulations!? . If you made it this far, you successfully used Score-P to . instrument the application . analyze its execution with a summary measurement, and . examine it with one the interactive analysis report explorer GUIs . ... revealing the call-path profile annotated with . the “Time” metric . Visit counts . MPI message statistics (bytes sent/received) . ... but how good was the measurement? . The measured execution produced the desired valid result . however, the execution took rather longer than expected! . even when ignoring measurement start-up/completion, therefore . it was probably dilated by instrumentation/measurement overhead SCORE-P AND SCALASCA PERFORMANCE TOOLS TRAINING, NERSC, JULY 26, 2016 2 VIRTUAL INSTITUTE – HIGH PRODUCTIVITY SUPERCOMPUTING Performance analysis steps . 0.0 Reference preparation for validation . 1.0 Program instrumentation . 1.1 Summary measurement collection . 1.2 Summary analysis report examination . 2.0 Summary experiment scoring . 2.1 Summary measurement collection with filtering . 2.2 Filtered summary analysis report examination . 3.0 Event trace collection . 3.1 Event trace examination & analysis SCORE-P AND SCALASCA PERFORMANCE TOOLS TRAINING, NERSC, JULY 26, 2016 3 VIRTUAL INSTITUTE – HIGH PRODUCTIVITY SUPERCOMPUTING BT-MZ summary analysis result scoring % scorep-score scorep_bt-mz_B.8x4.<jobid>/profile.cubex . Report scoring as textual Estimated aggregate size of event trace: 40 GB Estimated requirements for largest trace buffer (max_buf): 6 GB output Estimated memory requirements (SCOREP_TOTAL_MEMORY): 6 GB (warning: The memory requirements cannot be satisfied by Score-P to avoid intermediate flushes when tracing.
    [Show full text]
  • Profiling and Tracing Tools for Performance Analysis of Large Scale Applications
    Available online at www.prace-ri.eu Partnership for Advanced Computing in Europe Profiling and Tracing Tools for Performance Analysis of Large Scale Applications Jerry Erikssonb, Pedro Ojeda-Mayb, Thomas Ponweisera,*, Thomas Steinreitera aRISC Software GmbH, Softwarepark 35, 4232 Hagenberg, Austria bHigh Performance Computing Center North (HPC2N), MIT Huset, Umeå Universitet, 901 87 Umeå, Sweden Abstract The usage of modern profiling and tracing tools is vital for understanding program behaviour, performance bottlenecks and optimisation potentials in HPC applications. Despite their obvious benefits, such tools are still not that widely adopted within the HPC user community. The two main reasons for this are firstly unawareness and secondly the sometimes inhibitive complexity of getting started with these tools. In this work we aim to address this issue by presenting and comparing the capabilities of four different performance analysis tools, which are 1) HPCToolkit, 2) Extrae and Paraver, 3) SCALASCA and 4) the Intel Trace Analyzer and Collector (ITAC). The practical usage of these tools is demonstrated based on case studies on the widely used molecular dynamics simulation code GROMACS. Keywords: Performance Analysis, Profiling, Tracing, HPCToolkit, Extrae, Paraver, SCALASCA, ITAC, GROMACS 1. Introduction Background of this work is a survey conducted by the PRACE project in the beginning of 2016. In order to develop links to European Centres of Excellence (CoEs) and to understand their needs with respect to high performance computing, a questionnaire has been developed and circulated to each of eight selected CoEs. The results of this survey are summarised in the PRACE-4IP deliverable D7.3 [1]. One finding of this survey which motivated the present work is that from the CoE’s answers it is evident that still the use of profiling tools for code optimization is not that well established.
    [Show full text]
  • Best Practice Guide Modern Processors
    Best Practice Guide Modern Processors Ole Widar Saastad, University of Oslo, Norway Kristina Kapanova, NCSA, Bulgaria Stoyan Markov, NCSA, Bulgaria Cristian Morales, BSC, Spain Anastasiia Shamakina, HLRS, Germany Nick Johnson, EPCC, United Kingdom Ezhilmathi Krishnasamy, University of Luxembourg, Luxembourg Sebastien Varrette, University of Luxembourg, Luxembourg Hayk Shoukourian (Editor), LRZ, Germany Updated 5-5-2021 1 Best Practice Guide Modern Processors Table of Contents 1. Introduction .............................................................................................................................. 4 2. ARM Processors ....................................................................................................................... 6 2.1. Architecture ................................................................................................................... 6 2.1.1. Kunpeng 920 ....................................................................................................... 6 2.1.2. ThunderX2 .......................................................................................................... 7 2.1.3. NUMA architecture .............................................................................................. 9 2.2. Programming Environment ............................................................................................... 9 2.2.1. Compilers ........................................................................................................... 9 2.2.2. Vendor performance libraries
    [Show full text]
  • CUBE 4.3.4 – User Guide Generic Display for Application Performance Data
    CUBE 4.3.4 – User Guide Generic Display for Application Performance Data April 3, 2016 The Scalasca Development Team [email protected] ii Chapter 0. Copyright Copyright Copyright © 1998–2016 Forschungszentrum Jülich GmbH, Germany Copyright © 2009–2015 German Research School for Simulation Sciences GmbH, Jülich/Aachen, Germany All rights reserved. Redistribution and use in source and binary forms, with or without modification, are per- mitted provided that the following conditions are met: • Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. • Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. • Neither the names of Forschungszentrum Jülich GmbH or German Research School for Simulation Sciences GmbH, Jülich/Aachen, nor the names of their con- tributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIB - UTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITN - ESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDI - NG, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVIC - ES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIB - ILITY OF SUCH DAMAGE.
    [Show full text]
  • Scalasca 2.3 User Guide Scalable Automatic Performance Analysis
    Scalasca 2.3 User Guide Scalable Automatic Performance Analysis May 2016 The Scalasca Development Team [email protected] The entire code of Scalasca v2 is licensed under the BSD-style license agreement given below, except for the third-party code distributed in the 'vendor/' subdirectory. Please see the corresponding COPYING files in the subdirectories of 'vendor/' included in the distribution tarball for details. Scalasca v2 License Agreement Copyright © 1998–2016 Forschungszentrum Jülich GmbH, Germany Copyright © 2009–2015 German Research School for Simulation Sciences GmbH, Jülich/Aachen, Germany Copyright © 2014–2015 RWTH Aachen University, Germany Copyright © 2003–2008 University of Tennessee, Knoxville, USA Copyright © 2006 Technische Universität Dresden, Germany All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: • Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. • Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. • Neither the names of – the Forschungszentrum Jülich GmbH, – the German Research School for Simulation Sciences GmbH, – the RWTH Aachen University, – the University of Tennessee, – the Technische Universität Dresden, nor the names of their contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DIS- CLAIMED.
    [Show full text]
  • The Scalasca Performance Toolset Architecture
    CONCURRENCY AND COMPUTATION: PRACTICE AND EXPERIENCE Concurrency Computat.: Pract. Exper. 2010; 22:702–719 Prepared using cpeauth.cls [Version: 2002/09/19 v2.02] The Scalasca performance toolset architecture Markus Geimer1, Felix Wolf1,2,3, Brian J.N. Wylie1, Erika Abrah´am´ 3, Daniel Becker1,3, Bernd Mohr1 1 J¨ulich Supercomputing Centre, Forschungszentrum J¨ulich, 52425 J¨ulich, Germany 2 German Research School for Simulation Sciences, 52062 Aachen, Germany 3 Computer Science Department, RWTH Aachen University, 52056 Aachen, Germany SUMMARY Scalasca is a performance toolset that has been specifically designed to analyze parallel application execution behavior on large-scale systems with many thousands of processors. It offers an incremental performance-analysis procedure that integrates runtime summaries with in-depth studies of concurrent behavior via event tracing, adopting a strategy of successively refined measurement configurations. Distinctive features are its ability to identify wait states in applications with very large numbers of processes and to combine these with efficiently summarized local measurements. In this article, we review the current toolset architecture, emphasizing its scalable design and the role of the different components in transforming raw measurement data into knowledge of application execution behavior. The scalability and effectiveness of Scalasca are then surveyed from experience measuring and analyzing real-world applications on a range of computer systems. key words: parallel computing, performance analysis,
    [Show full text]
  • Score-P – a Joint Performance Measurement Run-Time Infrastructure for Periscope, Scalasca, TAU, and Vampir
    Score-P – A Joint Performance Measurement Run-Time Infrastructure for Periscope, Scalasca, TAU, and Vampir Markus Geimer1), Bert Wesarg2) With contributions from Andreas Knüpfer2) and Christian Rössel1) 1)FZ Jülich, 2)ZIH TU Dresden Fragmentation of tools landscape • Several performance tools co-exist • With own measurement systems and output formats • Complementary features and overlapping functionality • Redundant effort for development and maintenance • Limited or expensive interoperability • Complications for user experience, support, training Vampir Scalasca TAU Periscope VampirTrace EPILOG / TAU native Online OTF CUBE formats measurement EuroMPI‘12: Hands-on Practical Hybrid Parallel Application Performance Engineering SILC Project Idea • Start a community effort for a common infrastructure – Score-P instrumentation and measurement system – Common data formats OTF2 and CUBE4 • Developer perspective: – Save manpower by sharing development resources – Invest in new analysis functionality and scalability – Save efforts for maintenance, testing, porting, support, training • User perspective: – Single learning curve – Single installation, fewer version updates – Interoperability and data exchange • SILC project funded by BMBF • Close collaboration PRIMA project funded by DOE EuroMPI‘12: Hands-on Practical Hybrid Parallel Application Performance Engineering Partners • Forschungszentrum Jülich, Germany • German Research School for Simulation Sciences, Aachen, Germany • Gesellschaft für numerische Simulation mbH Braunschweig, Germany •
    [Show full text]
  • The Arm Architecture for Exascale HPC
    The Arm Architecture for Exascale HPC EXALAT - Lattice Field Theory at the Exascale Dr. Olly Perks - Principal HPC Engineer [email protected] 17th June 2020 © 2020 Arm Limited (or its affiliates) Arm and our role in HPC © 2020 Arm Limited (or its affiliates) What is Arm? • Arm designs IP (such as the Arm ISA) • We do not manufacture hardware • 32-bit RISC instruction encoding • More simplistic but limiting • AArch64 execution state • Atomic memory ops • Half-precision float • Pointer authentication • A64 instruction set • Type2 hypervisor support • RAS support • Nested virtualization 4 © 2020 Arm Limited (or its affiliates) • Statistical profiling • Complex float Why Arm? Especially for Infrastructure / HPC / Scientific Computing / ML? Hardware Software • Flexibility: Allow vendors to differentiate • All based on the same instruction set • Speed and cost of development • Commonality between hardware • Reuse of software • Provide different licensing • Core - Reference design (A53/A72/N1) • Comprehensive software ecosystem • Architecture - Design your own (TX2, A64FX) • Operating systems, compilers, libraries, tools • Not just vendor - third party too • Other hardware components • NoCs, GPUs, memory controllers • “Building blocks” design • Large community • Everything from Android to HPC • Architecture validation for correctness 5 © 2020 Arm Limited (or its affiliates) Variation in the Processor Market Marvell (Cavium) Ampere (X-Gene) eMag Quicksilver Fujitsu Huawei (HiSilicon) 1616 Amazon (Annapurna) EPI / SiPearl Other PHYTIUM 6 © 2020 Arm Limited (or its affiliates) Each generation brings faster performance and new infrastructure specific features 5nm 7nm+ 7nm Poseidon 16nm Zeus Platform Ares Platform Cosmos Platform Platform “N1” 2021 2020 Today 2018 30% Faster System Performance per Generation + New Features Limited Arm © 2018 © Not Just Hardware Applications Performance Open-source, owned, commercial ISV codes, … Engineering … PBS Pro, Altair IBM LSF, SLURM, Arm Forge (DDT, MAP), Rogue Wave, HPC Toolkit, Schedulers Containers, Interpreters, etc.
    [Show full text]
  • Large-Scale Performance Analysis of PFLOTRAN with Scalasca
    Mitglied der Helmholtz-Gemeinschaft Large-scale performance analysis of PFLOTRAN 2011-05-26 | 2011-05-26 [email protected] Jülich Supercomputing Centre Brian J. N. Wylie & Mar with Scalasca kus Geimer Overview Dagstuhl challenge ■ PFLOTRAN at large-scale on Cray XT5 & IBM BG/P Scalasca performance analysis toolset ■ Overview of architecture and usage ■ Instrumentation of PFLOTRAN & PETSc ■ Summary & trace measurement experiments ■ Analysis report & trace exploration Scalasca scalability improvement ■ Unification of definition identifiers Conclusions 2011-05-26 | CUG2011 (Fairbanks) Brian J. N. Wylie, Jülich Supercomputing Centre 2 Dagstuhl challenge Demonstrate performance measurement and analysis of PFLOTRAN using “2B” problem dataset and more than 10,000 MPI processes Challenge issued for Dagstuhl seminar 10181 (3-7 May 2010) on “Program development for extreme-scale computing” ■ two months notice with download/build/run instructions ■ accounts/allocations provided by VI-HPS & INCITE/PEAC ■ IBM BG/P (jugene.fz-juelich.de) ■ Cray XT5 (jaguar.nccs.ornl.gov) ■ numerous research groups and vendors presented their results and discussed issues encountered ■ http://www.dagstuhl.de/10181 2011-05-26 | CUG2011 (Fairbanks) Brian J. N. Wylie, Jülich Supercomputing Centre 3 PFLOTRAN 3D reservoir simulator actively developed by LANL/ORNL/PNNL ■ approx. 80,000 lines of Fortran9X, combining solvers for ■ PFLOW non-isothermal, multi-phase groundwater flow ■ PTRAN reactive, multi-component contaminant transport ■ employs PETSc, LAPACK, BLAS & HDF5 I/O libraries ■ 87 PFLOTRAN + 789 PETSc source files ■ parallel I/O tuning via PERI active liaison ■ “2B” input dataset run for 10 timesteps ■ uses 3-dimensional (non-MPI) PETSc Cartesian grid ■ TRAN(sport) step scales much better than FLOW step ■ FLOW step generally faster, but crossover at larger scales 2011-05-26 | CUG2011 (Fairbanks) Brian J.
    [Show full text]