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Photonic Encryption Using All Optical Logic

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Photonic Encryption Using All Optical Logic SANDIA REPORT SAND 2003-4474 Unlimited Release Printed December 2003 Photonic Encryption using All Optical Logic Jason D Tang, Thomas D Tarman, and Lyndon G Pierson Ethan L. Blansett and G. Allen Vawter Perry J. Robertson and Richard Schroeppel Prepared by Sandia National Laboratories Albuquerque, New Mexico 87185 and Livermore, California 94550 Sandia is a multiprogram laboratory operated by Sandia Corporation, a Lockheed Martin Company, for the United States Department of Energy’s National Nuclear Security Administration under Contract DE-AC04-94AL85000. Approved for public release; further dissemination unlimited. Issued by Sandia National Laboratories, operated for the United States Department of Energy by Sandia Corporation. NOTICE: This report was prepared as an account of work sponsored by an agency of the United States Government. Neither the United States Government, nor any agency thereof, nor any of their employees, nor any of their contractors, subcontractors, or their employees, make any warranty, express or implied, or assume any legal liability or responsibility for the accuracy, completeness, or usefulness of any information, apparatus, product, or process disclosed, or represent that its use would not infringe privately owned rights. Reference herein to any specific commercial product, process, or service by trade name, trademark, manufacturer, or otherwise, does not necessarily constitute or imply its endorsement, recommendation, or favoring by the United States Government, any agency thereof, or any of their contractors or subcontractors. The views and opinions expressed herein do not necessarily state or reflect those of the United States Government, any agency thereof, or any of their contractors. Printed in the United States of America. This report has been reproduced directly from the best available copy. Available to DOE and DOE contractors from U.S. Department of Energy Office of Scientific and Technical Information P.O. Box 62 Oak Ridge, TN 37831 Telephone: (865)576-8401 Facsimile: (865)576-5728 E-Mail: [email protected] Online ordering: http://www.doe.gov/bridge Available to the public from U.S. Department of Commerce National Technical Information Service 5285 Port Royal Rd Springfield, VA 22161 Telephone: (800)553-6847 Facsimile: (703)605-6900 E-Mail: [email protected] Online order: http://www.ntis.gov/help/ordermethods.asp?loc=7-4-0#online 2 SAND2003-4474 Unlimited Release Printed December 2003 Photonic Encryption using All Optical Logic Jason D. Tang, Thomas D. Tarman, and Lyndon G. Pierson Advanced Networking Integration Department Ethan L. Blansett and G. Allen Vawter RF Microsystems Technologies Perry J. Robertson RF and Opto Microsystems Richard C. Schroeppel Crypto and Info Systems Surety Sandia National Laboratories P.O. Box 5800 Albuquerque, NM 87185-0806 Abstract With the build-out of large transport networks utilizing optical technologies, more and more capacity is being made available. Innovations in Dense Wave Division Multiplexing (DWDM) and the elimination of optical-electrical-optical conversions have brought on advances in communication speeds as we move into 10 Gigabit Ethernet and above. Of course, there is a need to encrypt data on these optical links as the data traverses public and private network backbones. Unfortunately, as the communications infrastructure becomes increasingly optical, advances in encryption (done electronically) have failed to keep up. This project examines the use of optical logic for implementing encryption in the photonic domain to achieve the requisite encryption rates. In order to realize photonic encryption designs, technology developed for electrical logic circuits must be translated to the photonic regime. This paper examines two classes of all optical logic (SEED, gain competition) and how each discrete logic element can be interconnected and cascaded to form an optical circuit. Because there is no known software that can model these devices at a circuit level, the functionality of the SEED and gain competition devices in an optical circuit were modeled in PSpice. PSpice allows modeling of the macro characteristics of the devices in context of a logic element as opposed to device level computational modeling. By representing light intensity as voltage, “black box” models are generated that accurately represent the intensity response and logic levels in both technologies. By modeling the behavior at the systems level, one can incorporate systems design tools and a simulation environment to aid in the overall functional design. Each black box model of the SEED or gain competition device takes certain parameters (reflectance, intensity, input response), and models the optical ripple and time delay characteristics. These “black box” models are interconnected and cascaded in an encrypting/scrambling algorithm based on a study of candidate encryption algorithms. We found that a low gate count, cascadeable encryption algorithm is most feasible given device and processing constraints. The modeling and simulation of optical designs using these components is proceeding in parallel with efforts to perfect the physical devices and their interconnect. We have applied these techniques to the development of a “toy” algorithm that may pave the way for more robust optical algorithms. These design/modeling/simulation techniques are now ready to be applied to larger optical designs in advance of our ability to implement such systems in hardware. 3 [this page left intentionally blank] 4 Table of Contents 1. Introduction................................................................................................................................. 6 2. Photonic Encryptor Usage .......................................................................................................... 7 3. Overview of S-SEED Device Performance and Logic............................................................... 9 3.1. Carrier Sweep-out Time Measurements of 1550-nm SEEDs............................................ 10 3.2. Cascading of Discrete S-SEEDs at 865 nm ....................................................................... 11 3.3. XOR Logic Gate Demonstration ....................................................................................... 13 3.4. Substrate-Mode Microoptic Interconnects......................................................................... 15 4. PSpice modeling of S-SEED .................................................................................................... 19 4.1. PSpice Model..................................................................................................................... 19 4.2. Diode Electrical Model...................................................................................................... 19 4.3. Responsivity Curves .......................................................................................................... 19 4.4. Reflectivity Curve.............................................................................................................. 19 4.5. Gate Operation................................................................................................................... 19 5. S-SEED Switching Behavior .................................................................................................... 25 5.1. S-SEED Circuit.................................................................................................................. 25 5.2. Measurement Setup............................................................................................................ 25 5.3. Simulation Setup................................................................................................................ 25 6. Characterization of the Optical Gate......................................................................................... 29 7. Optical Logic Gate Simulation ................................................................................................. 31 8. Gain Competition Optical Logic............................................................................................... 34 8.1. Processing Challenges ....................................................................................................... 35 8.2. Packaging and Interconnect Issues .................................................................................... 36 8.3. Future Developmental Directions...................................................................................... 36 9. Survey of Encryption Methods ................................................................................................. 41 9.1. Electrical-to-Optical Translation of Current Encryptor Designs....................................... 41 9.1.1. Conventional Block Ciphers....................................................................................... 41 9.1.2. Conventional Stream Ciphers ..................................................................................... 42 9.2. Purely Optical Implementations ........................................................................................ 42 9.2.1. Chaotic Mode-Locked Lasers for Communications Encryption ................................ 42 9.2.2. Quantum Cryptography with Coherent State Noise ................................................... 42 9.2.3. Single Photon Quantum Cryptography....................................................................... 42 9.3. Hybrid Electrical/Optical Implementation........................................................................
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