Numerical Computation Guide
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Decimal Layouts for IEEE 754 Strawman3
IEEE 754-2008 ECMA TC39/TG1 – 25 September 2008 Mike Cowlishaw IBM Fellow Overview • Summary of the new standard • Binary and decimal specifics • Support in hardware, standards, etc. • Questions? 2 Copyright © IBM Corporation 2008. All rights reserved. IEEE 754 revision • Started in December 2000 – 7.7 years – 5.8 years in committee (92 participants + e-mail) – 1.9 years in ballot (101 voters, 8 ballots, 1200+ comments) • Removes many ambiguities from 754-1985 • Incorporates IEEE 854 (radix-independent) • Recommends or requires more operations (functions) and more language support 3 Formats • Separates sets of floating-point numbers (and the arithmetic on them) from their encodings (‘interchange formats’) • Includes the 754-1985 basic formats: – binary32, 24 bits (‘single’) – binary64, 53 bits (‘double’) • Adds three new basic formats: – binary128, 113 bits (‘quad’) – decimal64, 16-digit (‘double’) – decimal128, 34-digit (‘quad’) 4 Why decimal? A web page… • Parking at Manchester airport… • £4.20 per day … … for 10 days … … calculated on-page using ECMAScript Answer shown: 5 Why decimal? A web page… • Parking at Manchester airport… • £4.20 per day … … for 10 days … … calculated on-page using ECMAScript Answer shown: £41.99 (Programmer must have truncated to two places.) 6 Where it costs real money… • Add 5% sales tax to a $ 0.70 telephone call, rounded to the nearest cent • 1.05 x 0.70 using binary double is exactly 0.734999999999999986677323704 49812151491641998291015625 (should have been 0.735) • rounds to $ 0.73, instead of $ 0.74 -
Nios II Custom Instruction User Guide
Nios II Custom Instruction User Guide Subscribe UG-20286 | 2020.04.27 Send Feedback Latest document on the web: PDF | HTML Contents Contents 1. Nios II Custom Instruction Overview..............................................................................4 1.1. Custom Instruction Implementation......................................................................... 4 1.1.1. Custom Instruction Hardware Implementation............................................... 5 1.1.2. Custom Instruction Software Implementation................................................ 6 2. Custom Instruction Hardware Interface......................................................................... 7 2.1. Custom Instruction Types....................................................................................... 7 2.1.1. Combinational Custom Instructions.............................................................. 8 2.1.2. Multicycle Custom Instructions...................................................................10 2.1.3. Extended Custom Instructions................................................................... 11 2.1.4. Internal Register File Custom Instructions................................................... 13 2.1.5. External Interface Custom Instructions....................................................... 15 3. Custom Instruction Software Interface.........................................................................16 3.1. Custom Instruction Software Examples................................................................... 16 -
The MPFR Team [email protected] This Manual Documents How to Install and Use the Multiple Precision Floating-Point Reliable Library, Version 2.2.0
MPFR The Multiple Precision Floating-Point Reliable Library Edition 2.2.0 September 2005 The MPFR team [email protected] This manual documents how to install and use the Multiple Precision Floating-Point Reliable Library, version 2.2.0. Copyright 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc. Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.1 or any later version published by the Free Software Foundation; with no Invariant Sections, with the Front-Cover Texts being “A GNU Manual”, and with the Back-Cover Texts being “You have freedom to copy and modify this GNU Manual, like GNU software”. A copy of the license is included in Appendix A [GNU Free Documentation License], page 30. i Table of Contents MPFR Copying Conditions ................................ 1 1 Introduction to MPFR ................................. 2 1.1 How to use this Manual ........................................................ 2 2 Installing MPFR ....................................... 3 2.1 How to install ................................................................. 3 2.2 Other make targets ............................................................ 3 2.3 Known Build Problems ........................................................ 3 2.4 Getting the Latest Version of MPFR ............................................ 4 3 Reporting Bugs ........................................ 5 4 MPFR Basics ......................................... -
IEEE Std 754-1985 Revision of Reaffirmed1990 IEEE Standard for Binary Floating-Point Arithmetic
Recognized as an American National Standard (ANSI) IEEE Std 754-1985 An American National Standard IEEE Standard for Binary Floating-Point Arithmetic Sponsor Standards Committee of the IEEE Computer Society Approved March 21, 1985 Reaffirmed December 6, 1990 IEEE Standards Board Approved July 26, 1985 Reaffirmed May 21, 1991 American National Standards Institute © Copyright 1985 by The Institute of Electrical and Electronics Engineers, Inc 345 East 47th Street, New York, NY 10017, USA No part of this publication may be reproduced in any form, in an electronic retrieval system or otherwise, without the prior written permission of the publisher. IEEE Standards documents are developed within the Technical Committees of the IEEE Societies and the Standards Coordinating Committees of the IEEE Standards Board. Members of the committees serve voluntarily and without compensation. They are not necessarily members of the Institute. The standards developed within IEEE represent a consensus of the broad expertise on the subject within the Institute as well as those activities outside of IEEE which have expressed an interest in participating in the development of the standard. Use of an IEEE Standard is wholly voluntary. The existence of an IEEE Standard does not imply that there are no other ways to produce, test, measure, purchase, market, or provide other goods and services related to the scope of the IEEE Standard. Furthermore, the viewpoint expressed at the time a standard is approved and issued is subject to change brought about through developments in the state of the art and comments received from users of the standard. Every IEEE Standard is subjected to review at least once every five years for revision or reaffirmation. -
Floating Point Representation (Unsigned) Fixed-Point Representation
Floating point representation (Unsigned) Fixed-point representation The numbers are stored with a fixed number of bits for the integer part and a fixed number of bits for the fractional part. Suppose we have 8 bits to store a real number, where 5 bits store the integer part and 3 bits store the fractional part: 1 0 1 1 1.0 1 1 $ 2& 2% 2$ 2# 2" 2'# 2'$ 2'% Smallest number: Largest number: (Unsigned) Fixed-point representation Suppose we have 64 bits to store a real number, where 32 bits store the integer part and 32 bits store the fractional part: "# "% + /+ !"# … !%!#!&. (#(%(" … ("% % = * !+ 2 + * (+ 2 +,& +,# "# "& & /# % /"% = !"#× 2 +!"&× 2 + ⋯ + !&× 2 +(#× 2 +(%× 2 + ⋯ + ("%× 2 0 ∞ (Unsigned) Fixed-point representation Range: difference between the largest and smallest numbers possible. More bits for the integer part ⟶ increase range Precision: smallest possible difference between any two numbers More bits for the fractional part ⟶ increase precision "#"$"%. '$'#'( # OR "$"%. '$'#'(') # Wherever we put the binary point, there is a trade-off between the amount of range and precision. It can be hard to decide how much you need of each! Scientific Notation In scientific notation, a number can be expressed in the form ! = ± $ × 10( where $ is a coefficient in the range 1 ≤ $ < 10 and + is the exponent. 1165.7 = 0.0004728 = Floating-point numbers A floating-point number can represent numbers of different order of magnitude (very large and very small) with the same number of fixed bits. In general, in the binary system, a floating number can be expressed as ! = ± $ × 2' $ is the significand, normally a fractional value in the range [1.0,2.0) . -
IEEE Standard 754 for Binary Floating-Point Arithmetic
Work in Progress: Lecture Notes on the Status of IEEE 754 October 1, 1997 3:36 am Lecture Notes on the Status of IEEE Standard 754 for Binary Floating-Point Arithmetic Prof. W. Kahan Elect. Eng. & Computer Science University of California Berkeley CA 94720-1776 Introduction: Twenty years ago anarchy threatened floating-point arithmetic. Over a dozen commercially significant arithmetics boasted diverse wordsizes, precisions, rounding procedures and over/underflow behaviors, and more were in the works. “Portable” software intended to reconcile that numerical diversity had become unbearably costly to develop. Thirteen years ago, when IEEE 754 became official, major microprocessor manufacturers had already adopted it despite the challenge it posed to implementors. With unprecedented altruism, hardware designers had risen to its challenge in the belief that they would ease and encourage a vast burgeoning of numerical software. They did succeed to a considerable extent. Anyway, rounding anomalies that preoccupied all of us in the 1970s afflict only CRAY X-MPs — J90s now. Now atrophy threatens features of IEEE 754 caught in a vicious circle: Those features lack support in programming languages and compilers, so those features are mishandled and/or practically unusable, so those features are little known and less in demand, and so those features lack support in programming languages and compilers. To help break that circle, those features are discussed in these notes under the following headings: Representable Numbers, Normal and Subnormal, Infinite -
On Various Ways to Split a Floating-Point Number
On various ways to split a floating-point number Claude-Pierre Jeannerod Jean-Michel Muller Paul Zimmermann Inria, CNRS, ENS Lyon, Universit´ede Lyon, Universit´ede Lorraine France ARITH-25 June 2018 -1- Splitting a floating-point number X = ? round(x) frac(x) 0 2 First bit of x = ufp(x) (for scalings) X All products are s computed exactly 2 2 X with one FP p 2 2 k a b multiplication a + b ! 2 k + k X (Dekker product) 2 2 X Dekker product (1971) -2- Splitting a floating-point number absolute splittings (e.g., bxc), vs relative splittings (e.g., most significant bits, splitting of the significands for multiplication); In each "bin", the sum is no bit manipulations of the computed exactly binary representations (would result in less portable Matlab program in a paper by programs) ! onlyFP Zielke and Drygalla (2003), operations. analysed and improved by Rump, Ogita, and Oishi (2008), reproducible summation, by Demmel & Nguyen. -3- Notation and preliminary definitions IEEE-754 compliant FP arithmetic with radix β, precision p, and extremal exponents emin and emax; F = set of FP numbers. x 2 F can be written M x = · βe ; βp−1 p M, e 2 Z, with jMj < β and emin 6 e 6 emax, and jMj maximum under these constraints; significand of x: M · β−p+1; RN = rounding to nearest with some given tie-breaking rule (assumed to be either \to even" or \to away", as in IEEE 754-2008); -4- Notation and preliminary definitions Definition 1 (classical ulp) The unit in the last place of t 2 R is ( βblogβ jt|c−p+1 if jtj βemin , ulp(t) = > βemin−p+1 otherwise. -
IEEE 754 Format (From Last Time)
IEEE 754 Format (from last time) ● Single precision format S Exponent Significand 1 8 23 The exponent is represented in bias 127 notation. Why? ● Example: 52.25 = 00110100.010000002 5 Normalize: 001.10100010000002 x 2 (127+5) 0 10000100 10100010000000000000000 0100 0010 0101 0001 0000 0000 0000 0000 52.25 = 0x42510000 08/29/2017 Comp 411 - Fall 2018 1 IEEE 754 Limits and Features ● SIngle precision limitations ○ A little more than 7 decimal digits of precision ○ Minimum positive normalized value: ~1.18 x 10-38 ○ Maximum positive normalized value: ~3.4 x 1038 ● Inaccuracies become evident after multiple single precision operations ● Double precision format 08/29/2017 Comp 411 - Fall 2018 2 IEEE 754 Special Numbers ● Zero - ±0 A floating point number is considered zero when its exponent and significand are both zero. This is an exception to our “hidden 1” normalization trick. There are also a positive and negative zeros. S 000 0000 0 000 0000 0000 0000 0000 0000 ● Infinity - ±∞ A floating point number with a maximum exponent (all ones) is considered infinity which can also be positive or negative. S 111 1111 1 000 0000 0000 0000 0000 0000 ● Not a Number - NaN for ±0/±0, ±∞/±∞, log(-42), etc. S 111 1111 1 non-zero 08/29/2017 Comp 411 - Fall 2018 3 A Quick Wake-up exercise What decimal value is represented by 0x3f800000, when interpreted as an IEEE 754 single precision floating point number? 08/29/2017 Comp 411 - Fall 2018 4 Bits You can See The smallest element of a visual display is called a “pixel”. -
Automatic Hardware Generation for Reconfigurable Architectures
Razvan˘ Nane Automatic Hardware Generation for Reconfigurable Architectures Automatic Hardware Generation for Reconfigurable Architectures PROEFSCHRIFT ter verkrijging van de graad van doctor aan de Technische Universiteit Delft, op gezag van de Rector Magnificus prof. ir. K.C.A.M Luyben, voorzitter van het College voor Promoties, in het openbaar te verdedigen op donderdag 17 april 2014 om 10:00 uur door Razvan˘ NANE Master of Science in Computer Engineering Delft University of Technology geboren te Boekarest, Roemenie¨ Dit proefschrift is goedgekeurd door de promotor: Prof. dr. K.L.M. Bertels Samenstelling promotiecommissie: Rector Magnificus voorzitter Prof. dr. K.L.M. Bertels Technische Universiteit Delft, promotor Prof. dr. E. Visser Technische Universiteit Delft Prof. dr. W.A. Najjar University of California Riverside Prof. dr.-ing. M. Hubner¨ Ruhr-Universitat¨ Bochum Dr. H.P. Hofstee IBM Austin Research Laboratory Dr. ir. A.C.J. Kienhuis Universiteit van Leiden Dr. ir. J.S.S.M Wong Technische Universiteit Delft Prof. dr. ir. Geert Leus Technische Universiteit Delft, reservelid Automatic Hardware Generation for Reconfigurable Architectures Dissertation at Delft University of Technology Copyright c 2014 by R. Nane All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any form or by any means, electronic, mechanical, photocopying, recording, or otherwise, without permission of the author. ISBN 978-94-6186-271-6 Printed by CPI Koninklijke Wohrmann,¨ Zutphen, The Netherlands To my family Automatic Hardware Generation for Reconfigurable Architectures Razvan˘ Nane Abstract ECONFIGURABLE Architectures (RA) have been gaining popularity rapidly in the last decade for two reasons. -
Floating Point Arithmetic
Systems Architecture Lecture 14: Floating Point Arithmetic Jeremy R. Johnson Anatole D. Ruslanov William M. Mongan Some or all figures from Computer Organization and Design: The Hardware/Software Approach, Third Edition, by David Patterson and John Hennessy, are copyrighted material (COPYRIGHT 2004 MORGAN KAUFMANN PUBLISHERS, INC. ALL RIGHTS RESERVED). Lec 14 Systems Architecture 1 Introduction • Objective: To provide hardware support for floating point arithmetic. To understand how to represent floating point numbers in the computer and how to perform arithmetic with them. Also to learn how to use floating point arithmetic in MIPS. • Approximate arithmetic – Finite Range – Limited Precision • Topics – IEEE format for single and double precision floating point numbers – Floating point addition and multiplication – Support for floating point computation in MIPS Lec 14 Systems Architecture 2 Distribution of Floating Point Numbers e = -1 e = 0 e = 1 • 3 bit mantissa 1.00 X 2^(-1) = 1/2 1.00 X 2^0 = 1 1.00 X 2^1 = 2 1.01 X 2^(-1) = 5/8 1.01 X 2^0 = 5/4 1.01 X 2^1 = 5/2 • exponent {-1,0,1} 1.10 X 2^(-1) = 3/4 1.10 X 2^0 = 3/2 1.10 X 2^1= 3 1.11 X 2^(-1) = 7/8 1.11 X 2^0 = 7/4 1.11 X 2^1 = 7/2 0 1 2 3 Lec 14 Systems Architecture 3 Floating Point • An IEEE floating point representation consists of – A Sign Bit (no surprise) – An Exponent (“times 2 to the what?”) – Mantissa (“Significand”), which is assumed to be 1.xxxxx (thus, one bit of the mantissa is implied as 1) – This is called a normalized representation • So a mantissa = 0 really is interpreted to be 1.0, and a mantissa of all 1111 is interpreted to be 1.1111 • Special cases are used to represent denormalized mantissas (true mantissa = 0), NaN, etc., as will be discussed. -
FORTRAN 77 Language Reference
FORTRAN 77 Language Reference FORTRAN 77 Version 5.0 901 San Antonio Road Palo Alto, , CA 94303-4900 USA 650 960-1300 fax 650 969-9131 Part No: 805-4939 Revision A, February 1999 Copyright Copyright 1999 Sun Microsystems, Inc. 901 San Antonio Road, Palo Alto, California 94303-4900 U.S.A. All rights reserved. All rights reserved. This product or document is protected by copyright and distributed under licenses restricting its use, copying, distribution, and decompilation. No part of this product or document may be reproduced in any form by any means without prior written authorization of Sun and its licensors, if any. Portions of this product may be derived from the UNIX® system, licensed from Novell, Inc., and from the Berkeley 4.3 BSD system, licensed from the University of California. UNIX is a registered trademark in the United States and in other countries and is exclusively licensed by X/Open Company Ltd. Third-party software, including font technology in this product, is protected by copyright and licensed from Sun’s suppliers. RESTRICTED RIGHTS: Use, duplication, or disclosure by the U.S. Government is subject to restrictions of FAR 52.227-14(g)(2)(6/87) and FAR 52.227-19(6/87), or DFAR 252.227-7015(b)(6/95) and DFAR 227.7202-3(a). Sun, Sun Microsystems, the Sun logo, SunDocs, SunExpress, Solaris, Sun Performance Library, Sun Performance WorkShop, Sun Visual WorkShop, Sun WorkShop, and Sun WorkShop Professional are trademarks or registered trademarks of Sun Microsystems, Inc. in the United States and in other countries. -
Floating Point Square Root Under HUB Format
View metadata, citation and similar papers at core.ac.uk brought to you by CORE provided by Repositorio Institucional Universidad de Málaga Floating Point Square Root under HUB Format Julio Villalba-Moreno Javier Hormigo Dept. of Computer Architecture Dept. of Computer Architecture University of Malaga University of Malaga Malaga, SPAIN Malaga, SPAIN [email protected] [email protected] Abstract—Unit-Biased (HUB) is an emerging format based on maintaining the same accuracy, the area cost and delay of FIR shifting the representation line of the binary numbers by half filter implementations has been drastically reduced in [3], and unit in the last place. The HUB format is specially relevant similarly for the QR decomposition in [4]. for computers where rounding to nearest is required because it is performed simply by truncation. From a hardware point In [5] the authors carry out an analysis of using HUB format of view, the circuits implementing this representation save both for floating point adders, multipliers and converters from a area and time since rounding does not involve any carry propa- quantitative point of view. Experimental studies demonstrate gation. Designs to perform the four basic operations have been that HUB format keeps the same accuracy as conventional proposed under HUB format recently. Nevertheless, the square format for the aforementioned units, simultaneously improving root operation has not been confronted yet. In this paper we present an architecture to carry out the square root operation area, speed and power consumption (14% speed-up, 38% less under HUB format for floating point numbers. The results of area and 26% less power for single precision floating point this work keep supporting the fact that the HUB representation adder, 17% speed-up, 22% less area and slightly less power for involves simpler hardware than its conventional counterpart for the floating point multiplier).