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Delta-Sigma Digital-RF Modulation for High Data Rate Transmitters Albert Delta-Sigma Digital-RF Modulation for High Data Rate Transmitters by Albert Jerng B.S. Electrical Engineering Stanford University, 1994 M.S. Electrical Engineering Stanford University, 1996 Submitted to the Department of Electrical Engineering and Computer Science in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Electrical Engineering and Computer Science at the MASSACHUSETTS INSTITUTE OF TECHNOLOGY Sept Z006 Sept ý006 @ Massachusetts Institute of Technology 2006. All rights reserved. Author partment of lectrical Engineering and Computer Science Department of Q letrical Engineering and Comput'er" S' ience September 21, 2006 C ertified by .... ... .............................. Charles G. Sodini -I Professor Th2iess Supervisor Accepted by............ .-......... ............... Arthur C. Smith MASSACHUSErr S INSTITUTE Uhairman, Department Committee on Graduate Students OF TECHN OLOGY APR 3 0 2007 ARCHIVES LIBRARIES Delta-Sigma Digital-RF Modulation for High Data Rate Transmitters by Albert Jerng Submitted to the Department of Electrical Engineering and Computer Science on September 21, 2006, in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Electrical Engineering and Computer Science Abstract A low power, wideband wireless transmitter utilizing AE direct digital modulation of an RF carrier is presented. The transmitter architecture replaces high dynamic range analog circuits with high speed digital circuits and a passive LC bandpass filter, saving power and area compared to conventional IQ modulators for wideband systems. A prototype transmitter IC built in 0.13 pm CMOS demonstrates a data rate of 1.2 Gb/s using OFDM modulation in a bandwidth of 200 MHz centered at 5.25 GHz. The modulator consumes 187 mW and occupies a die area of 0.72 mm2 . A quadrature digital-IF approach eliminates modulator LO feedthrough and image spurs from the output spectrum without requiring analog circuitry or system calibration, simplifying the design of the transmitter. The largest modulator spur is measured to be -47 dBc. Measured SNDR over a 200 MHz bandwidth is 43 dB. Successful implementation of the AE RF modulator requires the design of a high- Q, tunable RF bandpass filter, and a low power, high speed digital AE modulator. A 4th order passive LC bandpass filter with center frequency of 5.25 GHz is designed and implemented using differential coupled resonators. Variation of the filter response over process and temperature is removed through the design of an automatic self-tuning loop that calibrates the filter center frequency to the system LO. A 2.625 GS/s, 2nd order, 3-bit digital AE modulator is realized through the use of a pass-gate adder circuit optimized for low power and high speed. The digital modulator is software programmable to support multiple bandwidths, frequency channels, and modulation schemes. It can be used adaptively to transmit in selected channels with variable bit-rates, depending on channel conditions. It is envisioned that the AE digital-RF modulator can be used as a universal transmitter for wideband systems and applications that require high data rates and low power consumption. Thesis Supervisor: Charles G. Sodini Title: Professor Acknowledgments The completion of my PhD program has been a very rewarding process and experi- ence. In particular, I have been enriched by the interactions with faculty, and fellow students both inside and outside the classroom and lab. I'd like to thank my advisor Prof. Charles Sodini - his guidance and judgement throughout my thesis project has been greatly appreciated. Thanks for pushing me with thought-provoking questions, which helped me realize the full potential of this project. I'd like to thank my com- mittee member Prof. Anantha Chandrakasan for providing me with knowledge on digital design issues and giving me a kickstart on the high speed adder design. I'd like to thank my committee member Prof. Mike Perrott for providing helpful suggestions on the phase detector design in my tuning loop, providing advice throughout my pro- gram, and sharing lab equipment with our group. I'd also like to thank Prof. Vladimir Stoyanovic for helpful discussions regarding high speed digital interfaces. During my summer at ADI, I got some great feedback regarding my project. In particular, I'd like to thank Bill Schofield and Richard Schreier for their helpful discussions and comnments. I have enjoyed the comaraderie and help of many labmates over the years. Andy Wang was a great source of knowledge on system issues. Todd Sepke has helped me a lot through technical discussions, and by proofreading papers for me. Anh Pham provided great advice on RF board design and was a magician soldering ICs for me. Lunal Khuon provided lots of helpful lab parts and was a great conference roommate and fellow senior citizen/dad. Andrew Chen was a great die photographer and helped me out on digital testability issues. Ken Tan, Nir Matalon, Farinaz Edalat, and Khoa Nguyen helped me understand the WiGLAN system and use the boards to test EVM on my transmitter. Mark Spaeth provided lots of help with PCB design questions and lab troubles. It has been fun socializing with the all the above and other members of the lab John Fiorenza, Matt Guyton, Albert Chow, Johnna Powell, and Kevin Ryu. I'd also like to thank Rhonda Maynard for all her help with taking care of purchase orders, and quotes, and reimbursements, and just making life easier for me. I'd like to thank my family and friends for always being there for me. To my parents, thank you for all your support over the years, and for providing the framework that makes this all possible. To my wife, Veronica, thank you for embracing the change of lifestyle and weather so whole-heartedly, and for being such a good mother and partner. And to my little one, Elliot, thank you for brightening each day with your smile. Contents 1 Introduction 1.1 WiGLAN Transmitter .......................... 1.2 Conventional IQ Transmitter . ...................... 1.2.1 IQ Modulator Impairments . ................... 1.3 AZ Digital-RF Modulation ....................... 1.3.1 Process Scaling . ......................... 1.3.2 Circuit Integration . ....................... 2 Digital-RF Conversion 2.1 Previous Research ............................. 2.2 RF Bandpass Reconstruction Filter . .................. 2.3 Filtering Requirements . ......................... 3 LC Bandpass Filter Design 3.1 Challenges . ............... 3.2 Differential Coupled Resonator Topology 3.2.1 Area Considerations ....... 3.2.2 Impedance Considerations . 3.2.3 Inductor Design .......... 3.2.4 Varactor Design .......... 3.2.5 5.25 GHz Filter Design ...... 3.3 Automatic Tuning Loop ......... 3.3.1 Non-Idealities ........... 7 3.3.2 Digital Tuning Loop..... 3.4 Q-enhancement . ........... 3.5 Test Filter Measurements ...... 3.6 Summary ............... 4 AE System Architecture 4.1 Choosing Clock Frequency ...... 4.2 Co-Design of AE NTF and RF BPF 4.3 Comparison to Oversampling with No Noise-Shaping 4.4 UWB System Example ........ 4.5 Summary ............... 5 Quadrature Digital-IF AE Modulator 5.1 Digital-IF ................. 5.2 Quadrature Digital-IF .......... 5.2.1 Bandpass AE ........... 5.3 Frequency Planning ............ 5.4 Summary ................. 6 Digital Circuit Design 93 6.1 Low Power Design Challenges ...... 93 6.1.1 General Techniques ........ 94 6.2 AE Modulator Topology . ........ 96 6.3 Low Power, High Speed Adder Design . 99 6.3.1 Conventional Static Mirror Adder 99 6.3.2 Passgate Adder . ......... 102 6.4 Top Level Implementation and Results . 107 6.4.1 Interpolation Filter . ....... 108 6.4.2 Digital-IF Up-Converter ..... 110 6.4.3 Simulation . ............ 110 6.5 Summary . .... ............ 112 7 DRFC Circuit Design 113 7.1 Unit Cell Mismatches ........................... 114 7.1.1 DAC Mismatches .......... ................ 115 7.1.2 AE DRFC Mismatches ............ ........... 118 7.2 Behavioral Simulations .......................... 120 7.2.1 LO Phase Mismatch ............ ..... ...... 124 7.3 Circuit Implications ................... ........ 124 7.4 DRFC Unit Cell Implementation ................... 126 7.5 Simulation Results .............. ........... 130 7.6 Summary .............. ................... 134 8 Measurement Results 135 8.1 Fabricated Test Chips ....... ........... ....... 135 8.2 Test Setup ................. .............. 138 8.3 Test Chip Results ................... .......... 139 8.4 Power/Area Comparison ................ ........ 150 9 Conclusion 153 9.1 Future Directions ........... .. ............ 154 9.1.1 Mismatch Shaping ................... ..... 154 List of Figures 1-1 Conventional IQ Modulator ................... .... 22 1-2 IQ Modulator Output Spectrum ................... .. 25 1-3 Digital QPSK Modulator ................... ...... 26 1-4 Digital AE RF Modulator ................... ..... 27 2-1 RF DAC Unit Cell ....... .. .......... 30 2-2 DRFC Unit Cell ....... .............. 31 2-3 Up-Converted Clock Images ................... .... 32 2-4 Up-Converted Quantization Noise ................... 32 2-5 Quadrature Digital-RF Converter Core . ................ 33 3-1 Filter Topology ........... ..... ............. 38 3-2 Differential Resonator with Non-linear C(V) . ........... 43 3-3 LC BPF Schematic ................... ....... 45 3-4 Differential Inductor Lumped Element Model . ............ 45 3-5 Differential Tank Capacitance C(V) . .................. 46 3-6 Coupled Resonator Model ................... ....
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