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Modeling Deep Reactive Ion Etching Learning Module Modeling Deep Reactive Ion Etching Learning Module Contents Interactive Primary Reading Overview Presentation Concept Check Simulation Activity Video Activity This Learning Module introduces Deep Reactive Ion Etching (DRIE) used in the fabrication of microsystems, an overview of how DRIE can be computationally modeled, and a brief conclusion of the Design for Nanomanufacturing at UC Berkeley’s research on modeling a DRIE process. Activities in this module allow you to demonstrate and apply your understanding of the basic concepts of these processes. Target audience: High School for educational purposes only Made possible through grants from the National Science Foundation and the Design for Nanomanufacturing at UC Berkeley? Disclaimer The information contained herein is considered to be true and accurate; however the Design for Nanomanufacturing at UC Berkeley makes no guarantees concerning the authenticity of any statement. The Design for Nanomanufacturing at UC Berkeley accepts no liability for the content of this unit, or for the consequences of any actions taken on the basis of the information provided. Modeling Deep Reactive Ion Etching Interactive Primary Reading Participant’s Guide Description This activity (1) describes the DRIE process used in nanomanufacturing, and how it is traditionally implemented in industry, (2) introduces the computational modeling process career researchers use to mathematically model experimental data, (3) discusses the results of the Design for Nanomanufactuing at UC Berkeley research on modeling DRIE, and (4) provides opportunities for you to demonstrate and apply your understanding of the material covered by the text Introduction Originally developed for Microelectromechanical systems (MEMS), Deep Reactive Ion Etching (DRIE) is a nanomanufacturing process used to produce nanoscopic devices and components such as integrated circuits (ICs) known as microchips. DRIE is used to manufacture ICs by “carving” microscopic, steep-sided features such as trenches, holes, and posts into Silicon wafers that make up the transistors in the IC. As of 2017, approximately 25 million transistors can be fabricated on a single 20mm2 microchip. Depending on the IC being fabricated, the size of these features may range from 0.5 microns to approximately 1,000 microns with aspect-ratios of approximately 30:1 while some nanomanufacturing companies claim to achieve aspect ratios of 50:1. Although there are two DRIE technologies to carve out these near-perfect 90 degree, high aspect-ratio features, the Bosch process is the industry recognized production technique and will be the context of DRIE discussed in this module. The Bosch process patented by the German engineering and electronics company Robert Bosch GmbH, is a top-down, dry-etch process. Bosch Process Figur Figur Top-down etching processes require a larger sample of Silicon than the finished product. While this does waste materials, top-down manufacturing provides more control during the fabrication process and often favored over bottom-up processes. The most common used top-down technique implemented today is nanolithography. In this context, nanolithography requires the sample to be layered with a mask that protects some parts of Unetched the sample and exposes other parts to be Unetched carved sample away during the dry-etch process. Figure 1 sample depicts a sample layered with such a mask then etched creating holes and trenches. Posts are etched in a similar fashion as shown in Figure 2. Dry-etching is a method that exposes Sample etched the sample to plasma. When the plasma is Sample etched excited by a **electromagnetic field, the plasma bombards the sample with high energy ions. These ions travel nearly 90 degrees to the surface of the sample, resulting in a steep-sided etch. The patented Bosch process increases the certainty of a near-perfect 90 degree sidewall by processing the sample in an etch cycle and “protection” cycle, known as a deposit cycle or permissive cycle, that alternate repeatedly. During the deposit cycle, the sample is exposed to a gas the coats feature protecting its sidewalls from being etched during the next etch cycle. Each cycle of the Bosch process can last anywhere between a tenth of a second to several seconds. Discussion I Working in your group answer the following questions. When you are finished discussing, summarize your answers on a presentation-whiteboard and be prepared to discuss your findings, opinions, and insights. A. The fabrication of ICs is not the only application of a DRIE process. Identify another product that is produced through a DRIE process and describe how it is used. Discuss the significance of each of this device being so small. B. DRIE fabrication is a multidisciplinary field. Research a nanomanufacturing company and identify: the number of people its employs, its location, qualifications to work as a technician there. Your teacher may show an IC fabrication video before moving on- you can find the video at https://www.youtube.com/watch?v=35jWSQXku74 Modeling Overview Traditionally, the nanofabrication of microchips is a guess-and-check process. Engineers do not know what the optimal pattern layout of features on the wafer should be in order to have each chip etched properly with minimal defects. For example, the etched features do not come out the desired shape or are not etched to the desired depth during fabrication- the product is otherwise defective to some capacity. Several wafers are wasted in the process of simply determining the placement of features. To make matters worse- a layout that is effective for one system (the machines and tools performing the etch process) will likely not be the same for another system, as each system is unique and operates slightly different. This results in low production yields, and high variation in chip quality crippling the commercial capacity of nanomanufacturing. Modeling DRIE can overcome these challenges by determining the optimal feature layout with information extracted from the production of only a few wafers. Etch-rate of features vary on three etching effects: (1) self-loading: larger features etch more slowly over time, (2) microloading: closely grouped features etch more slowly, and (3) macroloading: the overall etch rate is inversely proportional to the amount of the wafer being etched. Each effect is subject to further variation from parameters such as the number of features, the density of features, the exposure time, position of each feature, arrangement of features, and feature size. PhD candidate Brian Salazar, under the supervision of Professor Hayden Taylor, at UC Berkeley’s Design for Nanomanufacturing lab is working to refine the models of each effect and unify them into a single model that addresses all three effects to determine the optimal feature placement. While the actual process of computational modeling varies widely from problem to problem and may involve cycling through various steps several times, a general method for computational modeling is explained below: Computational modeling method 1. Extracting information from the experimental data a. Sometimes the information you need requires manipulating the data through calculation or passing it through some function b. Divide the data into two sets: (1) training set - this set is used for fitting the model, and (2) validation set - this set is used for checking if the model works 2. Visualizing the information a. This may include plotting the data or drawing up figures 3. A mathematical model for each effect is derived from physical law and chemistry. 4. The mathematical model is translated into a script that could manipulated with statistical software (such as MATLAB) creating a preliminary computational model 5. A simulation of the computational model is run for the training set a. Think of this as plugging in your independent variable into your equation and recording all of your dependent variable results 6. A quantitative comparison is made between the simulation results and the experimental data --check how well the model came to predicting the training set a. If the two do not match well enough, you ask yourself (granted there are no bugs in your code!): i. What parameters can I refine to improve the fit? ⇒ return to “step 5” ● These parameters could be slopes, scaling factors, etc… ● Is there a better way to compute said parameters? ● Is there a better mathematical model to base this fit on? ⇒ return to “step 4” b. If the two match well enough (minimal error), run the simulation for the validation set and check how well the model came to predicting the validation set i. If the two do not match well enough, you ask yourself (granted there are no bugs in your code!): ● What parameters can I refine to improve the fit? ⇒ return to “step 5” a. These parameters could be slopes, scaling factors, etc… ● Is there a better way to compute said parameters? ● Is there a better mathematical model to base this fit on? ⇒ return to “step 4” ii. If the two match well enough, congratulations! Share your findings. Modeling DRIE Conclusion Following such a process, Mr. Salazar’s investigation of the effects due to self-loading led to the development and refinement of a “feature-scale”, “wafer-scale”, and “wafer/die-scale” models. Respectively, the models take in the effects of self-loading & ARDE, macroloading, and microloading. Convolving the 3 models using advanced mathematics, a single unified comprehensive model is proposed for determining the optimal feature layout with information extracted from the production of only a few wafers. An interactive simulation of the feature/wafer-scale model in is hosted on NanoHUB.org. Discussion II Working in your group answer the following questions. When you are finished discussing, summarize your answers on a presentation-whiteboard and be prepared to discuss your findings, opinions, and insights. C. Choose one of the effects that vary the etching rate of features mentioned above. What are some parameters that may impact the etch rate of your chosen effect.
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