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Instruction Set Architecture RISC-V: An Overview of the Instruction Set Architecture Harry H. Porter III Portland State University [email protected] January 26, 2018 The RISC-V project deines and describes a standardized Instruction Set Architecture (ISA). RISC-V is an open-source speci2ication for computer processor architectures, not a particular chip or implementation. To date, several different groups have designed and fabricated silicon implementations of the RISC-V speci2ications. Based on the performance of these implementations and the growing need for interoperability among vendors, it appears that the RISC-V standard will increase in importance. This document introduces and explains the RISC-V standard, giving an informal overview of the architecture of a RISC-V processor. This document does not discuss a particular implementation; instead we discuss some of the various design options that are included in the formal RISC-V speci2ication. This document gives the reader an initial introduction to the RISC-V design. Date Last Modi=ied: January 26, 2018 Available Online: www.cs.pdx.edu/~harry/riscv Table of Contents List of Instructions 6 Chapter 1: Introduction 11 Introduction 11 The RISC-V Naming Conventions 13 The Usual Disclaimer / Request For Corrections 15 Document Revision History / Permission to Copy 16 Basic Terminology 17 Chapter 2: Basic Organization 20 Main Memory 20 Little Endian 20 The Registers 23 Control and Status Registers (CSRs) 25 Alignment 26 Chapter 3: Instructions 28 Instructions 28 The Compressed Instruction Extension 28 Instruction Encoding 31 User-Level Instructions 36 Arithmetic Instructions (ADD, SUB, …) 38 Logical Instructions (AND, OR, XOR, …) 49 Shifting Instructions (SLL, SRL, SRA, …) 52 Miscellaneous Instructions 57 Branch and Jump Instructions 65 Load and Store Instructions 78 Integer Multiply and Divide 89 Chapter 4: Floating Point Instructions 103 Floating Pointing – Review of Basic Concepts 103 The Floating Point Extensions 119 Floating Point Load and Store Instructions 124 Basic Floating Point Arithmetic Instructions 127 Floating Point Conversion Instructions 133 RISC-V Architecture Summary / Porter Page S2 of S323 Table of Contents Floating Point Move Instructions 137 Floating Point Compare and Classify Instructions 142 Chapter 5: Register and Calling Conventions 146 Standard Usage of General Purpose Registers 146 Saving Registers Across Calls 148 Register x0 - The Zero Register (“zero”) 150 Register x1 - The Return Address (“ra”) 150 Register x2 - The Stack Pointer (“sp”) 151 Register x3 - The Global Pointer (“gp”) 152 Register x4 - The Thread Base Pointer (“tp”) 152 Register x5-x7,x28-x31 - Temp Registers (“t0-t6”) 153 Register x8,x9,x18-x27 - Saved Registers (“s0-s11”) 154 Register x8 - Frame Pointer (“fp”) 154 Register x10-x17 - Argument Registers (“a0-a7”) 155 Calling Conventions for Arguments 156 Floating Point Registers 158 Chapter 6: Compressed Instructions 160 Compressed Instructions 160 Instruction Formats 161 Load Instructions 162 Store Instructions 168 Jump, Call, and Conditional Branch Instructions 175 Load Constant into a Register 178 Arithmetic, Shift, and Logic Instructions 180 Miscellaneous Instructions 189 Instruction Encoding 191 Chapter 7: Concurrency and Atomic Instructions 195 Hardware Threads (HARTs) 195 The RISC-V Memory Model 196 Concurrency Control - Review and Background 198 A Review of Caching Concepts 200 RISC-V Concurrency Control 205 The FENCE Instructions 205 Load-Reserved / Store-Conditional Semantics 210 RISC-V Architecture Summary / Porter Page S3 of S323 Table of Contents Atomic Memory Control Bits: “aq” and “rl” 213 Using LR and SC Instructions 217 Deadlock and Starvation – Background 219 Starvation and LR/SC Sequences 220 The Atomic Memory Operation (AMO) Instructions 221 Chapter 8: Privilege Modes 227 Privilege Modes 227 Interface Terminology 230 Exceptions, Interrupts, Traps and Trap Handlers 234 Control and Status Registers (CSRs) 235 CSR Listing 237 Instructions to Read/Write the CSRs 241 Basic CSRs: CYCLE, TIME, INSTRET 246 CSR Register Mirroring 249 An Overview of Important CSRs 252 Exception Processing and Invoking a Trap Handler 257 The Status Register 268 Additional CSRs 280 System Call and Return Instructions 284 Chapter 9: Virtual Memory 288 Physical Memory Attributes (PMAs) 288 Cache PMAs 291 PMA Enforcement 291 Virtual Memory 296 Sv32 (Two-Level Page Tables) 302 The Sv32 Page Table Algorithm 309 Sv39 (Three-Level Page Tables) 311 Sv48 (Four-Level Page Tables) 313 Chapter 10: What is Not Covered 316 The Decimal Floating Point Extension (“L”) 316 The Bit Manipulation Extension (“B”) 316 The Dynamically Translated Languages Extension (“J”) 316 The Transactional Memory Extension (“T”) 316 The Packed SIMD Extension (“P”) 317 RISC-V Architecture Summary / Porter Page S4 of S323 Table of Contents The Vector SIMD Extension (“V”) 317 Performance Monitoring 317 Debug/Trace Mode 318 Acronym List 319 About the Author 323 RISC-V Architecture Summary / Porter Page S5 of S323 List of Instructions Add Immediate 38 Add Immediate Word 39 Add Immediate Double 40 Add 41 Add Word 42 Add Double 42 Subtract 45 Subtract Word 46 Subtract Double 46 Sign Extend Word to Doubleword 47 Sign Extend Doubleword to Quadword 47 Negate 48 Negate Word 48 Negate Doubleword 49 And Immediate 49 And 49 Or Immediate 50 Or 50 Xor Immediate 50 Xor 51 Not 51 Shift Left Logical Immediate 52 Shift Left Logical 52 Shift Right Logical Immediate 53 Shift Right Logical 53 Shift Right Arithmetic Immediate 54 Shift Right Arithmetic 54 Shift Instructions for RV64 and RV128 56 Nop 57 Move (Register to Register) 57 Load Upper Immediate 58 Load Immediate 58 Add Upper Immediate to PC 59 Load Address 60 Set If Less Than (Signed) 61 Set Less Than Immediate (Signed) 61 Set If Greater Than (Signed) 62 RISC-V Architecture Summary / Porter Page S6 of S323 List of Instructions Set If Less Than (Unsigned) 62 Set Less Than Immediate (Unsigned) 62 Set If Greater Than (Unsigned) 63 Set If Equal To Zero 63 Set If Not Equal To Zero 64 Set If Less Than Zero (signed) 64 Set If Greater Than Zero (signed) 65 Branch if Equal 65 Branch if Not Equal 67 Branch if Less Than (Signed) 67 Branch if Less Than Or Equal (Signed) 67 Branch if Greater Than (Signed) 68 Branch if Greater Than Or Equal (Signed) 68 Branch if Less Than (Unsigned) 69 Branch if Less Than Or Equal (Unsigned) 69 Branch if Greater Than (Unsigned) 70 Branch if Greater Than Or Equal (Unsigned) 70 Jump And Link (Short-Distance CALL) 71 Jump (Short-Distance) 73 Jump And Link Register 73 Jump Register 74 Return 74 Call Faraway Subroutine 75 Tail Call (Faraway Subroutine) / Long-Distance Jump 77 Load Byte (Signed) 78 Load Byte (Unsigned) 78 Load Halfword (Signed) 79 Load Halfword (Unsigned) 79 Load Word (Signed) 80 Load Word (Unsigned) 81 Load Doubleword (Signed) 81 Load Doubleword (Unsigned) 82 Load Quadword 83 Store Byte 83 Store Halfword 84 Store Word 85 Store Doubleword 85 Store Quadword 86 Multiply 89 Multiply – High Bits (Signed) 91 RISC-V Architecture Summary / Porter Page S7 of S323 List of Instructions Multiply – High Bits (Unsigned) 91 Multiply – High Bits (Signed and Unsigned) 92 Multiply Word 94 Divide (Signed) 98 Divide (Unsigned) 98 Remainder (Signed) 99 Remainder (Unsigned) 99 Divide Word (Signed) 100 Divide Word (Unsigned) 100 Remainder Word (Signed) 101 Remainder Word (Unsigned) 101 Floating Load (Word) 124 Floating Load (Double) 125 Floating Load (Quad) 125 Floating Store (Word) 126 Floating Store (Double) 126 Floating Store (Quad) 127 Floating Add 127 Floating Subtract 128 Floating Multiply 129 Floating Divide 129 Floating Minimum 130 Floating Maximum 130 Floating Square Root 131 Floating Fused Multiply-Add 132 Floating Fused Multiply-Subtract 132 Floating Fused Multiply-Add / Subtract (Quad) 133 Floating Point Conversion (Integer to/from Single Precision) 134 Floating Point Conversion (Integer to/from Double Precision) 135 Floating Point Conversion (Integer to/from Quad Precision) 136 Floating Point Conversion (Single/Double to/from Quad Precision) 136 Floating Sign Injection (Single Precision) 137 Floating Sign Injection (Double Precision) 138 Floating Sign Injection (Double Precision) 138 Floating Move 139 Floating Negate 139 Floating Absolute Value 140 Floating Move To/From Integer Register (Single Precision) 140 Floating Move To/From Integer Register (Double Precision) 141 Floating Point Comparison 142 RISC-V Architecture Summary / Porter Page S8 of S323 List of Instructions Floating Point Classify 144 C.LW - Load Word 162 C.LW - Load Doubleword 162 C.LQ - Load Quadword 163 C.FLW - Load Single Float 164 C.FLD - Load Double Float 164 C.LWSP - Load Word from Stack Frame 165 C.LDSP - Load Doubleword from Stack Frame 166 C.LQSP - Load Quadword from Stack Frame 166 C.FLWSP - Load Single Float from Stack Frame 167 C.FLDSP - Load Double Float from Stack Frame 168 C.SW - Store Word 168 C.SD - Store Doubleword 169 C.SQ - Store Quadword 170 C.FSW - Store Single Float 170 C.FSD - Store Double Float 171 C.SWSP - Store Word to Stack Frame 172 C.SDSP - Store Doubleword to Stack Frame 172 C.SQSP - Store Quadword to Stack Frame 173 C.FSWSP - Store Single Float to Stack Frame 173 C.FSDSP - Store Double Float to Stack Frame 174 C.J - Jump (PC-relative) 175 C.JAL - Jump and Link / Call (PC-relative) 175 C.JR - Jump Register 176 C.JALR - Jump Register and Link / Call 176 C.BEQZ - Branch if Zero (PC-relative) 177 C.BNEQZ - Branch if Not Zero (PC-relative) 177 C.LI - Load Immediate 178 C.LUI - Load Upper Immediate 179 C.ADDI - Add Immediate 180 C.ADDIW - Add Immediate
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